JP2002009827A - Router and method for protecting memory from leakage - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent the leakage of a memory storing packets in a store-and- forward router with a simple configuration. SOLUTION: An interface 2 transmits a transmission slot retrieval request including packet interface to a retrieval card 4 in order to decide a destination slot of a packet received from a line side. A detection circuit 6 can also obtain the same packet information. The detection circuit 6 measures a time when the destination slot information with respect to the packet information is received by an interface 3 from the retrieval card 4. When a prescribed time reaches before the slot information is received by the interface 3, it is discriminated that a hardware fault takes place, the detection circuit 6 gives an instruction to the interface 2 to release the memory area of a memory 1 storing the packet. The interface 2 uses a drop function provided substantially thereto to release the memory area.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a router for forcibly opening a memory area in which invalidated packets are stored, and a memory leak protection method.
The present invention relates to memory leak protection for a memory provided in an AND-forward router.

[0002]

2. Description of the Related Art An example of this kind of prior art is disclosed in JP-A-11-33126.
Since it is described as “communication device, communication method, and recording medium” in Japanese Patent Publication No. 0, the technology will be described with reference to the drawings in the publication.

FIG. 15 is an overall configuration diagram of a general device (router) for forwarding (transferring) a packet. The router includes two line cards 10 and 20 for transmitting and receiving packets via a line, a forwarding engine 30 for forwarding packets received by the line cards 10 and 20, a line card 10,
A crossbar switch (hereinafter, referred to as “switch”) 40 interconnecting the forwarding engine 20 and the forwarding engine 30
It is composed of

[0004] The line card 10 (20) includes a transmission line corresponding unit 11 (21) and a reception line corresponding unit 12 (22).
And a FSU (From Switch Unit) 13 (23) for receiving and buffering a page from the switch 40, and a TSU (To Switch Unit) for transmitting the page sent from the receiving-side line corresponding unit 12 (22) to the switch 40. Switch Unit) 1
4 (24).

[0005] The forwarding engine 30 is an FSU.
13 (23), FSU3 having the same configuration as TSU14 (24)
3, a forwarding processor 35 for performing a forwarding process based on a route page request received from the FSU 33 and a routing table.

FIG. 16 shows the FSU of the router shown in FIG.
13 (23 and 33 have the same configuration). In FIG. 16, when the page receiving unit 42 receives the page data constituting the packet, the page data is supplied to the object generating unit 45 and the payload memory 43, and the address that can be assigned to the payload memory 43 by the address converting unit 41. Generated. The object generation unit 45 generates only one object including the address for each packet, and stores the page data in the address of the payload memory 43 in a list structure. When detecting a memory leak due to a loss of an object or the like, the memory leak detection unit 44 forcibly releases an area of a corresponding address of the payload memory 43.
This release is performed when the expiration date set for the object elapses.

With this configuration, when the address information of the object is lost due to disturbance such as noise, the page allocated to the payload memory is not released permanently (this is called a memory leak), and the payload is deleted. This reduces the number of pages that can be allocated in the memory and prevents the memory from being used effectively, thereby preventing the performance of the device from being reduced.

[0008]

However, in the above-mentioned prior art, when the memory leak detection unit detects the occurrence of a memory leak, the memory area is set to an unused state and the page is released. However, there is a problem that it is necessary to add a data area release function to the section.

An object of the present invention is to provide a router and a memory leak protection method which do not require the addition of a data area release function.

[0010]

According to a first aspect of the present invention, when a destination slot of a packet received from a communication line cannot be searched, an area of a memory storing the packet is released. When a predetermined memory leak protection required state is entered by using the drop function, the memory area is released until the memory leak required protection state is released.

A router according to a second aspect of the present invention comprises a plurality of line cards connected to a communication line and a routing table search card (4) for searching a destination slot of a packet received by the line card from the communication line. In the router interconnected by the switch (5), each line card includes a memory (1) for storing a packet received from a communication line and a head address of a packet received for searching for a destination slot in a routing table search card. (4) A transmitting-side switch interface (2) for transmitting a received packet to the searched destination slot via the crossbar switch (5), and a searched destination received via the crossbus switch (5). The slot is sent to the transmitting switch interface (2), and the transmitted packet is sent to the communication line. After the head address of the received packet is input to the receiving switch interface (3) to be notified and the transmitting switch interface (2), the searched destination slot is notified by the receiving switch interface (3). A memory leak detection circuit (6) for detecting the occurrence of a memory leak based on the time up to and issuing a drop instruction to the reception-side switch interface (3);
Upon receiving a drop notification based on a drop instruction from the receiving-side switch interface (3), the memory area is opened in the memory (1).

A third aspect of the present invention is characterized in that the memory leak detection circuit (6) detects the occurrence of a memory leak based on the amount of received packets stored in the memory (1).

According to the present invention, a crossbar switch (5) includes a plurality of line cards connected to a communication line and a routing table search card (4) for searching a destination slot of a packet received by the line card from the communication line. On memory leak protection in routers interconnected by.
First, the packet received from the communication line is stored in the memory (1). The transmission switch interface (2) of the line card transmits the head address of the packet received for searching for the destination slot to the routing table search card (4) via the crossbar switch (5). The routing table search card (4) searches for a destination slot according to the head address. The receiving switch interface (3) of the line card receives the searched destination slot via the crossbar switch (5) and notifies the transmitting switch interface (2). The transmission-side switch interface (2) transmits the packet stored in the memory (1) to the destination slot via the crossbar switch (5). Switch interface on the receiving side (3)
Receives the transmitted packet via the crossbar switch (5) and transmits the packet to the communication line. The memory leak detection circuit (6) operates from the input of the head address of the received packet to the transmission-side switch interface (2) to the notification of the searched destination slot by the reception-side switch interface (3). The occurrence of a memory leak is detected depending on the time, and a drop instruction is issued. The receiving switch interface (3) notifies the transmitting switch interface (2) of the drop based on the drop instruction.
Upon receiving the drop notification, the transmitting-side switch interface (2) releases the memory area of the memory (1).

The memory leak detection circuit (6) may detect a memory leak based on the amount of packets stored in the memory (1).

According to the present invention, the drop function inherently used so that the packet start address does not hit the routing table when searching for the destination slot is provided in the memory area for protecting the memory leak. Since it is determined that the router is used, a router having a simple configuration can be provided, and the method can be simplified.

[0016]

Next, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing a configuration example of an embodiment of the router of the present invention. As for the present invention, FIG.
5 is applied, the memory 1, the switch interface 2, the switch interface 3, and the memory leak detector 6 in FIG. 1 constitute the line card 10 or 20 in FIG.
15 corresponds to the forwarding engine 30 in FIG. 15, and the switch 5 in FIG. 1 corresponds to the switch 40 in FIG.

The memory 1 holds a packet received from the line side. The switch interface 2 receives the packet information for determining the destination slot from the memory 1 and transmits the packet information to the routing table search card 4 via the switch 5 as a destination slot search request. In addition, a packet from the memory 1 is transmitted to a destination slot in accordance with an instruction from the switch interface 3, and a memory area of the packet held in the memory 1 is released. The switch interface 3 notifies the switch interface 2 of destination information (consisting of a destination and a packet head address) received from the routing table search card 4 via the switch 5 and, when a packet is received via the switch 5, Send to line side. The routing table search card 4 searches the transmission slot search request received from the switch interface 2 via the switch 5 by using a routing table having a built-in destination slot of the packet, and transmits the destination information to the switch interface 3. The switch 5 connects slots for transmission and reception.

Next, a general operation will be described. The packet received from the line side is held in the memory 1 until it decides to which slot to send. At this time, the packet is divided into units of data width of the memory 1, and a link list is formed and held. To determine the destination of the packet held in the memory 1, the switch interface 2 receives the head data of the packet and the head address of the packet from the memory 1. The destination IP address and the packet start address indicated in the packet start data are transmitted to the routing table search card 4. The routing table search card 4 searches for the destination slot number from the IP address received from the switch interface 2, and uses the searched destination slot number and packet start address as the routing information as the switch 5.
Via the switch interface 3.

When the switch interface 3 receives the destination slot number and the packet start address from the routing table search card 4, it notifies the switch interface 2 of them. When a packet transmitted from another card is received via the switch 5, the packet is transmitted to the line side. Switch interface 2
When the destination slot number and the packet start address are received from the switch interface 3, the packets of the link list including the packet start address are sequentially transmitted to the destination slot number via the switch 5, and the memory of the memory 1 used by the packet is used. Release the area.

When a packet P is received from a line, the packet P is divided for each data width of the memory 1 as shown in FIG. Here, it is assumed to be separated from A to D. The data of A to D is held at unused addresses 00h to 03h of the memory 1. At the time of holding, a pointer is set so as to form a linked list of data A to D. Follow this pointer sequentially from 00h,
By reading the data of h → 01h → 02h → 03h, the original packet P can be formed. The data whose pointer value indicates 00h indicates the last data of the packet. When the packet is actually transmitted, the head address 00h for the packet so that the packet can be sent in order from the beginning of the packet.
Is kept.

Next, in order to determine the destination slot of the packet P, the switch interface 2 receives the head address 00h and the packet head data A of the packet P from the memory 1 as shown in FIG. The switch interface 2 extracts the destination IP address E from the packet head data A and sends it to the routing table search card 4 together with the packet head address 00. As shown in FIG. 7, the routing table search card 4 receives the packet start address 00h from the switch interface 2.
And the IP address E. Therefore, the IP address E
To retrieve the destination slot F from the routing table, and transmits it to the switch interface 3 together with the packet start address 00h. The switch interface 3
As shown in FIG. 5, the destination slot F and the packet start address 00h are received and notified to the switch interface 2. The switch interface 2 has a destination slot F
The packet P generating the link list is sequentially transmitted from the start address 00h to the memory area of the memory 1 used by the packet P (addresses 00h, 01h, 02
h, 03h).

Next, the memory leak search circuit 6 receives the packet information from the memory 1 and measures the time during which the packet is held in the memory 1 until the destination is determined in the routing table search card 4, thereby obtaining the memory information. A process for determining whether or not a leak has occurred is performed. Then, when it is determined that the packet is a memory leak, a drop instruction is issued to the switch interface 3 so as to release an area of the memory 1 for the packet. When receiving the drop instruction from the memory leak detection circuit 6, the switch interface 3
The switch interface 2 is notified of the drop. The switch interface 2 releases the memory area of the memory 1 according to the drop notification received from the switch interface 3. When the destination of the packet is determined, the switch interface 3 notifies the memory leak detection circuit 6 of the transmission data information.

FIG. 2 is a block diagram showing a configuration example of the memory leak detection circuit 6. The memory 8 holds the time during which the packet is held in the memory 1. This value is C
It is counted up at a certain interval by the PU 7.
Further, based on the time when the packet is held in the memory 1 based on the value in the memory 8, the CPU 7 issues a drop instruction to the switch interface 3 to release the memory area for the packet held for a certain period of time.

Next, the operation of the circuit of FIG. 2 will be described with reference to FIG. The packet received from the line side is held in the memory 1, and the switch interface 2 receives the packet information and the head address of the packet in order to determine the destination slot for the packet. At the same time, the memory leak detection circuit 6 receives the packet start address to measure the time until the destination is determined.
The CPU 7 sets the value of the address of the memory 8 that is the same as the received packet head address to “1”. If the value is not "0" for all the addresses of the memory 8 at regular intervals, the CPU 7 increments the value by "1". Memory 8
Indicates the time during which a packet having that address as the packet start address is stored in the memory 1. The CPU 7 determines from the value held in the memory 8 whether or not the packet has a memory leak.

When the switch interface 3 receives the destination slot and the packet start address from the routing table search card 4, the memory area of the memory 1 is released by the switch interface 2. When the memory area of the memory 1 is released, the CPU 7 must clear the time held in the memory 8 for the packet whose destination has been determined. Therefore, when the CPU 7 receives, from the switch interface 3, the packet start address determined as the transmission destination as the transmission information address, the CPU 7 sets the value of the same address as the packet start address in the memory 8 to “0”.

While the switch interface 3 does not receive the destination slot from the routing table search card 4, the value of the memory 8 continues to be counted up. When the value of the memory 8 reaches a certain value, the CPU 7 determines that a memory leak has occurred for a packet having that address as the packet start address. As a result, a process of releasing the memory area of the memory 1 used by the packet is performed. When determining that the memory leaks, the CPU 7 notifies the interface 3 of the packet start address, and sends an instruction to drop the packet.
When receiving the packet start address and the drop instruction, the switch interface 3 notifies the switch interface 2 to drop the packet start address, and the switch interface 2 drops the packet. Therefore, the memory area used in the memory 1 for the packet is released.

Next, a more specific description will be given using the packet data shown in FIG.

As shown in FIG. 3, the packet P received from the line is divided into A to D for each data width of the memory 1 and held at addresses 00h to 03h of the memory 1.
In order to determine the destination slot of the packet P, the switch interface 2 stores the packet P head address 00h and the packet head data A in the memory 1 as shown in FIG.
, The memory leak detection circuit 6 also receives the packet start address 00h. The CPU 7 shown in FIG.
As shown in the figure, the data value of the address 00h of the memory 8 corresponding to the received packet start address 00h is set to "1".
To When the data value is not “0” for all addresses of the memory 8 at a constant interval (here, 1 second interval), the CPU 7 increments the value by “1”.

First, an example in which a destination slot is determined will be described. The switch interface 3 receives the destination slot F for the packet P and the packet start address 00h from the routing table search card 4 as shown in FIG. Switch interface 3
Notifies the switch interface 2 of the packet start address and at the same time notifies the memory leak detection circuit 6 of the packet start address 00h because the destination slot of the packet has been determined. Switch interface 2
Reads the packet P with the packet start address 00h from the memory 1 and sends it to the switch 5. The switch 5 sends the packet P to the switch interface 3 in the destination slot F, and the packet P is sent out to the line. When the packet P is transmitted, the areas of 00h, 01h, 02h and 03h are released by the switch interface 2, and the CPU 7 of the memory leak detection circuit 6 sends the packet start address received from the switch interface 3 as shown in FIG. 00h, the address 00 of the memory 8
The value of h is set to “0”.

Next, an example in which the destination slot is not determined will be described. This is a case where a destination slot cannot be searched in the routing table search card 4 due to some failure. While the switch interface 3 does not receive the destination slot from the routing table search card 4, the value of the memory 8 continues to be incremented. As a result, when the value of the memory 8 reaches a certain value (here, 10 seconds), as shown in FIG. 10, the CPU 7 determines that a memory leak has occurred for the packet having the address 00h as the top address. , The packet head address 00h in the switch interface 3
And tells it to drop the packet. After the drop instruction, the value that has reached a certain value is returned to “0”. The switch interface 3, as shown in FIG.
When the packet head address 00h and the drop instruction are received, the switch interface 2 is notified to drop the packet head address 00h. The packet is discarded by the switch interface 2 and the addresses 00h, 01h, 02h and 03 used in the memory 1 are discarded.
The memory area of h is released.

According to this embodiment, the drop function inherently provided in the router is used to discard a packet whose destination slot is not determined within a predetermined time. The drop function is a function of releasing a storage memory area of a packet whose destination slot cannot be searched in the routing table search card 4.

Further, since the memory leak detection circuit 6 is controlled by a program, the change of the time for determining a memory leak can be easily realized by changing the program.

Next, another embodiment of the router according to the present invention will be described. In the first embodiment, the memory leak is determined based on the time required for the destination slot to be determined. In the second embodiment, the memory leak is determined based on the usage amount of the memory 1. is there. That is, until the amount of use of the memory 1 holding the packet exceeds a certain value, even if the destination slot is not determined, the packet is kept held in the memory 1.

Memory leak detection circuit 6 in second embodiment
Receives the packet start address and the number of addresses used by the packet in the memory 1 from the memory 1. In the example shown in FIG. 3, the packet start address for the packet P is “00h”, and the number of addresses used in the memory 1 is “4”. The CPU 7 sets the packet start address 00
The used address number “4” of the packet is written to the same address of the memory 8 as that of the address h. Then, a link list in which the head addresses of the packets using the memory 1 are linked in the order in which the packets are held in the memory 1 is formed in the memory 8. Also, the total number of addresses used in the memory 1 is stored so that the user can know how much the memory 1 is used.

When the switch interface 3 receives the destination slot from the routing table search card 4, the CPU 7 deletes the packet start address received from the link list in the memory 8, and calculates the number of addresses used of the packet from the total number of addresses used. Number minus 1 is memory 1
Is the total number of addresses used. On the other hand, when the destination slot is not determined and the total number of addresses used in the memory 1 reaches a certain value, the packet head addresses are sequentially deleted from the head of the link list formed in the memory 8 and the number of the used addresses is reduced. To reduce the total number of addresses used. Then, it instructs the switch interface 3 to drop this packet. This is repeated until the total number of addresses used in the memory 1 becomes equal to or less than a certain value.

It is assumed that two packets have already been stored in the memory 1, and that these packets are denoted by P1 and P2, respectively. Assume that the packet head address is 00h for the packet P1, and the four addresses 00h, 01h, 02h and 03h are used. Further, after the memo packet P1 is stored in the memory 1, the packet P2 is set to 04h, 05h and 06h, with the packet start address set to 04h.
Packets P1, P2
In both cases, it is assumed that the destination of the packet has not been determined.
At this time, as shown in FIG. 11, the memory leak detection circuit 6 forms a link list with the packet head addresses of the packets P1 and P2 in the memory 8, and the total number of addresses used is 4 + 3 = 7.

Here, the packet P3 is newly stored in the memory 1 with the packet start address set to 07h and the address 07h.
And 08h, the CPU 7 sends the packet P3
, The packet head address 07h and the number of used addresses “2” are received. The number of used addresses “2” is written to the address 07h of the memory 8, and the value of the total number of used addresses is set to 7 + 2 = 9. Further, in order to add to the end of the formed link list, the pointer of the last address 04h is rewritten from 00h to 07h.

Here, it is assumed that the reference value of the total number of used addresses at which the CPU 7 determines that there is a memory leak is 10. In this state shown in FIG. 12, since the total number of addresses used is 9 and has not reached the reference value, the CPU 7 is waiting for the destination of the packet to be determined. Then, the packet head address 00
When the destination of the packet h is determined, the packet head address 00h is received from the switch interface 3, and as shown in FIG. 13, the pointer of the address 00h of the memory 8 and the number of addresses used are cleared to 00h and “0”, respectively. , Will be removed from the linked list. Also, the total number of used addresses is reduced from 9 to 5 because it is reduced by the used address number “4” of the address 00h.

Next, the reference value of the total number of addresses used by the CPU 7 to judge a memory leak is "8". In this case, in the state shown in FIG. 12, the total number of addresses used is 9 and exceeds the reference value 8. Therefore, as shown in FIG. 14, the CPU 7 determines that there is a memory leak, notifies the switch interface 3 of the head address 00h of the link list formed in the memory 8, and notifies the switch interface 3 of dropping at the same time. At this time, the pointer of the address 00h of the memory 8 and the number of addresses used are cleared to 00h and “0”, respectively, and are deleted from the link list. Further, the total number of used addresses is reduced by the number of used addresses “4” at the address 00h, and the total number of used addresses is 9 → 5. If the total number of addresses to be used still exceeds the reference value “8”, the same processing is performed sequentially from the link list until the total number becomes equal to or less than the reference value.

Since the second embodiment does not judge that a memory leak occurs while a memory holding a packet has a free space, even if a considerable amount of time is required to determine a destination slot, the packet is not leaked. Can also be transmitted.

A program for causing a computer to execute the memory leak protection method described above is stored in a semiconductor memory, a floppy (registered trademark) disk, or a CD-R.
The program may be recorded on a recording medium such as an OM and read and executed by a computer constituting a router.

[0043]

The first effect of the present invention is that the memory area of the memory for storing the packet received by the store-and-forward router is released by the inherent drop function. This means that the memory work can be protected with a simple configuration.

The second effect is that, because a program is used to determine whether a memory leak has occurred, by changing the program, the reference setting for determining a memory leak can be easily changed. It is.
This is because the time setting can be changed by changing the program because the program determines whether or not there is a memory leak.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of a router according to the present invention.

FIG. 2 is a block diagram of a memory leak detection circuit.

FIG. 3 is a diagram showing a storage state of packet data in a memory 1;

FIG. 4 is a data flow diagram in the switch interface 2.

FIG. 5 shows a switch 4 in the switch interface 3
Of data flow from

FIG. 6 is a flow chart of data from the memory leak detection circuit 6 in the switch interface 3;

FIG. 7 is a flow chart of data in the routing table 4;

FIG. 8 is a flow chart of data from the memory 1 in the memory leak detection circuit 6;

FIG. 9 is a flow chart of data from the switch interface 3 in the memory leak detection circuit 6;

FIG. 10 is a flow chart of memory data to the switch interface 3 in the memory leak detection circuit 6;

FIG. 11 is a diagram showing a data storage state in a memory 8 of a memory leak detection circuit 6 in another embodiment of the router of the present invention.

FIG. 12 is a flow chart of data from the memory 1 in the memory leak detection circuit 6 in another embodiment of the router of the present invention.

FIG. 13 is a flow chart of data from the switch interface 3 in the memory leak detection circuit 6 in another embodiment of the router of the present invention.

FIG. 14 is a diagram showing the flow of data to the switch interface 3 in the memory leak detection circuit 6 in another embodiment of the router of the present invention.

FIG. 15 is a general block diagram of a router to which the present invention is applied;

FIG. 16 is a block diagram showing a conventional embodiment.

[Explanation of symbols]

 1 Memory 2 Switch Interface 3 Switch Interface 4 Routing Table Search Card 5 Switch 6 Memory Leak Detection Circuit 7 CPU 8 Memory 10 Line Card 11 Transmitting Line Corresponding Unit 12 Receiving Line Corresponding Unit 13 FSU 14 TSU 20 Line Card 21 Transmitting Line Corresponding unit 22 Receiving line corresponding unit 23 FSU 24 TSU 30 Forward engine 33 FSU 34 TSU 35 Forwarding processor 40 Switch

Claims (6)

[Claims] When a destination slot of a packet received from a communication line cannot be searched, a predetermined memory leak is performed by using a drop function provided for releasing an area of a memory storing the packet. A router that releases the memory area until the memory leak protection required state is released when the protection required state is entered. 2. A router in which a plurality of line cards connected to a communication line and a routing table search card for searching a destination slot of a packet received by the line card from the communication line are interconnected by a crossbar switch. Each of the line cards includes a memory for storing a packet received from the communication line, a routing table search card for a head address of the received packet for searching for the destination slot, and a search for the received packet. A transmission-side switch interface for transmitting to the destination slot via the crossbar switch, and the retrieved destination slot received via the cross-bus switch to the transmission-side switch interface,
A receiving switch interface for notifying the transmitted packet to the communication line, and a head address of the received packet is input to the transmitting switch interface. A memory leak detection circuit for detecting the occurrence of a memory leak by the time until the destination slot is notified, and issuing a drop instruction to the receiving switch interface. Upon receiving a drop notification based on an instruction, the router releases the memory area of the memory. 3. The memory leak detection circuit according to claim 1, wherein: a head address of the received packet is input to the transmission-side switch interface until the received destination slot is notified by the reception-side switch interface. 3. The router according to claim 2, wherein instead of detecting the occurrence of a memory leak based on the time, the occurrence of a memory leak is detected based on the amount of received packets stored in the memory. 4. A memory in a router in which a plurality of line cards connected to a communication line and a routing table search card for searching a destination slot of a packet received by the line card from the communication line are interconnected by a crossbar switch. A leak protection method, comprising: storing a packet received from a communication line in a memory; and
Transmitting a head address of the received packet to the routing table search card via the crossbar switch to search for the destination slot; and the routing table search card searches the destination slot based on the head address. Procedure, the receiving switch interface of the line card,
Receiving the retrieved destination slot via the crossbar switch and notifying the transmitting side switch interface, the transmitting side switch interface directs the packet stored in the memory to the destination slot, and A step of transmitting via a switch; a step of transmitting the packet to the communication line when the receiving side switch interface receives the transmitted packet via the crossbar switch; and A step of detecting the occurrence of a memory leak and instructing a drop instruction by the time from when the head address of the received packet is input until the notified destination slot is notified by the receiving-side switch interface; The receiving switch interface is A step of performing a drop notification to the transmission-side switch interface based on the drop instruction; and a step of releasing the memory area of the memory when the transmission-side switch interface receives the drop notification. Memory leak protection method. 5. The memory leak detection circuit according to claim 1, wherein a start address of the received packet is input to the transmission-side switch interface, and the memory switch detection circuit notifies the searched destination slot by the reception-side switch interface. The memory leak detection circuit detects the occurrence of a memory leak based on the amount of received packets stored in the memory and issues a drop instruction in place of the procedure of detecting the occurrence of a memory leak based on the time and performing the drop instruction. 5. The memory leak protection method according to claim 4, further comprising a step of performing the procedure. 6. A computer-readable recording medium on which a program for causing a computer to execute the memory leak protection method according to claim 4 or 5 is recorded.