JP2001518694A - Method and apparatus for probing an integrated circuit through the backside of an integrated circuit die - Google Patents

Abstract

(57) Abstract: A method and apparatus for probing signals passing from an integrated circuit through the backside of an integrated circuit die (401). The passive diffusion (405) is located in the semiconductor substrate of the flip-chip mounted integrated circuit die. The passive diffusion unit is coupled to the signal line (409) through a contact (407). The signal lines carry the integrated circuit signal of interest. In embodiments, the disclosed passive spreading unit is oversized to reduce the attenuation of the signal obtained from the passive spreading unit. In addition, the disclosed passive diffusion is laterally spaced from the diffusion near the semiconductor substrate of the integrated circuit, damaging nearby structures in the integrated circuit die, such as other diffusions in the exposure process. This allows the passive diffusion to be exposed while reducing the risk of erosion. Further, the disclosed passive diffuser is laterally spaced from nearby diffusers to reduce crosstalk interference from nearby diffusers.

Description

DETAILED DESCRIPTION OF THE INVENTION

(Related Application) The present application is based on “A Method of Access” filed on October 2, 1996.
ssing the Circuitry on a Semiconductor
or Substrate from the Bottom of the
No. 08 / 724,223, entitled "Semiconductor Substrate", now abandoned November 2, 1994.
Assigned to the assignee of the present application, which is a continuation-in-part of 08 / 344,149 filed on 3rd.

[0002] The present application is further directed to "Method and A" filed on December 12, 1996.
pparatus Using an Infrared Laser Bas
ed Optical Probe for Measuring Elect
ric Fields Directly From Active Regi
No. 08 / 766,149 entitled "ons in an Integrated Circuit" and is assigned to the assignee of the present application.

[0003] The present application is further directed to "Method and A" filed on December 20, 1996.
pparatus for Endpointing While Milli
No. 08 / 771,712, entitled "ng an Integrated Circuit" and assigned to the assignee of the present application.

[0004] The present application further discloses a method and application filed on _________________
pparatus Providing a Circuit Edit St
Structure Through the Back Side of an
Related to co-pending application no. _____________, entitled "Integrated Circuit Die," assigned to the assignee of the present application.

[0005] The present application is further directed to a "Method and A"
pparatus For Performing a Circuit Ed
it Through the Back Side of an Integ
co-pending application entitled "rated Circuit Die"
___________ and assigned to the assignee of the present application.

[0006] The present application is further directed to a "Method and A"
pparatus Providing a Mechanical Prob
e Structure in an Integrated Circuit
Die, co-pending application No. ___________, assigned to the assignee of the present application.

FIELD OF THE INVENTION [0007] The present invention relates generally to integrated circuit testing, and specifically to methods and apparatus for probing integrated circuits.

Background Information Newly designed integrated circuits must be thoroughly tested after being formed on a semiconductor substrate to ensure that the circuit operates as designed. Incorrectly functioning portions of the integrated circuit are identified and corrected by modifying the integrated circuit design. This process of testing an integrated circuit to identify design problems is called debugging. After debugging the integrated circuit and correcting design problems, the final fully functional integrated circuit design is used to mass produce the integrated circuit in a consumer manufacturing environment.

[0009] The debugging process probes several internal electrical nodes within an integrated circuit to obtain important electrical data from the integrated circuit, such as voltage levels, timing information, current levels, thermal information, and the like. Sometimes there is a need. A typical integrated circuit device includes multiple layers of metal interconnect. Generally, the first layer of metal interconnects of an integrated circuit device has electrical data that is most useful for debugging. The metal interconnect lines of the first metal layer are located closest to the semiconductor substrate and are typically directly coupled to key components of the integrated circuit device, such as transistors, resistors, capacitors, and the like. What the designer analyzes most during the debugging process is the electrical data received, manipulated, and transmitted by these components.

FIG. 1A illustrates a metal interconnect 11 located along the periphery of an integrated circuit die 105.
3 is an illustration of an integrated circuit package 101 including wire bonds 103 that electrically connect the integrated circuit connection to pins 107 of the package substrate 111 through 3. FIG. FIG. 1A
The metal interconnect 113 is coupled to the diffusion region 117 through a metal contact 109, as shown in FIG. In some cases, diffusion region 117 may be used as a transistor, resistor, capacitor, etc. in an integrated circuit device. As shown in FIG. 1A, a probe tool 115 can be used to probe the metal interconnect 113 through the front side 119 of the integrated circuit die 105 and obtain electrical data from the integrated circuit die 105.

The wire bond design of the integrated circuit package 101 of FIG. 1A has several disadvantages. First, as the integration density and complexity of the integrated circuit die 105 increase, the number of wire bonds 103 required to control the function of the integrated circuit die 105 must also increase. However, there is a limited number of wire bonds 103 that can fit around the periphery of the integrated circuit die 105. One way to increase the number of wire bonds 103 that fit around the periphery of the integrated circuit die 105 is to increase the overall size of the integrated circuit die 105, thereby increasing the peripheral area. Unfortunately, increasing the overall size of the integrated circuit die 105, in turn, significantly increases the cost of manufacturing the integrated circuit.

[0012] Another disadvantage of the integrated circuit package 101 of FIG.
To electrically couple to bond 103, the active circuitry in integrated circuit die 105 is
The problem is that it must be routed through the electrical interconnect 113 to the area around the integrated circuit die 105. By routing these metal interconnect lines 113 over the integrated circuit die 105 over a relatively long distance, the resistive, capacitive, and inductive effects on these long interconnects 113 can be significant. An overall speed reduction of Further, the inductance of the wire bonds 103 can also severely limit the high frequency operation of integrated circuit devices within the integrated circuit package 101.

While the integrated circuit industry has been striving to increase device speed as well as speed of integrated circuits, there is a trend to use flip-chip technology when packaging complex high speed integrated circuits. Flip chip technology uses control collap
Also referred to as chip connection (C4) packaging.
In flip chip packaging technology, integrated circuit dies have been turned over. This is the opposite of today's integrated circuit packaging methods using wire bond technology, as shown in FIG. 1A. By turning over the integrated circuit, a ball bond can be used to make a direct electrical connection from the bond pad directly to a pin of the flip-chip package.

For clarity, FIG. 1B shows a flip chip package 151 in which the integrated circuit die 155 has been turned over with respect to the wire bond integrated circuit die 105 of FIG. 1A. Compared to the wire bond 103 of FIG. 1A, when using the ball bond 153 of the flip chip package 151, the metal interconnect 159 connects the integrated circuit of the integrated circuit die 155 and the pin 157 of the package substrate 161. Direct connections can be increased. As such, the inductance problem which plagues typical wire bond integrated circuit packaging techniques is reduced.
Unlike wire bond technology, which can only be bonded along the periphery of the integrated circuit die 155, flip chip technology allows the connection to be located anywhere on the surface of the integrated circuit die. As a result, the distribution of inductance power to the integrated circuit is reduced.
This is another major advantage of flip chip technology.

[0015] The result of flipping the integrated circuit die 155 in a flip-chip package 151 that accesses the internal nodes of the integrated circuit die 155 for debugging has been a rather difficult problem. As mentioned above, current debug processes for wire bond technology are based, in part, on probing metal interconnects directly through the front side of an integrated circuit die. However, with flip-chip packaging technology, this frontside methodology is not feasible due to the flipped integrated circuit die.
For example, as shown in FIG. 1B, the package substrate 161 is jammed to access the metal interconnect 159 for the purpose of probing in a conventional manner. Instead, the PN junction forming the diffusion region 163 of the integrated circuit can be accessed through the backside 165 of the semiconductor substrate of the integrated circuit die 155.

FIG. 2 is a schematic diagram example of an integrated circuit 201 including a circuit 203 having inputs 205 and 207 and an output 209. As shown in FIG. 2, input 205 is
11 and input 207 is generated by circuit 213. It will be appreciated that the example schematic shown in FIG. 2 is only one of the myriad different combinations of integrated circuits that can be included in an integrated circuit die.

Assuming that the circuit designer is debugging integrated circuit 201, inputs 205 and 20
It may be desirable to probe the signals from 7 and output 209. In addition, the metal connections associated with input 205, input 207 and output 209 of FIG.
Assume that it corresponds to B metal interconnect 159. In this figure, the metal interconnect 1
59 is disturbed by diffusion region 163 so that metal interconnect 159
Access to is restricted. As a result, circuit designers cannot probe metal interconnects using conventional techniques.

In some cases, input 205, input 2 of FIG. 2 through diffuser region 163 of FIG. 1B.
07 and output 209 also cannot be probed. In particular, the diffusion region 163
Is an active forward biased transistor diffusion, milling through the back surface 165 to the semiconductor substrate of the integrated circuit die 155 for probing purposes and exposing one of the diffusion regions 163 to form a forward biased PN junction Is damaged. further,
The lateral spacing between diffuser regions 163 is often the backside 1 for probing purposes.
It is not enough to mill the semiconductor substrate of integrated circuit die 155 away from 65. For example, because the diffusion regions 163 are closely spaced, exposing a particular diffusion region 163 by milling often unnecessarily destroys nearby structures and / or diffusion regions.

Returning to FIG. 2, note that an electrostatic discharge (ESD) protection diode 217 is coupled between input 207 and ground. As is well known to those skilled in the art,
An ESD protection diode, such as diode 217, may be coupled to the input gate of the transistor in situations where there is no nearby diffusion region that provides a short ESD path from the gate of the transistor to ground. For example, the transistor diffusion region (not shown) of circuit 211 implements a near ESD path at input 205 from the transistor gate to ground. Therefore, no ESD protection diode is located at input 205. In contrast, the diffusion region (not shown) of circuit 213 is relatively far away from the input gate coupled to input 207, thereby increasing the metal to diffusion ratio associated with input 207. Therefore, by placing the ESD protection diode 217 between the input 207 and the ground, it is possible to prevent the occurrence of ESD for the gate coupled to the input 207. Note that there is no ESD protection diode coupled to output 209 since there is no input gate at output 209 that needs to be protected from an ESD event.

In summary, ESD protection diodes, such as diode 217, are typically only placed on integrated circuit inputs with a relatively high metal to diffusion ratio. ESD protection diodes are typically not located in the prior art on integrated circuit outputs or integrated circuit inputs with relatively low metal to diffusion ratios.

In view of the foregoing, what is desired is an improved method and apparatus for probing integrated circuits. With such methods and equipment, the latest flip chip
Signals can be probed through the backside of the packaged integrated circuit. further,
With such methods and equipment, it is also possible to probe both the input and output signals of the integrated circuit.

SUMMARY OF THE INVENTION A method and apparatus for probing integrated circuits is disclosed. In one embodiment, a probe structure is described that includes a signal line disposed in a dielectric isolation layer of an integrated circuit die and a passive diffusion coupled to the signal line. The passive diffusion is located on the semiconductor substrate of the integrated circuit die and is laterally spaced at least about 1.0 microns within the semiconductor substrate from a nearest active diffusion located within the semiconductor substrate of the integrated circuit die. .
Additional features and advantages of the invention will be apparent from the following detailed description, figures, and claims.

The present invention will now be described by way of example and not by way of limitation in the accompanying drawings.

DETAILED DESCRIPTION A method and apparatus for probing integrated circuits is disclosed. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. However, it will be apparent to one skilled in the art that the specific details are not required in order to practice the invention. In other instances, well-known materials or methods have not been described in detail so as not to obscure the present invention. Figures representing embodiments of the present invention are shown in FIGS.
These figures are not intended to limit the invention. The specific steps described herein are only intended to provide a clear understanding of the invention and to illustrate the various embodiments of how to practice the invention to achieve the desired result. And For purposes of this description, a semiconductor substrate may be a substrate that includes any material used in the manufacture of semiconductor devices.

The present invention is directed to a method and apparatus for implementing a novel probe structure that can be used with electron beam, ion beam, mechanical, and other well-known similar probe techniques. As mentioned above, the ability to probe signal lines passing through the front of the integrated circuit die can be used to debug logic, timing, speed paths, or other issues associated with newly developed microprocessors, microcontrollers, memory chips, etc. It is a technique that can help you. As shown in FIGS. 1A and 1B, respectively, the packaging technology continues to transition from wire bond technology to flip chip technology, and it is possible to develop the ability to probe signals through the backside of an integrated circuit die. Is desired.

FIG. 3 illustrates passive probe structures 319, 321 and 323 in accordance with the teachings of the present invention.
FIG. 3 is a schematic diagram of an integrated circuit 301 including: In the illustrated embodiment, integrated circuit 301 is included in a flip-chip mounted integrated circuit die. The integrated circuit 301 has an input 305
, An input 307 and an output 309. Input 305 is coupled to receive the output of circuit 311 and input 307 is coupled to receive the output of circuit 313. Probe structure 319 is coupled at input 305 to the input gate of the transistor, probe structure 321 is coupled at input 307 to the input gate of the transistor, and probe structure 323 is coupled at output 309 to the drain and source of the output transistor. I have. It will be understood that the example schematic shown in FIG. 3 is also just one of the myriad different combinations of integrated circuits that can be probed in accordance with the teachings of the present invention.

If there are probe structures 319, 321 and 323, input 305, input 30
Probe access to 7 and output 309 can be made through the backside of the flip-chip package integrated circuit in accordance with the teachings of the present invention. Without probe structures 319, 321 and 323, input 305, input 307 and output 3
Probe access to 09 is not possible through the back of the integrated circuit die. As already described for FIG. 2, access to the signal lines corresponding to inputs 205, inputs 207 and outputs 209 from the front of the integrated circuit die is interrupted by the package substrate. Further, access to signal lines from the backside of the integrated circuit die may be disturbed by various diffusions in the semiconductor substrate.

It should be noted that in some cases, the ESD protection diode 217 of FIG. 2 may restrict access to the input 207 to some extent. However, ESD
The protection diodes are generally limited to only those integrated circuit inputs having a high metal to diffusion ratio, so there is no similar access to inputs 205 and 209. In addition, as the device density of integrated circuits tends to increase, the ESD protection diodes are shrinking and are tightly packed near other diffusions to minimize the lateral spacing of the integrated circuit dies. As a result, for example, the ESD protection diode 217 of FIG.
It is usually difficult or even impossible to probe signals from ESD protection diodes such as.

The difficulty in using an ESD protection diode as a probe structure is partly due to the signal-to-noise ratio of the probed signal due to the attenuation of the signal picked up on the relatively small diffusion of the ESD protection diode. This is the result of having become low. In addition, it is common to pack diffusions tightly in the semiconductor substrate to minimize lateral spacing, increasing crosstalk interference in the probed signal,
Further, the signal-to-noise ratio is reduced. Moreover, it is also difficult to expose a tightly packed ESD protection diode diffusion from the backside of the integrated circuit die without damaging nearby diffusions and / or structures.

The diffusions of the passive probe points 319, 321 and 323 just described are oversized compared to other diffusions of the semiconductor substrate in order to reduce the attenuation of the signal to be probed. Thus, the signal-to-noise ratio of the signal obtained according to the present invention is increased. In addition, the diffusion regions of the probe structures 319, 321 and 323 have sufficient lateral spacing from other diffusions of the integrated circuit die to allow access from the backside of the integrated circuit die and crosstalk from nearby diffusions. Interference can be reduced and leakage current into the semiconductor substrate can be reduced when the probe structure described herein is exposed according to the teachings of the present invention.

In one embodiment of the present invention, a passive probe structure coupled to the input and output of the integrated circuit is used by the circuit designer using known techniques, such as circuit 303, for use in integrated circuit design. Included in cell library. As such, integrated circuits that include the probe structures described herein can be configured to probe signals from inputs or outputs, depending on whether the passive probe structures described herein are coupled to corresponding inputs or outputs. Is set beforehand at the time of circuit design.

In another embodiment, the probe structures described herein are included in the cell library as independent circuit elements using well-known techniques. In this embodiment, if the circuit designer knows that he wants to probe the signal from the integrated circuit input or output specified at circuit design time, then the circuit designer can now apply to the individual inputs and outputs of the integrated circuit. The described passive probe structure can be included. Using the passive probe structure described here, these probe signals can be acquired through the backside of the flip-chip mounted integrated circuit die.

FIG. 4A illustrates a cross-section of a flip-chip mounted integrated circuit die 401 with a passive probe structure 403 in accordance with the teachings of the present invention. As can be seen from the embodiment shown in FIG. 4A, the probe structure 403 includes a passive diffusion 405 located on the semiconductor substrate of the integrated circuit die 401 coupled to the signal line 409 through a contact 407. For the purposes of this disclosure, a passive diffuser may simply be interpreted as a diffuser located in a semiconductor substrate to define signal access locations. In one embodiment, signal lines 409 are made of a conductive material such as metal, polysilicon, and the like. In one embodiment, the semiconductor substrate of integrated circuit die 401 includes silicon. In another embodiment, signal line 409 is located on the dielectric isolation layer of integrated circuit die 401 and is coupled to active diffusion 411. In other embodiments, active diffusion 411 may be part of a transistor, capacitor, or other integrated circuit element from which an integrated circuit debugger derives a signal. Note that signal line 409 can be coupled to the integrated circuit element from which the circuit designer is trying to retrieve the probe signal. For the purposes of this disclosure, an active diffuser can be interpreted as a diffuser located in a semiconductor substrate that becomes active during normal operation of the integrated circuit.

In one embodiment, passive diffusion 405 is oversized with respect to other active transistor diffusions in the semiconductor substrate. In one embodiment, the passive diffuser 40
5, at least X ² square microns in cross-sectional area, the minimum width is at least X microns. In one embodiment, X is at least 1 micron. By making the passive diffusion unit have a sufficient cross-sectional area, attenuation of the probe signal on the passive diffusion unit 405 at the time of probing is reduced, and the signal-to-noise ratio of the probed signal is increased.

In another embodiment, passive diffuser 405 is laterally spaced from the nearest diffuser, such as active diffusers 411 and 413, by at least Y microns.
In one embodiment, Y is at least 1.0 micron. Due to the lateral spacing of the passive diffusions 405 described herein, crosstalk interference from adjacent diffusions, such as active diffusions 411 and 413, is reduced, and the probe structure 40 is used for probing.
When access is made to the passive diffusion portion 405 from the back surface of the integrated circuit die 401, the diffusion portions near the active diffusion portions 411 and 413 are prevented from being damaged as much as possible.
Probe access to

In one embodiment, probe structure 403 is probed through the backside of a silicon semiconductor substrate using an infrared photon beam probe tool. FIG. 4B shows an embodiment where the probe structure 403 is probed with an infrared laser beam 421. An infrared photon beam probing technique using the backside of a silicon semiconductor substrate is described in "Method and Apparatus Using an Infra" filed on December 12, 1996, which is assigned to the assignee of the present application.
red Laser Based Optical Probe for Me
asuring Electric Fields Directly Fro
m Active Regions in an Integrated Ci
rcuit ”described in co-pending application Ser. No. 08 / 766,149.

In another embodiment of the present invention, probe structure 403 is exposed so as to be accessible for probing. In one embodiment, probe structure 403 may be probed using a particle beam probe tool, such as, for example, an electron beam probe tool, an ion beam probe tool, or a photon beam probe tool. it can. In other embodiments, the probe structure 403 can be accessed using a mechanical probe tool. For a useful technique for using mechanical probes on flip-chip packaged integrated circuit dies, see
“Method” of ______________________________________ as
and Apparatus Providing a Mechanica
l Probe Structure in an Integrated C
described in co-pending application number _______________.

In one embodiment, when the probe structure 403 is exposed for probing,
Flip-chip mounted integrated circuit die 401 is initially thinner in the area above probe structure 403. This aspect of the invention is shown in FIG. 4B, where the back surface portion 415 of the integrated circuit die 401 has been removed from the back surface 419 above the probe structure 403. In one embodiment, the integrated circuit die 401 has been generally thinned to a thickness of about 200 microns using well-known techniques. In other embodiments, the integrated circuit die 401 can be locally trenched in the region above the probe structure 403 using well-known techniques. A useful technique for thinning a flip-chip packaged integrated circuit die and accessing the circuit from the backside of the flip-chip packaged integrated circuit die is now abandoned November 2, 1994.
"A Method of Access," filed October 2, 1996, assigned to the assignee of the present application, which is a continuation of 08 / 344,149 filed on 3rd.
ing the Circuitry on a Semiconductor
Substrate from the Bottom of the Se
co-pending application no.
Note that this is described in U.S. Pat. No. 8,724,223.

After the thinning step shown in FIG. 4B, a portion 417 of the semiconductor substrate above the probe structure 403 is milled to expose the probe structure 403 and
19 to expose the passive diffusion portion 405 and / or the contact 407. This aspect of the invention is shown in FIG. 4C. As can be seen from FIG. 4C, the probe structure 403 can be probed using well-known techniques with the particle beam 423. The particle beam is a photon beam, an ion beam,
A beam, an electron beam or the like may be used.

In one embodiment, probe structure 403 is exposed using well-known cutting techniques, such as, for example, a focused ion beam milling tool. In one embodiment, gallium ions are used in the focused ion beam milling tool. Techniques that help in pointing while milling an integrated circuit are:
“Method, filed December 20, 1996, assigned to the assignee of the present application.
and Apparatus for Providing Endpoin
ting While Milling an Integrated Cir
Note that it is described in co-pending application Ser. No. 08 / 771,712 entitled "quit."

As described with respect to FIG. 4A, increasing the lateral spacing of the passive diffusion 405 from adjacent diffusions, such as active diffusions 411 and 413, allows the probe structure 403 from the back surface 419 to be unimpeded. Because of the accessibility, portions 417 can be removed from the back surface of integrated circuit die 401 without damaging nearby diffusions such as active diffusions 411 and 413 during the milling process as much as possible.
Further, by increasing the lateral spacing, the passive diffusion unit 405 can be
The risk of shorting to ground to the semiconductor substrate near 1 is also reduced. In particular, in one embodiment of the present invention, focused ion beam milling using gallium ions.
The passive diffusion 405 is exposed using a tool. Therefore, the focused ion beam milling tool implants gallium into the adjacent dielectric isolation layer in the process of milling the passive diffusion 405. By providing a sufficient space between the passive diffusion unit 405 and the diffusion units near the active diffusion units 411 and 413, the lateral size of the opening above the passive diffusion unit 405 is sufficiently increased, and the passive diffusion unit 405 Can reduce leakage current from the passive diffusion 405 to the rest of the semiconductor substrate of the integrated circuit die 401 through gallium embedded with a focused ion beam tool while exposing the substrate.

FIG. 5 is a top view of a flip chip packaged integrated circuit die 501 showing passive probe structures 503 and 505 in accordance with the teachings of the present invention. In the embodiment shown in FIG. 5, passive probe structures 503 and 505 are integrated circuit die 50.
And passive diffusion portions 507 and 509 disposed in one semiconductor substrate. In one embodiment, passive diffusions 507 and 509 are N + diffusions in a P-well. In another embodiment, passive diffusions 507 and 509 are P + diffusions in the N-well. As shown in FIG. 5, passive diffusion 507 is at least X microns wide and has a minimum cross-sectional area that can reduce attenuation of signals extracted from the probe structures described herein. Further, as shown in FIG. 5, the passive diffusion portions 507 and 509 of the passive probe structures 503 and 505 are spaced apart from each other by at least D microns to minimize the crosstalk interference and the generation of the leakage current. suppress. In one embodiment, D is at least 1.0 micron. As shown in FIG. 5, passive diffusion portions 507 and 509 of passive probe structures 503 and 505 are provided.
Has a lateral spacing from the nearest active diffusions 511 and 513 of at least Y microns.

The passive diffusion unit 507 of the embodiment shown in FIG. 5 is coupled to the signal line 517 through the contact 515 so as to be able to probe a signal flowing through the signal line 517. The passive diffusion unit 509 is coupled to the signal line 519 through the contact 521 so that a signal flowing through the signal line 519 can be probed. Signal lines 517 and 519 can be coupled to an input or output of the integrated circuit, or any other integrated circuit node of interest. Therefore,
The signal lines 517 and 519 can be directly coupled to the input gate of another transistor (not shown) or the output drain or source of another transistor (not shown).

FIG. 5 further shows the input gate 525 of the transistor 527 through the signal line 529.
Are shown coupled to the ESD protection diode 523. As can be seen from FIG. 5, the lateral spacing of the diffusion of the ESD protection diode 523 from the nearby diffusion is:
It is not enough to reduce crosstalk interference. Further, the relatively small cross-sectional area of the diffusion portion of the ESD protection diode 523 causes excessive attenuation of the signal extracted through the ESD protection diode 523. Furthermore, since the lateral spacing between the diffusion of the ESD protection diode 523 and the nearby diffusion is relatively narrow, the diffusion of the ESD protection diode 523 is probed without damaging the diffusion of the transistor 527 nearby. Exposure can be very difficult or impossible. Furthermore, even if a focused ion beam milling tool is used to successfully expose the diffusion of the ESD protection diode 523 without damaging nearby diffusions, the ESD protection diode 523 may be exposed through the implanted ions. The current leaking from the diffusion to the semiconductor substrate may be unacceptably large.

In contrast, passive diffusion 507 of passive probe structures 503 and 505
And 509 are oversized in size and have wider lateral spacing compared to the ESD protection diode 523, which reduces probe signal attenuation and reduces crosstalk interference. In addition, because the lateral spacing between the passive diffusions 507 and 509 and other structures has increased, the passive diffusion 5
07 and 509 can be exposed, leakage current in the semiconductor substrate can be reduced, and damage to nearby structures can be suppressed.

FIG. 6 is a flow chart 601 illustrating steps performed in accordance with the teachings of the present invention, which allows the integrated circuit to be probed through the backside of the integrated circuit die. As shown in processing block 603, the passive diffuser is coupled to the signal line of interest in the integrated circuit die. As shown in processing blocks 605 and 607, the passive diffusions are oversized and laterally spaced within the semiconductor die to reduce crosstalk interference and reduce the backside of the integrated circuit die. Through which the passive diffusion portion can be exposed. If a passive diffuser is used for the probe, the semiconductor is thinned from the back of the integrated circuit die as described in processing block 609. Next, as shown in processing blocks 611 and 613, in accordance with an embodiment of the present invention, the passive diffuser is exposed from the backside of the integrated circuit die and signals are extracted from the passive diffuser.

Thus, what has been described is a method and apparatus for probing signals from an integrated circuit through the backside of a flip-chip mounted integrated circuit die. In the foregoing detailed description, the methods and apparatus of the present invention have been described with reference to specific embodiments. However, it will be apparent that various modifications and changes can be made without departing from the broad spirit and scope of the invention. Therefore, the specification and figures should be regarded as illustrative rather than restrictive.

[Brief description of the drawings]

FIG. 1A illustrates a prior art wire bond technique.

FIG. 1B illustrates a flip chip or C4 packaging technique according to the prior art.

FIG. 2 is a schematic diagram of an integrated circuit with inputs and outputs that can be probed by a circuit designer during debugging.

FIG. 3 is a schematic diagram of an integrated circuit with inputs and outputs that can be probed in accordance with the teachings of the present invention.

FIG. 4A is a cross-sectional view of a probe structure in accordance with the teachings of the present invention with respect to another diffusion region of an integrated circuit die.

FIG. 4B is a cross-sectional view of an integrated circuit die provided with a probe structure in accordance with the teachings of the present invention, which is generally thinned and / or locally grooved from the backside of the integrated circuit die.

FIG. 4C is a cross-sectional view of an integrated circuit die with a probe structure exposed according to the teachings of the present invention.

FIG. 5 is a top view of an integrated circuit die with a probe structure in accordance with the teachings of the present invention with respect to other integrated circuit devices in the integrated circuit die.

FIG. 6 is a flowchart illustrating the steps performed to probe an integrated circuit using the disclosed probe structure in accordance with the teachings of the present invention.

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification code FI Theme coat ゛ (Reference) H01L 21/66 (81) Designated country EP (AT, BE, CH, CY, DE, DK, ES, FI, FR, GB, GR, IE, IT, LU, MC, NL, PT, SE), OA (BF, BJ, CF, CG, CI, CM, GA, GN, GW, ML, MR, NE, SN, TD, TG), AP (GH, GM, KE, LS, MW, SD, SZ, UG, ZW), EA (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM), AL, AM, AT, AZ, BA, BB, BG, BR, BY, CA, CH, CN, CU, CZ, DE, DK, EE, ES, FI, GB, GE, GH, GM, H , HU, ID, IL, IS, JP, KE, KG, KP, KR, KZ, LC, LK, LR, LS, LT, LU, LV, MD, MG, MK, MN, MW, MX, NO, NZ, PL, PT, RO, RU, SD, SE, SG, SI, SK, SL, TJ, TM, TR, TT, UA, UG, US, UZ, VN, YU, ZWF terms (reference) 2G011 AA01 AE22 2G032 AA00 AF07 AF08 4M106 AA02 AD01 AD23 AD26 BA01 BA02 BA03 BA04 BA08 CA01 5F038 CA02 CA10 DT01 DT04 DT12 EZ04

Claims (27)

[Claims] 1. A probe structure in an integrated circuit die, comprising: a signal line disposed in a dielectric isolation layer of the integrated circuit die; and a passive line disposed in the semiconductor substrate of the integrated circuit die to be coupled to the signal line. A diffuser, wherein a passive diffuser is laterally spaced at least about 1.0 micron into the integrated circuit die semiconductor substrate from a closest active diffuser located in the integrated circuit die semiconductor substrate. A probe structure characterized by being opened. 2. The method of claim 1, wherein the passive diffusion is at least about 1.0 micron laterally into the semiconductor substrate of the integrated circuit die from another closest passive diffusion of another probe structure located within the semiconductor substrate. The probe structure according to claim 1, wherein the probe structure is spaced. 3. The probe structure according to claim 1, wherein the cross-sectional area of the passive diffusion is at least about 1.0 square microns. 4. The probe structure according to claim 1, wherein the width of the passive diffusion is at least about 1.0 micron. 5. The probe structure of claim 1, wherein the passive diffusion includes an N + diffusion located in a P-well located in a semiconductor substrate of the integrated circuit die. 6. The N-type wherein a passive diffusion is disposed on a semiconductor substrate of an integrated circuit die.
The probe structure according to claim 1, further comprising a P + diffusion portion disposed in the well. 7. The integrated circuit die of claim 1, wherein the integrated circuit die is included in a flip-chip mounted integrated circuit and the probe structure is accessed through a back surface of the integrated circuit die.
The probe structure according to 1. 8. The transistor of claim 1, wherein the passive diffusion is coupled directly to the output of the transistor located in the integrated circuit die through a signal line to probe the output signal of the transistor. The probe structure according to 1. 9. The probe structure according to claim 8, wherein the passive diffusion unit is directly connected to a drain of the transistor through a signal line. 10. The probe structure according to claim 8, wherein the passive diffusion unit is directly coupled to a source of the transistor through a signal line. 11. The probe structure according to claim 1, wherein the passive diffuser is coupled directly through a signal line to an input of a transistor located in the integrated circuit die. 12. The probe structure according to claim 11, wherein the passive diffusion unit is directly connected to a gate of the transistor through a signal line. 13. The probe structure according to claim 11, wherein the probe structure is included in a cell library used when designing an integrated circuit. 14. A method for probing an integrated circuit die, the method comprising: disposing a passive diffusion in a semiconductor substrate of the integrated circuit die; and coupling the passive diffusion to a signal line in the integrated circuit die. Probing a passive diffusion through the backside of the integrated circuit die. 15. The method of claim 14, including the additional step of generally thinning the integrated circuit die from the backside of the integrated circuit die, wherein the step of thinning is performed prior to the step of probing. . 16. The method of claim 1, further comprising the step of thinning the integrated circuit die locally from the backside of the integrated circuit die proximate to the passive diffusion, wherein the thinning step is performed before the probing step. Item 15. The method according to Item 14. 17. The method of claim 14, including the additional step of exposing the passive diffusion from the backside of the integrated circuit die, wherein the exposing step is performed before the step of probing. 18. The method according to claim 17, wherein the step of arranging comprises: starting from a closest active diffusion located within the semiconductor substrate of the integrated circuit die so as to reduce crosstalk of signals measured in the step of probing. The method of claim 14, wherein the passive diffusions are laterally spaced by at least about 1.0 micron. 19. The method of claim 14, wherein the cross-sectional area of the passive diffuser in the step of placing is at least about 1 micron with respect to the attenuation of the signal picked up in the step of probing. 20. The method of claim 14, wherein the step of probing is performed by a particle beam probe tool. 21. The method of claim 14, wherein the step of probing is performed by an electron beam probe tool. 22. The method of claim 14, wherein the step of probing is performed by an ion beam probe tool. 23. The method according to claim 14, wherein the step of probing is performed by a photon beam probe tool. 24. The method of claim 14, wherein the step of probing is performed through a back surface of the silicon semiconductor substrate by an infrared beam probe tool.
The method described in. 25. The method of claim 14, wherein the step of probing is performed by a mechanical probe tool. 26. The method of claim 16, wherein the step of locally thinning is performed by a focused ion beam milling tool. 27. The method of claim 17, wherein the exposing step is performed by a focused ion beam milling tool.