JP2001358412A - Circuit board and plasma display using the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a plasma display device wherein voltage margin in a display part is ensured, difference of wiring inductance in each path is reduced and luminance unevenness is eliminated. SOLUTION: A wiring wherein inductance value per unit length is large is made to have a folded structure. Folded parts are made to adjoin each other in such a manner that interval between the tip and the end of the folded part of the wiring is at most 10 mm. To a wiring whose inductance value is large, an eddy current pattern is formed in other layer.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a structure of a drive circuit board used for various power electronic devices, and more particularly, to a circuit board having a plurality of wirings having different inductance values, the variation in inductance and the total wiring. A circuit board with a structure that reduces inductance,
Further, the present invention relates to a plasma display using the same.

[0002]

2. Description of the Related Art Conventional PDP (Plasma Display Pane)
The wiring pattern of the representative example 1) will be described with reference to FIG.

FIG. 2 is a perspective view of a PDP as viewed from a driving section. PDPs can be broadly divided into display units and drive units. The driving section mainly includes a sustain X substrate 10 and a sustain Y substrate 11, and the display section includes panels 109 and 110.

The X-side output modules 12 and 13 and the electrolytic capacitors 16 and
17 is mounted on the sustain Y substrate 11.
Electrolytic capacitors 18 and 19 forming a power supply unit with the side output modules 14 and 15 are mounted.

[0005] An X-side BUS board 103 is connected to the sustain X-board 10, and an X-side FPC (Flexible Printed) is provided.
It is connected to a panel 109 via a circuit board (104). Similarly, the sustain Y substrate 11 is the Y-side relay substrate 1.
05 and the panel 109 via the Y-side FPC 106.

The panels 109 and 110 are both made of glass, and the panel 109 is called a front glass substrate and the panel 110 is called a rear glass substrate. An interval d = two glass substrates
After adhering at about 100 μm and exhausting the inside, a mixed rare gas such as Ne and Xe or Ne and He is sealed in a space called a cell. Noble gas pressure p =
It is about 67 kPa.

The voltages applied to the X-side output modules 12 and 13 and the Y-side output modules 14 and 15 are
By making the voltage larger than the voltage value (Paschen's law) determined by the pd product (= 6.7 Pa · m), the panel 1
The rare gas sealed between 09 and 110 discharges.

The ultraviolet rays generated by the discharge are applied to three types of phosphors R (red), G (green), and B
By irradiating (blue), the PDP emits light and displays. One pixel is formed by a set of three RGB cells, and color display is performed.

The path for maintaining light emission is defined by the X-side output module 12 on the sustain X substrate 10 and the sustain Y substrate 1.
1 will be described as an example.

Each of the X-side output module 12 and the Y-side output module 14 is a 2 in 1 package in which two semiconductor elements are incorporated in a totem-pole type. Go through the H side, and then go to the X side BUS board 103,
It flows to the panels 109 and 110 through the PC 104.
Panels 109 and 110 are composed of about 400 to 1500 line electrodes (not shown), and the current passing through panels 109 and 110 is applied to Y-side FPC 106 and Y-side relay board 1.
05, flows on the L side of the Y side output module 14, and reaches the Y side ground.

The ground on the Y side and the ground on the X side are electrically connected by ground plates 107 and 108, and the current reaching the ground on the Y side passes through the ground plates 107 and 108 and finally ends. It reaches the ground of the electrolytic capacitor 16 and forms a loop. A similar loop is formed for the X-side output module 13 and the Y-side output module 15.

Looking at the current flow path in detail, first, the electrolytic capacitor 16 to the X-side output module 12 passes through a path 20 which is a pattern on the sustain X substrate 10, and then the X-side output module 12 It passes through a path 21 which is an intra-module pattern.

Thereafter, the path is divided into two paths at paths 113 and 114, which are patterns on the sustain X substrate 10, and passes through paths 115 and 116 of the X-side BUS substrate 103 and the X-side FPC 104, respectively. Furthermore, panels 109 and 110
The path 117 passes through the paths 118 and 119 of the Y-side FPC 106 and the Y-side relay board 105 and then enters the Y-side output module 14 from the paths 120 and 121 which are patterns on the sustain Y board 11.

Then, the ground plate 10 passes through a path 22 which is a pattern in the module of the Y-side output module 14, and
7, and reaches the electrolytic capacitor 16 via the path 23.

The switching element 24 is mainly supplied with current from the electrolytic capacitor 17, and its output is connected to the wiring pattern 1.
00 is connected. The current supplied from the switching element 24 to the wiring pattern 100
4 has a function of mainly compensating the current for the path 114.

Similarly, the switching element 25 receives a current mainly from the electrolytic capacitor 19 and
The switching element 26 receives a current from the electrolytic capacitor 16, and the switching element 27 receives a current from the electrolytic capacitor 18.
It has the function of compensating the current mainly for the long path among the two paths.

[0017]

The above conventional structure has the following problems in configuration.

In the X-side output module 12, the wiring within the module connected from the power supply pin (not shown) to the output pin (not shown) has a small pattern width and a large wiring inductance value of about 60 nH. Similarly, in the Y-side output module 14, the wiring inductance value of the wiring in the module connected from the output pin (not shown) to the ground pin (not shown) is about 60 nH.

Assuming that the wiring inductance value is L and the time change rate of the current flowing through the wiring is Δi / Δt, L × (Δ
i / Δt). This voltage drop causes a problem that a voltage margin applied to panels 109 and 110 is reduced.

The path 11 on the sustain X substrate 10
Since the wiring lengths of the wirings 3 and 114 are greatly different from each other, a difference in wiring inductance value is generated by about 200 nH. Similarly, a difference between the wiring inductance values of the routes 120 and 121 on the sustain Y substrate 11 is about 200 nH. This inductance difference causes a voltage difference for each path.

Since the luminance of the PDP depends on the voltage applied to the rare gas in the panels 109 and 110, if the voltage applied to each line electrode is different, a luminance step occurs, which greatly impairs the performance of the PDP. Problems arise. Conventionally, switching elements 24, 25, 26, and 27 have been added to compensate for current in a path having a large inductance value, thereby coping with the problem of a luminance step.

In view of the above, it is an object of the present invention to secure a voltage margin of a PDP and to eliminate a luminance step of the PDP.

[0023]

Means for Solving the Problems The present inventors have newly proposed a structure capable of securing a voltage margin of a PDP and eliminating a luminance step. According to this structure, as shown in FIG. 1, the electrolytic capacitor 16 is moved to the output side of the X-side output module 12 on the sustain X substrate 10, and a wiring pattern in the module having a large inductance value per unit length is folded in the middle. In addition, as shown in FIG. 6, the eddy current pattern 60 is provided on a layer different from the wiring layer with respect to the path 113 having a larger wiring inductance value among the paths 112 and 113.

[0024]

Embodiments of the present invention will be described below in detail with reference to the drawings.

[Embodiment 1] FIG. 1 shows a PDP in which patterns in a module are adjacent to each other and an eddy current pattern is provided in an inner layer.
It is a schematic diagram of a drive substrate. The feature is that, by moving the electrolytic capacitors 16 and 17 to the output side of the X-side output modules 12 and 13, the wiring in the module is folded.

The sustain X substrate 10 is a printed circuit board having a four-layer structure, and the layers are electrically connected by through holes. As shown in FIG. 6, the inner layer is provided with an eddy current pattern 60 for a long path 114 in a layer different from the wiring layer.

FIG. 6 is a schematic diagram using an eddy current layer in paths having different inductance values. The eddy current pattern 60 may be electrically independent of other wirings, or may be connected to other wirings at only one location.

FIG. 3 is a schematic diagram showing the size and position of the ground plate of FIG. The ground plates 107 and 108 are shown in FIG.
As shown in the figure, electrolytic capacitors 16, 17, 18, 19
To the negative (-) terminal.

FIG. 4 is a schematic diagram showing a component arrangement and a current path in the sustain X substrate of FIG. Looking at the configuration of the sustain X substrate 10 in detail, as shown in FIG.
Semiconductor devices 40 and 41 are provided in the X-side output module 12.
However, in the X-side output module 13, the semiconductor elements 42, 4
3 exist in a totem pole type.

The semiconductor elements 40 and 42 form the H side of the X-side output modules 12 and 13, respectively.
Reference numerals 1 and 43 denote L of the X-side output modules 12 and 13, respectively.
Side, MOSFET (Metal Oxide S
emiconductor / Field Effect Transistor) and IGB
T (Insulated Gate Bipolar Transistor) or the like is used.

A current path on the sustain X substrate 10 will be described with reference to FIGS. The current output from the positive (+) terminal of the electrolytic capacitor 16 reaches a power supply pin (not shown) of the X-side output module 12 through a path 111 which is a pattern on the sustain X substrate 10.

The current path in the X-side output module 12, which is the path 112 in FIG. 1, is composed of a path 44 and a path 45, which are patterns in the module, as shown in FIG.

The current flowing out of the X-side output module 12 is supplied to the paths 113 and 1 which are patterns on the sustain X substrate 10.
The path is divided into two paths at 14 and reaches the output connectors 30 and 31. Then, the X side BUS board 103 and the X side FPC
Panels 109 and 110 from paths 115 and 116 of 104
Of the Y-side FPC 106 and the paths 118 and 119 of the Y-side relay board 105.

The current further passes through the paths 120 and 121, which are patterns on the sustain Y substrate 11, to become one path in the Y-side output module 14, and similarly to the X-side output module 12, a path that is a pattern in the module. 122
Pass through. Finally, the current loop is completed by reaching the negative terminal of the electrolytic capacitor 16 from the path 123 flowing through the ground plates 107 and 108.

At this time, in the X-side output module 12, the path 44 and the path 45 are folded close to the semiconductor element 40. Similarly, in the X-side output module 13, the Y-side output module 14, and the Y-side output module 15,
The wiring in the module is folded close to the semiconductor element.

By providing the folded portion in this way, X
The reason why the wiring inductance value in the side output module 12 is reduced will be described below.

FIG. 5 is a schematic diagram showing the principle of reducing the inductance value of the folded structure. The pattern 50 corresponds to a wiring inside the module in the X-side output module 12, and the eddy current layer 51 corresponds to a heat sink (not shown) of the X-side output module 12.

The pattern 50 has a small wiring width and the largest inductance value per unit length in the sustain X substrate 10. By making the folded structure as shown in FIG. 5, the current 52 flowing through the pattern 50 is in the opposite direction, and a force acts in a direction that hinders a change in the magnetic field of each other, so that the inductance value of the pattern 50 is reduced. The effect of is obtained.

Further, since the eddy current 53 flows in the eddy current layer 51 in a direction that hinders the change of the current 52, the inductance value of the pattern 50 is reduced.

FIG. 21 shows an example of the wiring of the module 12. Power supply pin 2100 to switching element 2102
, And the wiring 2104 from the switching element 2102 to the output pin 2101 are adjacent to each other with a width of about 5 mm and a wiring interval of about 1 mm, thereby reducing the wiring inductance value.

The output pin 2105 is connected to the recovery pin 21.
The wiring 2107 in the module reaching 06 also has a folded structure to reduce the wiring inductance value.

FIG. 8 is a circuit diagram schematically showing the wiring of the PDP having the circuit structure of FIG. 1, and shows a circuit diagram of the inductance value reduction by the folded structure. The wiring pattern can be represented by an inductance component in terms of a circuit. The circuit components excluding the wiring pattern are
0, the electrolytic capacitor 16, and the load 74 representing the panels 109 and 110.

Conventionally, as shown in FIG. 2, the power supply unit and the output unit of the X-side output module 12 are connected to the X-side output module 12.
Are provided on both sides. Let's take a look at FIG. 7 which shows a circuit of a conventional PDP wiring. FIG. 7 is a schematic diagram showing a conventional PDP wiring in a circuit form.

The inductances 71 and 72 indicate the path 20 in the X-side output module 12, and similarly, the inductance 73 is the same as the path 113 and the path 115 or the path 11
4 and the path 116, the inductance 75 is the path 118 and the path 119 or the path 120 and the path 121, and the inductances 76 and 77 are the path 2 in the Y-side output module 14.
2. The inductance 78 represents the path 23 of the ground plates 107 and 108. Currents 79 and 700 flow in the circuit in the direction shown in FIG.

The inductances 71, 72 and 76, 7
7 has a large L value of about 60 nH, and occupies a large proportion as an inductance value in the current loop, despite its short length. This absolute value causes a voltage drop, and the wiring in the module is a main factor in reducing the panel margin.

On the other hand, looking at the wiring of FIG. 8, the inductance 80 represents the path 44, and similarly, the inductance 81 is the path 45, the inductance 8
Reference numerals 2 and 83 denote a path 122 in the Y-side output module 14, and inductance 84 denotes a path 12 of the ground plates 107 and 108.
3 is represented. The circuit has currents 85, 86, 87, 88, 89
Flows in the direction of the figure.

The inductance 80 and the inductance 81
Since the current 85 and the current 86 flowing in the opposite directions are opposite to each other, a mutual inductance 800 is generated between the inductance 80 and the inductance 81. The sign of the mutual inductance 800 is minus, and the effective wiring inductance value of the X-side output module 12 is (inductance 80) +
(Inductance 81) -2 × (mutual inductance 8
00), which is greatly reduced.

FIG. 15 is a graph showing the relationship between the interval between the folded portions and the inductance value. The horizontal axis represents the wiring interval (logarithmic display), and the vertical axis represents the ratio to the original inductance value (logarithmic display). .

The smaller the distance between the wirings (eg, the gap between the paths 44 and 45), the greater the interaction between the currents and the lower the inductance value.
If it is less than mm, the low inductance effect is saturated. Also,
If the wiring interval exceeds 10 mm, the interaction between currents is reduced, and the low inductance effect is also reduced. Therefore, the wiring interval needs to be 10 mm or less, and 5 mm
The following is more desirable. When the wiring interval is 5 mm, the inductance value can be reduced to 1/2 to 1/3 of the original value.

Next, FIG. 16 is a graph showing the relationship between the distance between the wiring layer and the eddy current layer and the inductance value. The effect will be described. The horizontal axis represents the distance between the wiring layer and the eddy current layer (logarithmic representation), and the vertical axis represents the ratio (logarithmic representation) to the original inductance value.

As in FIG. 15, the inductance value decreases as the distance between the wiring layer and the eddy current layer decreases. When the interval is less than 0.1 mm, and where the interval exceeds 10 mm, the inductance value is saturated. The low inductance effect is smaller than in FIG. 15 because the absolute value of the eddy current is about 10% of the current flowing through the wiring layer. Therefore, the interval must be at least 10 mm or less,
If possible, 1 mm or less is desirable. When the interval is 1 mm,
The inductance value can be reduced to 1/2 to 1/3 of the original value.

A description will now be given of the low inductance effect caused by folding the wiring in the module and providing the eddy current layer.

FIG. 9 is a graph showing the change in the inductance value due to the change in the pattern in the module. The horizontal axis represents the old and new wirings, and the vertical axis represents the inductance value. The black circle 90 is the inductance value of the wiring in the conventional module, which corresponds to the total inductance value of the path 21 and the path 22 in FIG. 2, and the value is about 120 nH. The white circle 93 is the inductance value of the new module wiring, and corresponds to the total inductance value of the path 112 and the path 122 in FIG. The wiring interval of the folded part in the module is 1 mm,
By setting the distance between the wiring layer and the eddy current layer to 0.5 mm,
The inductance value can be reduced to about 10 nH or less than 10% of the conventional value.

The black circle 91 is the inductance value of the conventional ground wiring, which corresponds to the inductance value of the path 23 in FIG. 2, and its value is about 200 nH. The white circle 94 is the inductance value of the new ground wiring,
3 corresponds to the inductance value.

As shown in FIG. 3, the electrolytic capacitors 16 and
The earth plates 107, 10 are moved with the movement of the 17, 18, 19
8, the inductance value becomes about 20 n
H rises to about 220 nH.

As the ground wiring, a solid pattern of ground potential (not shown) in the inner layer of the sustain X substrate 10 and the sustain Y substrate 11 may be used instead of using the ground plates 107 and 108. Increases slightly from 20 nH.

The black square 92 is the total inductance value of the conventional current loop, which is about 660 nH. The white square 95 is the total inductance value of the new current loop, which is about 370 nH, which is lower than the conventional one by 290 nH.

Of these, by providing the folded structure and the eddy current layer in the module, the reduction in the inductance value of the wiring in the module is about 110 nH, and the increase in the inductance value of the ground wiring is about 20 nH. The inductance value is reduced. The remaining reduction of 200 nH will be described later.

The provision of the folded structure and the eddy current layer in the module reduces the inductance value because the inductance value per unit length of the wiring in the module is reduced.
This is because it is larger than the inductance value per unit length of the ground wiring. That is, for a circuit having a wiring having a different inductance value per unit length, the total wiring inductance value can be reduced by reducing the inductance value of the wiring having a larger inductance value per unit length.

Since the value of the voltage drop due to the inductance value is reduced by the reduction in inductance, the voltage margin of the panel can be improved accordingly.

Next, the difference in wiring inductance between the paths 113 and 114 in FIG. 1 will be described. The path 114 has a larger wiring inductance value than the path 113 and the path 114. Therefore, the eddy current pattern 60 is provided in another layer for the path 114.

As described above for the wiring in the module, the wiring inductance value of the path 114 is reduced according to FIG. 16 due to the eddy current effect. Since the eddy current pattern 60 is not applied to the path 113, the path 11
The wiring inductance value of No. 3 does not change, and the wiring inductance difference between the path 113 and the path 114 can be reduced.

FIG. 17 is a graph showing the change in the inductance value due to the provision of the eddy current layer, and shows the change in the wiring inductance value due to the application of the eddy current layer.
The horizontal axis represents the conventional wiring without the eddy current layer and the new wiring with the eddy current layer, and the vertical axis represents the wiring inductance difference between the path 113 and the path 114.

A black circle 1700 represents a conventional wiring inductance difference, and since there is no eddy current layer, a wiring inductance difference of 150 nH or more exists. This means that a wiring inductance difference of 300 nH or more occurs at the maximum in the current loop of FIG. 2, and this wiring inductance difference causes a problem of a luminance step.

A white circle 1701 represents a new wiring inductance difference. By setting the distance between the eddy current layer and the wiring layer to about 0.5 mm, the wiring inductance difference is reduced to 50 nH or less. This is up to 100n in the current loop of FIG.
This means that there is a wiring inductance difference of about H, which can be reduced to about 1/3 of the conventional value.

The reduction of the inductance value of 200 nH described in the description of FIG. 9 is achieved by providing the eddy current pattern 60 shown in FIG. 6 to reduce the inductance value of the path 114 and to reduce the inductance value of the paths 113 and 114 having different inductance values. This is because the inductance difference has been reduced. That is, when this is arranged, the breakdown of the inductance value 290 nH reduction shown in FIG. 9 is (X output path reduction: 100
nH) + (reduction of wiring in module: 90 nH) + (Y
Output path reduction: 100 nH).

The wiring is represented by a model in which a resistance and an inductance are connected in series. The resistance value is as small as about 50 mΩ, the wiring impedance is almost determined by the inductance component, and the tendency becomes stronger as the frequency becomes higher.

When the wiring inductance difference is about 100 nH, the wiring impedance difference is about 1Ω. Assuming that the time change rate of the current is about 10 ⁸ A / s, about 100 n
A difference in voltage drop of about 10 V is caused by the difference in wiring inductance of H.

FIG. 19 is a graph showing the relationship between the voltage applied to the panel and the luminance.
Assuming that the luminance value is B, the rare gas of the panel does not discharge when the voltage value is small, but starts discharging when the voltage reaches a certain threshold voltage (Vth) or more, and B = aV + C (a: proportional constant,
(C: constant), the luminance increases, and as the voltage value increases, the luminance is saturated.

Assuming that the voltage drop difference is ΔV and the luminance step is ΔB, it can be expressed as ΔB = aΔV. In the PDP, a = 1.2, so that the voltage drop difference of 10 V is equal to the luminance step difference of 12 cd / m ^2. Is equivalent to

FIG. 20 is a graph showing the relationship between the inductance difference and the luminance step, and shows the relationship between the inductance difference and whether or not a human recognizes the luminance step. In general,
Luminance step 12c corresponding to inductance difference 100nH
The value of about d / m ² is said to be a boundary recognized by human eyes as a luminance step, and the eddy current layer is applied only to a path having a large inductance value, and the inductance difference is reduced by 10%.
By setting it to 0 nH or less, the problem of the luminance step can be solved.

Furthermore, FIG. 2 which had to be added conventionally
Since the components such as the switching elements 24, 25, 26, and 27 can be omitted, the cost can be reduced and the degree of freedom of the board design can be increased.

[Embodiment 2] FIG. 10 is a schematic diagram in which the wiring in the X-side output module 12 is made adjacent without changing the arrangement of the electrolytic capacitor 16, and FIG. FIG. 18 is a graph showing a change in the inductance value when the wiring in the module is adjacent to the power supply unit, and FIG. 18 is a schematic diagram showing a region where the power supply unit is arranged.

Referring to FIG. 10 in detail, the electrolytic capacitor 1
6, the wiring from the electrolytic capacitor 16 to the X-side output module 12 is connected to the sustain X board 1
This is performed in the pattern above 0, and the wiring in the X-side output module 12 is made adjacent.

Similarly, in the X-side output module 13, the position of the electrolytic capacitor 17 is the same as the conventional one, the wiring from the electrolytic capacitor 17 to the X-side output module 13 is performed in a pattern on the sustain X board 10, and the X-side output The wiring in the module 13 is adjacent.

Since the positions of the electrolytic capacitors 16 and 17 do not change, a path 1001 representing the ground plates 107 and 108
Has the same inductance value as the path 23 of the ground wiring in FIG. The wiring inductance value of the wiring in the module as seen in the current loop by folding back as shown by the paths 44 and 45 in the X-side output module 12 is equal to that of the first embodiment.
In the same manner as described above, about 120 nH to about 10 nH or less,
It is reduced to 10 or less.

In order to reduce the total inductance, the sustain X connecting the + terminal of the electrolytic capacitor 16 and the power supply pin (not shown) of the X-side output module 12 is connected.
The wiring width of the path 1000 representing the pattern on the substrate 10 is
It is necessary to make the wiring width of the paths 44 and 45 in the X-side output module 12 larger.

The wiring width of the path 1000 is about 5 to 10 mm, which is at least twice the wiring width of the paths 44 and 45.
L value per unit length of 000 is 1 /
2 or less.

When viewed from the current loop, the amount of L increase by extending the path 1000, which is a pattern on the sustain X substrate 10, is about 80 nH, which is smaller than the amount of L reduction 110 nH by adjoining the paths 44 and 45. Since it can be kept small, the total inductance can be reduced.

FIG. 11 shows a change in the inductance value when the structure shown in FIG. 10 is employed. The horizontal axis represents the old and new wirings, and the vertical axis represents the inductance value.

A black circle 90 indicates a wiring inductance value of the conventional module wiring, which is about 120 nH. The white circle 93 indicates the wiring inductance value of the new module wiring, which is 10 nH or less, which is about 110 nH lower than the conventional value.

A black circle 91 and a white circle 1100 indicate the wiring inductance values of the conventional and new ground wirings, respectively, which are about 200 nH. A black circle 1101 indicates the wiring inductance value of the conventional board pattern, and the value is 1
0 nH or less.

A white circle 1103 indicates the wiring inductance value of the new board pattern, which is about 90 nH, which is about 80 nH greater than the conventional value.

A black triangle 1102 indicates the total wiring inductance value of the conventional module wiring, substrate pattern, and ground wiring, and the value is about 330 nH.

The white triangle 1104 indicates the total wiring inductance value of the new module wiring, the board pattern, and the ground wiring, and the value is about 300 nH, which is 3 times larger than the conventional value.
A low inductance of 0 nH is achieved.

The low inductance effect is smaller than that of the first embodiment because the L value per unit length of the substrate pattern is larger than the L value per unit length of the ground wiring.
Therefore, in order to reduce the inductance with respect to the wiring in the module having the largest L value per unit length and to minimize the increase in inductance value due to the extension of other wiring, the wiring having the smallest L value per unit length is used. Is effective for reducing the total inductance.

Extending the ground wiring rather than the substrate pattern is more effective for lowering the inductance. Therefore, it is necessary to devise the arrangement of the power supply unit.

An area 1801 in FIG. 18 represents an area between the output-side ends of the X-side output modules 12 and 13 and the end of the sustain X substrate 10, and the power supply section is most preferably arranged in this area. desirable. If the power supply unit cannot be physically located in the area 1801, the X-side output modules 12 and 13
May be arranged in the region 1800 between the input side end and the output side end, but the low inductance effect
1 is smaller than when the power supply unit is arranged.

In the case of the PDP, since the driving unit is used together with the panel in an upright state, convection of air occurs from the lower side to the upper side in FIG. Therefore, when arranging the power supply section in the area 1800, it is not realistic to arrange a component such as an electrolytic capacitor which is weak against heat above the X-side output module 12, and between the X-side output modules 12 and 13 or X It is arranged below the side output module 13.

When the power supply section is arranged outside the regions 1800 and 1801, the low inductance effect is considerably reduced as described above. Furthermore, in order to reduce the inductance, the power supply unit is brought as close as possible to the power supply pins of the X-side output modules 12 and 13, and in order to reduce the inductance difference between the paths, the X-side output modules 12 and 13 are reduced.
Are preferably brought closer to each other.

[Embodiment 3] FIG. 12 is a schematic diagram in which wirings in a microcomputer (hereinafter abbreviated as a microcomputer) are arranged adjacent to each other.

The switching element 1201 is mounted in the microcomputer 1200 as a bare chip. The power supply of the switching element 1201 is connected to the pad 1203 by bonding an Al wire 1202. Pad 1
203 is a wiring pattern 1204 in the microcomputer 1200.
Is connected to the power supply pin 1205.

Similarly, the input section of switching element 1201 is wire-bonded to pad 1209 connected to input pin 1211 by wiring pattern 1210, and the output section of switching element 1201 is connected to output pin 1
The wire 120 is wire-bonded to the pad 1206 connected by the wiring pattern 1207.

The current flows from the power supply pin 1205 to the output pin 1208 through the wiring pattern 1204, the switching element 1201, and the wiring pattern 1207.

The microcomputer 1200 has a size of about 10 mm square and a wiring width of about 1 mm. Since the length of the wiring is at most about 10 mm, the wiring inductance value is not as large as about 10 nH. Also, the current value is 10 to 100
It is as small as about mA.

However, the clock frequency of the microcomputer 1200 has been increasing from 100 MHz to 1 GHz.
The time change rate of the power supply current is 100 mA / 1 ns, that is, 1
It may reach 0 ⁸ A / s. Therefore, even when the wiring inductance value is about 10 nH, a voltage drop of about 1 V may occur depending on the inductance value. Microcomputer 1
200 operating voltage 5V, or 1 for 3.3V
When the voltage drop of V occurs, there is a possibility that the microcomputer 1200 malfunctions.

In the present invention, by setting the distance between the wiring pattern 1204 and the wiring pattern 1207 to be adjacent to about 1 mm, the sign of the mutual inductance can be made negative by the reverse current. If there is a metal plate serving as an eddy current layer, the wiring inductance value is reduced to about 1/10. Therefore, the value of the voltage drop due to the inductance value can be suppressed to about 0.1 V, so that malfunction of the microcomputer 1200 can be prevented.

The present invention can be applied not only to the microcomputer shown in FIG. 12, but also to discrete products such as general LSI products and IC products.

[Embodiment 4] FIG. 13 is a typical switching power supply circuit diagram, and FIG. 14 is a schematic diagram of a switching power supply substrate to which an adjacent pattern structure is applied.

Referring to FIG. 13, a primary side of a transformer 1300 includes a capacitor 1302 and a switching element 1301.
Are connected, and the current 1307 flows in the direction shown in the figure.

Diodes 1303, 1304, inductor 1305, and capacitor 1306 are connected to the secondary side of transformer 1300. When switching element 1301 is on, current 1308 flows in the direction of the figure, and switching element 1301 turns off. Current when 1309
Flows in the direction of the figure.

In FIG. 14, input pins 1401 and 1402
A DC voltage obtained by rectifying a commercial power supply is applied between the output pins 1403 and 1300 by changing the ratio (duty) of the ON / OFF time of the switching element 1301.
An arbitrary DC voltage can be extracted from between 404.

Since the directions of the currents flowing through the wiring patterns 1405 and 1406 on the primary side of the transformer 1300 are opposite to each other, the wiring inductance value can be reduced by making the interval adjacent to about 1 mm.

Similarly, wiring patterns 1407 and 1408
Since the reverse current flows through the wiring, it is possible to lower the wiring inductance value by placing
Voltage drop can be reduced. In addition, FIG.
It is a pin arrangement diagram of the module to which the present invention is applied.

[0105]

According to the present invention, the total wiring inductance value can be reduced by lowering the path having a large inductance value per unit length, thereby improving the voltage margin of the display section.

Further, by applying the eddy current layer to the path having a large wiring inductance value, the inductance difference between the paths can be reduced, and the luminance step of the panel can be eliminated.

[Brief description of the drawings]

FIG. 1 is a schematic perspective view of a PDP drive board in which patterns in a module of the present invention are adjacent to each other and an eddy current pattern is provided in an inner layer.

FIG. 2 is a schematic perspective view of a conventional PDP viewed from a driving unit side.

FIG. 3 is a schematic diagram showing the size and position of a ground plate of the PDP of the present invention.

FIG. 4 is a schematic view showing a component arrangement and a path within a sustain X substrate of the PDP of the present invention.

FIG. 5 is a schematic diagram illustrating the principle of reducing the inductance value of the folded structure according to the present invention.

FIG. 6 is a schematic diagram of the present invention using an eddy current layer for paths having different inductance values.

FIG. 7 is a schematic diagram showing a wiring of a conventional PDP in a circuit form.

FIG. 8 is a schematic diagram showing a PDP wiring having a circuit structure in which patterns in the module of the present invention are adjacent to each other;

FIG. 9 is a graph showing a change in inductance due to a change in a pattern in a module according to the present invention.

FIG. 10 is a schematic diagram in which patterns in a module are made adjacent without changing the arrangement of the electrolytic capacitor of the present invention.

FIG. 11 is a graph showing a change in inductance when wiring inside a module is made adjacent without moving the power supply unit of the present invention.

FIG. 12 is a schematic diagram in which wirings in a microcomputer according to the present invention are adjacent to each other.

FIG. 13 is a typical switching power supply circuit diagram.

FIG. 14 is a schematic perspective view of a switching power supply substrate to which the adjacent pattern structure of the present invention is applied.

FIG. 15 is a graph showing the relationship between the interval between the folded portions and the inductance value according to the present invention.

FIG. 16 is a graph showing a change in inductance value due to the provision of the eddy current layer of the present invention.

FIG. 17 is a graph showing a relationship between an inductance value and an interval between a wiring layer and an eddy current layer according to the present invention.

FIG. 18 is a schematic diagram showing an arrangement area of a power supply unit according to the present invention.

FIG. 19 is a graph showing a relationship between a voltage applied to the panel of the present invention and luminance.

FIG. 20 is a graph showing a relationship between an inductance difference and a luminance step according to the present invention.

FIG. 21 is a pin layout diagram of the module of the present invention.

[Explanation of symbols]

10: Sustain X substrate, 11: Sustain Y substrate, 1
2, 13: X-side output module, 14, 15: Y-side output module, 16 to 19: electrolytic capacitor, 100, 1
02, 1204, 1207, 1210, 1405, 14
06, 1407, 1408 ... wiring pattern, 103 ... X
BUS board, 104: X-side FPC, 105: Y-side relay board, 106: Y-side FPC, 107, 108: ground plate,
109, 110 ... panel, 20 to 23, 44, 45, 1
11 to 123, 1000, 1001... Route, 24, 2
5, 1201, 1301, 102 ... switching element, 30, 31 ... output connector, 40-43 ... semiconductor element, 50 ... pattern, 51, 60 ... eddy current pattern, 5
2,79,700,85-89,1307-1309 ...
Current, 53, 61 eddy current, 70 power supply, 74 load
71 to 73, 75 to 84 ... inductance, 800, 8
01: Mutual inductance, 90 to 95, 1100 to 1
104, 1700, 1701 ... inductance value for each wiring, 1200 ... microcomputer, 1202 ... Al wire, 12
03,1206,1209 ... pad, 1205,210
0: power supply pin, 1207, 1403, 1404, 210
1,105 output pins, 1211,1401,140
2 input pin, 1300 transformer, 1302, 130
6 ... Capacitor, 1303, 1304 ... Diode, 1
305: inductor, 1400: switching power supply board, 1800, 1801, area, 2103, 2104
2107: wiring in the module, 2106: collection pin.

Continued on the front page (72) Inventor Noboru Akiyama 7-1-1, Omika-cho, Hitachi City, Ibaraki Prefecture Inside Hitachi Research Laboratory, Hitachi, Ltd. (72) Ryuichi Saito 7-1-1, Omika-cho, Hitachi City, Ibaraki Prefecture Hitachi, Ltd.Hitachi Research Laboratories (72) Inventor Michitaka Osawa 3-2-1 Sakado, Takatsu-ku, Kawasaki, Kanagawa Prefecture Fujitsu Hitachi Plasma Display Limited In-house (72) Inventor Makoto Onozawa Sakado, Takatsu-ku, Kawasaki, Kanagawa Prefecture Fujitsu Hitachi Plasma Display Co., Ltd. In-house (72) Inventor Koichi Inoue 3-2-1 Sakado, Takatsu-ku, Kawasaki-shi, Kanagawa Prefecture Fujitsu Hitachi Plasma Display Co., Ltd. F-term (reference) 5C040 FA10 GK11 GK14 5C058 AA11 AB06 BA06 5E338 AA00 AA20 BB51 BB75 BB80 CC01 CC04 CC06 CD05 CD12 CD40 EE11

Claims (14)

[Claims] 1. A circuit board having a circuit on which a circuit having a circuit component and a conductor connecting the circuit component is mounted, and a power supply unit for supplying current to the substrate, wherein the power supply unit includes a circuit board. Wherein at least two current paths are supplied to the circuit board, and a difference between inductance values of the current paths is 100 nH or less. 2. The circuit board according to claim 1, wherein a difference between impedance values of the two current paths is 1 Ω or less. 3. The circuit board according to claim 1, wherein one power supply unit supplies a current to the current path. 4. There is a first, second, and third assembly having circuit components and a conductor connecting between the circuit components, and
And the second aggregate are connected by a first conductor, the second aggregate and the third aggregate are connected by a second conductor, and the third aggregate and the first aggregate are connected by a first conductor. The assembly forms one circuit by being connected by the third conductor, and the current flows through the first conductor.
Flows from the aggregate of the first through the first conductor to the second aggregate,
Further configured to flow through the second conductor to a third aggregate, and finally to return to the first aggregate through the third conductor;
Assuming that the inductance values of the first, second, and third conductors per unit length are L1, L2, and L3, respectively, in the circuit board in which L2 is the largest value among L1 to L3, A circuit board, wherein the mutual inductance value of the second conductor is configured to be negative. 5. The circuit board according to claim 4, wherein the second conductor has a folded portion in the middle of the circuit. 6. A circuit board comprising a first aggregate, a second aggregate and a third aggregate, wherein a circuit constituted by a fourth aggregate and a fourth and a fifth conductor is formed by a circuit of the second conductor. Instead, the fourth conductor and the fifth conductor have a folded portion with respect to a fourth assembly, and the closest distance between the fourth conductor and the fifth conductor is The circuit board according to claim 4, which is 10 mm or less. 7. The circuit board according to claim 5, wherein a conductor is provided at a distance of 10 mm or less from the folded portion so as to include a region where the folded portion is projected. 8. The distance between the first aggregate and the second aggregate is increased while the positions of the first aggregate and the third aggregate are kept as they are, and the distance between the second aggregate and the second aggregate is increased. The circuit board according to claim 4, wherein a distance from the third assembly is reduced. 9. The circuit board according to claim 6, wherein the second assembly is formed in the same direction as the third assembly with respect to the folded portion. 10. A substrate on which a circuit having a circuit component and a conductor connecting the circuit component is mounted, a driving unit having a power supply unit for supplying current to the substrate, and an electric signal from the driving unit. It has a display unit that is displayed,
The display unit has two or more electrodes for transmitting the electric signal in parallel and has a structure in which two glass plates are bonded to each other, and a minute space formed by the two glass plates is provided. A rare gas is sealed in the cell to form a cell. The rare gas is discharged by applying a voltage to the electrode, and the luminance of the display unit after the start of discharge depends on the number of the electric signals. A plasma display having two or more paths of supply current from a device to a display unit, wherein a difference between inductance values of the paths is 100 nH or less. 11. A substrate on which a circuit having a circuit component and a conductor connecting the circuit component is mounted, a driving unit including a power supply unit for supplying current to the substrate, and an electric signal from the driving unit. It has a display unit that is displayed,
The display unit has two or more electrodes for transmitting the electric signal in parallel and has a structure in which two glass plates are bonded to each other, and a minute space formed by the two glass plates is provided. A rare gas is sealed in the cell to form a cell. The rare gas is discharged by applying a voltage to the electrode, and the luminance of the display unit after the start of discharge depends on the number of the electric signals. A plasma display having two or more paths of a supply current from a semiconductor device to a display unit, wherein the circuit component is mounted on a multilayer substrate having two or more layers, the circuit has two paths, and the path has one current inlet. And two current outlets, and the current outlets are electrically connected to each other by a first metal pattern, and the two metal paths have different inductance values, and the first metal pattern corresponds to a path having a larger inductance value. Separate from the layer containing the pattern A second metal pattern in a region where a path having a large inductance value is projected on the layer in the thickness direction of the substrate; A plasma display, characterized in that: 12. The circuit according to claim 10, wherein the conductor connecting the circuit component and the circuit component and the second metal pattern are electrically independent of the circuit or connected at only one place. The plasma display as described. 13. A difference ΔV between a voltage drop of a voltage applied to an electrode of the cell and a difference ΔB in the luminance, wherein ΔB = a
The plasma display according to claim 10, wherein a difference between the voltage drops is ΔB / a or less when represented by ΔV (a: proportional constant). 14. The plasma display according to claim 13, wherein the proportionality constant a is 1.2 and the difference between the voltage drops is 10 V or less.