JP2001358316A - Method for manufacturing semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To form a dense ferroelectric film having high reliability in the case of manufacturing an FRAM using a ferroelectric substance as an insulating film of an information storage capacitor. SOLUTION: A method for manufacturing a semiconductor device comprises the steps sequentially forming a first electrode; a dielectric film and a second electrode in the case of forming a capacitor using the dielectric film made of a composite oxide film between a pair of electrodes, and laminating an insulating oxide film and a wiring layer on the capacitor and quickly heat treating at a temperature rising speed of 10 deg.C/s or more at a reduce pressure of 0.5×133.322 to 500×133.322 Pa between a first electrode forming step and a dielectric film forming step, between the dielectric film forming step and a second electrode forming step, or after the second electrode forming step.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method of manufacturing a semiconductor device having an array of memory cells using a composite oxide film as an insulating film of an information storage capacitor, and more particularly to a method of using a ferroelectric for a capacitor insulating film. Method and structure of a cell transistor / cell capacitor connection wiring portion, a bit line contact portion, and a memory cell in a ferroelectric memory (FRAM) having an array of ferroelectric memory cells, and a high dielectric constant in a capacitor insulating film The present invention relates to a method for forming a memory cell in a dynamic random access memory (DRAM) having an array of dynamic memory cells using a dielectric material, and relates to a FRAM or DRA.
It is applied to a semiconductor integrated circuit including M.

[0002]

2. Description of the Related Art In recent years, a nonvolatile ferroelectric memory cell (FRAM cell) using a ferroelectric thin film made of a material having a perovskite structure or a layered perovskite structure as an inter-electrode insulating film of an information storage capacitor and an array thereof have been provided. FRAM is attracting attention.

[0003] In the ferroelectric film, the electric polarization once generated when an electric field is applied remains even when the electric field is not applied, and an electric field of a certain strength or more is applied in a direction opposite to the electric field. It has the characteristic that the direction of polarization is reversed when it is performed.

Focusing on the polarization characteristic of the dielectric material in which the direction of polarization is reversed, a technology for realizing an FRAM cell using a ferroelectric material as an insulating film of a capacitor for storing information of a memory cell has been developed.

This FRAM cell has a structure in which a capacitor of a DRAM cell is replaced with a ferroelectric capacitor, and takes charge from a ferroelectric capacitor via a switching MOS transistor at the time of polarization inversion or non-inversion. Method (data destructive reading) is used, and there is a feature that stored data written in a memory cell is not lost even when an operation power supply is turned off.

[0006] FRAM is a type of large-capacity memory.
Compared with the RAM, the nonvolatile memory has a feature that a refresh operation is not required for data retention because of its non-volatility, and that power consumption during standby is unnecessary. In addition, as compared with a flash memory which is another nonvolatile memory, it has a feature that the number of times of data rewriting is large and the data rewriting speed is extremely high. In addition, as compared with an SRAM which requires a battery backup and is used for a memory card or the like, it has features that the power consumption is small and the cell area can be significantly reduced.

[0007] The FRAM having the above characteristics is expected to be very large, for example, replacing existing DRAMs, flash memories, and SRAMs, and applying it to logic embedded devices. In addition, since FRAM can operate at high speed without a battery, a non-contact card (RF-ID: Radio-
Development to Frequency-Identification Data) is beginning. The structure of the memory cell of the FRAM is DRA
A structure using a ferroelectric film instead of a paraelectric film in a storage capacitor for storing a charge capacity as information in the same manner as M, and a structure in which a silicon oxide film is replaced with a ferroelectric film in a gate insulating film of a MOSFET. It is roughly divided into two types. The latter is poor in feasibility because there is no suitable ferroelectric film that can be directly formed on the Si interface, and since only proposals have been made so far, FRAM usually refers to the former structure.

As shown in FIG. 22, the FRAM cell has one transistor and one capacitor (1T) composed of one transistor and one ferroelectric capacitor.
24, and a two-transistor, two-capacitor (abbreviated as 2T / 2C) type composed of two transistors and two ferroelectric capacitors, as shown in FIG.

The 1T / 1C structure has the advantage of being able to achieve high integration equivalent to that of a DRAM, but it is necessary to suppress variations in the ferroelectric characteristics of each memory cell and variations in deterioration, thereby increasing the yield and device reliability. Has the disadvantage that it is difficult to raise

The 2T / 2C structure has a disadvantage that it requires twice the area of the 1T / 1C structure. However, since a large characteristic margin can be obtained, it is easy to improve the yield and the element reliability.

In either structure, an electrode / ferroelectric / electrode stack structure is formed on a base insulating film, and Al or Cu wiring is provided through a contact hole formed in an oxide film on the stack to form a passivation film. Protect with.

By the way, as described above, the FRAM cell is capable of high-speed operation with low power consumption and is expected to achieve high integration. Therefore, the manufacturing process of the memory cell area is reduced and the ferroelectric material is hardly deteriorated. Consideration is needed. In addition, there is a situation where an existing FRAM device is mixed with other devices or a multilayer wiring technology indispensable for high integration has not been established yet.

The reason why it is difficult to form a multilayer wiring of a semiconductor integrated circuit on which an FRAM device is mounted is that the ferroelectric material is very weak to a reducing atmosphere (particularly a hydrogen atmosphere). Most of the existing LSI processes involve a process in which hydrogen is mixed, which is a major problem in the manufacture of FRAM.

An example of the step of mixing hydrogen is a step of filling a via hole in a multilayer wiring structure.
In particular, as a method of filling a via hole having a large aspect ratio, W filling by a CVD method is mainly used, but in the step of filling W, a large amount of hydrogen groups are generated, so that the ferroelectric is seriously damaged.

Hereinafter, the above problem will be described in detail.

Conventionally, as a structure of a ferroelectric memory cell,
There are (1) a post-bit line fabrication structure in which a ferroelectric capacitor is arranged below a bit line, and (2) a bit line pre-fabrication structure in which a bit line is arranged below a ferroelectric capacitor.

In the case of manufacturing a ferroelectric memory cell having a bit line post-fabrication structure, a ferroelectric capacitor is arranged above a pass transistor (a MOS transistor for a switch), and the lower electrode and the pass transistor are connected to each other. After connection with a polysilicon plug, a bit line is formed on the ferroelectric capacitor.

When the ferroelectric capacitor is formed, a lower electrode of the ferroelectric capacitor is usually formed on a polysilicon plug using Pt (platinum), and then a ferroelectric thin film is formed. When crystallization is performed by forming a dielectric thin film, high-temperature oxygen annealing is required.

Here, when PZT (lead zirconate titanate) is used as the ferroelectric material, when the oxidation is insufficient, the deterioration of the capacitor characteristics is caused by the generation of defects caused by the diffusion of Pb in the PZT. Happens. In order to avoid this, the oxygen annealing temperature required for performing sufficient oxidation is usually 600 ° C. to 700 ° C.

When a bismuth layered compound such as SBT (strontium bismuth tantalate) is used as the ferroelectric material, the necessary oxygen annealing temperature is usually as high as 800 ° C.

However, at the time of the above-described high-temperature oxygen annealing, there arises a problem that the lower electrode using Pt reacts with the polysilicon plug to form silicide, or the polysilicon plug is oxidized.

On the other hand, when manufacturing a ferroelectric memory cell having the bit line pre-formed structure, a bit line is formed above the pass transistor, and a ferroelectric capacitor is formed above the bit line.

At this time, when the lower electrode (for example, Pt) of the ferroelectric capacitor and the pass transistor are connected by a polysilicon plug, the same problem as in the above-described post-bit line structure occurs.

On the other hand, there has been proposed an upper electrode connection structure in which an upper electrode of a ferroelectric capacitor and a pass transistor are directly connected by a local electrode wiring composed of a buried wiring. This structure has the feature that the pattern layout of the ferroelectric capacitor has a relatively high degree of freedom. By arranging the ferroelectric capacitor on both the pass transistor region and the element isolation region, a fine structure can be realized. Is possible.

To realize the above-mentioned bit line tip forming / upper electrode connection structure, a capacitor protective film is deposited after forming from the lower electrode (plate electrode) to the upper electrode of the ferroelectric capacitor. Thereafter, in order to form a local electrode wiring for directly connecting the upper electrode and the pass transistor, a contact portion with the upper electrode and a contact portion with the active layer of the pass transistor are opened in the capacitor protective film, and the wiring is formed. After depositing the film, patterning is performed.

In order to realize the above-mentioned bit line tip forming / upper electrode connection structure, as described above, when the lower electrode (for example, Pt) of the ferroelectric capacitor and the pass transistor are connected by a polysilicon plug, the lower electrode is connected. Does not react with the polysilicon plug to form a silicide.

However, it is difficult to form the local electrode wiring for directly connecting the upper electrode and the pass transistor as described above in view of aspect ratio and step coverage accompanying miniaturization.

Further, PZT or BST is used as a ferroelectric material.
When using, a reducing atmosphere in various CVD (Chemical Vapor Deposition) processes performed when forming an electrode wiring after forming a ferroelectric thin film becomes a problem, and the ferroelectric material deteriorates its characteristics due to a reduction reaction. There is a problem that arises.

That is, when forming a local electrode wiring for connecting an upper electrode and a pass transistor, a DRAM is used.
Attempts to embed a W plug by W (tungsten) film formation in a strong reducing atmosphere (hydrogen-based gas) using a metal CVD apparatus as used in
Since the characteristics (electrical characteristics such as residual polarization) of the ferroelectric capacitor are deteriorated, the capacitor cannot be used.

On the other hand, when forming a local electrode wiring for connecting the upper electrode and the pass transistor, M
Even if an aluminum wiring film is formed using O (Metal Organic) CVD, it cannot be said that there is no reducing atmosphere (the hydrogen-based component including the source material cannot be completely removed). This causes deterioration of the characteristics of the capacitor.

When PZT or BST is used as the ferroelectric material, Pt, Ir, Ir oxide (IrO ₂ ), Ru, R
A noble metal such as u oxide (RuO ₂ ), LSCO, SRO, or a conductive oxide is used.

However, it is very difficult to finely process these materials at a submicron level of about 0.5 μm by RIE (reactive ion etching), ion milling, ECR, etc. It is not easy to miniaturize the body capacitor. However, when designing a highly integrated ferroelectric memory, miniaturization of the ferroelectric memory cell is indispensable, and miniaturization of the upper electrode of the ferroelectric capacitor is an important issue for miniaturization of the memory cell. .

On the other hand, although the degree of integration of memories is improving year by year, the electric capacitance of a dielectric capacitor for storing electric charges must be maintained at about 30 fF or more even when the size is reduced. To this end, the effective area of the capacitor must be increased, the thickness of the dielectric film must be reduced, or the dielectric constant of the dielectric material must be increased. Previous DRA
In the M technology, three-dimensional and thinner capacitors have been studied mainly by the former two improvements. However, the conventional S
In the case of iO ₂ -based dielectric films, their three-dimensionality and thinning are reaching their limits, and a technique for depositing a dielectric thin film having a large relative permittivity has become necessary.

By the way, a capacitor having the electrode / ferroelectric / electrode stack structure to be used in the FRAM or the electrode / high dielectric constant dielectric / electrode stack structure to be used in the DRAM is manufactured. In this case, as described above, Pt, Ir, R
Noble metals or conductive oxides such as u, IrO ₂ , RuO ₂ , LSCO and SRO are used.

As described above, the ferroelectric material of the FRAM cell capacitor is PZT (Pb (Zr, Ti) O
₃ ), SBT (SrBi ₂ Ta ₂ O ₉ ), BIT
An oxide having a perovskite structure, such as (Bi ₄ Ti ₃ O ₁₂ ), or an oxide in which a part thereof is substituted with a substitution element is used. BST ((Ba, Sr) TiO ₃ ) or the like is used as a high dielectric constant dielectric of the DRAM cell capacitor.

As a method for forming these ferroelectric or high dielectric constant dielectrics, sputtering, laser ablation, CVD (Chemical Vapor Deposition), MOD (M
etallo-Organic Decomposition or Sol-gel (Sol-
gel) method, etc., and further, mist MOD
LSMCD (Liquid Source Misted Chemical Depositi
on) method is known.

The sputtering method is excellent in mass productivity as a film forming technique, and is advantageous in terms of throughput since two electrodes (metal or conductive oxide) sandwiching a dielectric are formed by the same sputtering technique. It is.

However, since sputtering or laser ablation is a technique for forming a film in an atmosphere gas such as N ₂ , Ar, or Ar / O _2, it is necessary to avoid formation of a gas component by being taken into the film. However, there is a problem that voids caused by residual gas are generated in the composite oxide film (oxide film containing at least two kinds of metal elements), and a high-density oxide film cannot be formed.

Actually, Ar from the film immediately after the deposition
Are detected. This is because gas molecules near the target are guided by the high energy of the plasma and enter the film, and do not have a mechanism such as diffusion. Easy to be driven. Since the film immediately after deposition is an amorphous or low-density crystalline film, this residual gas is dispersed and inconspicuous. However, when the film is subjected to a heat treatment for crystallization, the residual gas is deposited on the crystal grain boundaries and interfaces. It is left behind and becomes a clear gap.

If the heat treatment is performed for a short time, large voids are generated not only at the grain boundaries and interfaces, but also within the grains. CV
Even in film formation by D or LSMCD, a carrier gas for introducing a raw material into a chamber is used.
Carrier gas is taken into the film, and as in the case of sputtering, as a result, voids resulting from the residual gas are generated in the composite oxide film.

The size of such a void is determined when the film is crystallized or densified by an annealing process subsequent to the film formation. Particularly, when the annealing is a rapid heat treatment at a high temperature rising rate, Notable. That is, in the crystallization annealing of the composite oxide film, rapid heat treatment is essential to minimize diffusion and evaporation, but there is a problem that a high-density film cannot be formed due to the above problems.

However, in a ferroelectric film having a low film density, not only an operation margin cannot be secured due to a decrease in the amount of polarization, but also it is not possible to drive on a low voltage side, and a short circuit is liable to occur when thinning. Further, there is also a problem that the characteristic changes greatly in an atmosphere in a later process. For the same reason, if a gap is also formed in the electrode film and the density is reduced, the film resistance increases and the operation speed decreases.

[0043]

As described above, in the conventional ferroelectric memory, it was difficult to prevent the characteristic deterioration of the ferroelectric capacitor and to integrate the process.

The present invention has been made to solve the above-mentioned problems, and it is intended to prevent a characteristic deterioration of a ferroelectric capacitor when manufacturing a ferroelectric memory cell and to enable a process integration. An object of the present invention is to provide a method for manufacturing a device.

Another object of the present invention is to provide a dense and reliable FRAM cell using a ferroelectric material or a DRAM cell using a high dielectric constant dielectric material as an insulating film of an information storage capacitor. Provided is a method for manufacturing a semiconductor device capable of forming a ferroelectric film or a high dielectric constant dielectric film having a high dielectric constant.

[0046]

According to a method of manufacturing a semiconductor device according to the present invention, a capacitor is formed using a dielectric film comprising a composite oxide film containing at least two or more metal elements between a pair of electrodes. When manufacturing a semiconductor device in which an insulating oxide film and a wiring layer are further laminated on the capacitor, the step of forming the capacitor includes the step of forming a first electrode for forming a first electrode and the step of forming the first electrode. A dielectric film forming step of forming the dielectric film on the first electrode, a second electrode forming step of forming a second electrode on the dielectric film, the first electrode forming step, and the dielectric film forming step 0.5 × 133.322 Pa or more and 500 × 13 Pa between the dielectric film forming step and the second electrode forming step, or after the second electrode forming step.
Performing a rapid heat treatment at a rate of temperature rise of 10 ° C./second or more under reduced pressure of 3.322 Pa or less.

[0047]

Embodiments of the present invention will be described below with reference to the drawings.

First, an FRAM according to an example of a semiconductor device to which the present invention is applied will be briefly described.

FIG. 22 shows an equivalent circuit of a one-transistor, one-capacitor type ferroelectric memory cell. FIG.
2, C is a ferroelectric capacitor, Q is a MOS transistor for charge transfer, WL is a word line connected to the gate of the MOS transistor, and BL is the MOS transistor.
A bit line connected to one end of the transistor, PL is a plate line connected to one end (plate) of the capacitor, and VPL is a plate line voltage.

FIG. 23 shows an equivalent circuit of a part of a ferroelectric memory having a ferroelectric memory cell array having, for example, a bit line folded configuration.

In FIG. 23, each MC includes a series connection of a ferroelectric capacitor C for information storage using a ferroelectric material for an inter-electrode insulating film and a MOS transistor (pass transistor) Q for charge transfer. The unit cells MC are arranged in a matrix to form a memory cell array 90.

.. WLi (i = 1, 2, 3,...) Are a plurality of word lines commonly connected to the gates of the transistors Q of the unit cells in the same row in the cell array 90.

PLi (i = 1, 2, 3,...) Are a plurality of plate lines commonly connected to the plates of the capacitors C of the unit cells in the same row in the cell array 90.

... BLi (i = 1, 2, 3, 4,...) Are bit lines commonly connected to one ends of transistors of unit cells in the same column in the cell array 90.

The word line selection circuit 81 selects a part of the plurality of word lines WLi based on an address signal and supplies a word line voltage.

The capacitor plate line selection circuit 82 receives the plurality of plate lines PL based on the address signal.
A part of i is selected to control the voltage of the plate line PLi.

On the other hand, 2 using two memory cells of FIG.
As shown in FIG. 24 or FIG. 25, the transistor / two-capacitor type ferroelectric memory cell includes a first transistor Q1 and a second transistor Q2, and the first transistor Q2 and the first transistor Q2.
Capacitors Q1 connected in series corresponding to the transistors Q1 and Q2, respectively.
And the second capacitor C2.

A first bit line BL1 and a second bit line / BL correspond to one end (drain) of each of the first transistor Q1 and the second transistor Q2.
1 is connected, a word line WL is commonly connected to each gate, and the first capacitor C1 and the second capacitor
Plate line PL common to each plate of the capacitor C2 of FIG.
Is connected.

The word line WL and the plate line PL are provided in parallel. A word line signal is supplied to a word line WL selected by a word line row decoder (not shown), and the plate line row is supplied. Decoder (not shown)
The plate line voltage VPL to the plate line PL selected by
Is supplied.

The two bit lines BL1 and / BL
1 is connected to a sense amplifier (not shown) for bit line potential sense amplification, a write circuit (not shown), and a precharge circuit (not shown).

Next, the principle of the data write operation and the principle of the data read operation of the ferroelectric memory cell having the two-transistor / two-capacitor configuration will be described with reference to FIGS.

FIGS. 24A to 24C show the state of the applied electric field and the electric polarization of the ferroelectric capacitor during the write operation, and FIGS. 25A to 25C show the state of the ferroelectric during the read operation. The state of the applied electric field and electric polarization of the body capacitor is shown.

FIG. 26 shows the potential applied to the plate line during the data write operation and the data read operation. When writing and reading data to and from the ferroelectric memory cell, the direction of the dielectric polarization is controlled by changing the potential of the plate line PL of the selected memory cell from, for example, 0V → 5V → 0V.

(A) In the data write operation,
In the initial state, the plate line PL is connected to the ground potential Vss (0 V).
, And the two bit lines BL1 and / BL1 are precharged to 0V, respectively.

First, as shown in FIG. 24A, one of the two bit lines BL1, / BL1 (for example, the second bit line / BL1) is set to, for example, 5V, and the word line WL is set.
When 5V is applied to the two transistors Q1 and Q2 to turn on, a potential difference occurs between both ends of the second capacitor C2, for example, a downward polarization in the figure occurs. Does not occur.

Next, as shown in FIG. 24B, when the plate line PL is set to 5 V, the first capacitor C1
, A potential difference is generated between both ends of the second capacitor C2 and an upward polarization occurs in the figure, but the polarization of the second capacitor C2 is not inverted. As a result, as shown in the drawing, the two capacitors C1 and C2 are in a state where polarizations in opposite directions are generated, and this state corresponds to a state of writing data “1” or “0”.

Next, as shown in FIG. 24C, the plate line PL is set to 0 V, the word line WL is set to 0 V, and
The transistors Q1 and Q2 are turned off.

(B) In the data read operation,
In the initial state, the plate line PL is set to 0V, and the two bit lines BL1 and / BL1 are precharged to 0V, respectively. Here, it is assumed that, for example, as shown in FIG. 25A, data in a state in which polarizations in opposite directions occur are written in the two capacitors C1 and C2.

First, as shown in FIG. 25B, when the plate line PL is set to 5 V and, for example, 5 V is applied to the word line WL to turn on the two transistors Q1 and Q2, the second Although a potential difference occurs between both ends of the capacitor C2, the direction of the polarization is reversed, but the direction of the polarization of the first capacitor C1 is not reversed. These two capacitors C1,
The read potential from C2 is sense-amplified by a sense amplifier, and the two bit lines BL1 and / BL1 are set to 0 V and 5 V correspondingly by the output of the sense amplifier. "1" and "0" are determined.

Subsequently, as shown in FIG. 25C, when the plate line PL is set to 0 V, the second capacitor C2
, A potential difference is generated between both ends of the first capacitor C1, and the direction of the polarization is reversed, and the direction of the polarization of the first capacitor C1 returns to the initial state without being reversed.

Next, an embodiment in which the present invention is applied to the above-described FRAM will be described in detail. FIGS. 1 to 3 show an example of a planar pattern of a part of a cell array in a cell array manufacturing process order for a large-capacity ferroelectric memory employing a ferroelectric memory cell according to the first embodiment of the present invention. It is shown schematically.

FIGS. 4 to 7 schematically show a part of the cross-sectional structure in the order of the manufacturing process of the cell array. Specifically, the SDG region and the cell capacitor along the line AA in FIG. 2 shows a cross-sectional structure including:

First, the structure of the cell array will be described. In the structure shown in FIG. 7, the connection structure between the pass transistor and the upper electrode 19 of the ferroelectric capacitor and the structure of the upper electrode 19 are different from those of the above-described conventional bit line forming / upper electrode connection structure.

Here, one MO for charge transfer is used.
S transistor (pass transistor) and 1 for information storage
FRAM having a one-transistor, one-capacitor type ferroelectric memory cell in which a unit cell has a configuration in which a plurality of ferroelectric capacitors are connected in series, and the unit cells are arranged in a matrix to form a memory cell array Will be described as an example. For simplicity of description, each word line is represented by WL, each bit line is represented by BL, and each plate line is represented by PL.

In FIG. 7, reference numeral 1 denotes a first conductivity type (for example, p
A semiconductor substrate (e.g., a silicon substrate) having a plurality of element regions (activation regions) SDG in a surface layer thereof, as shown in FIG. (In a direction parallel to the BL formation direction) and are arranged in a matrix when viewed in plan. An oxide film 2 for an isolation region is formed between each of the element regions SDG. ing.

Here, the positions of the element regions SDG in each column are shifted by one length (one pitch) of the element region SDG for each column, and each element region SDG is in a checkered pattern as a whole. (A zigzag arrangement with respect to the regular lattice).

In each of the element regions SDG, a first drain, channel, and source region constituting a first MOS transistor is linearly formed in a region on one end side from the central portion, and the first MOS transistor is formed from the central portion to the other end. A second drain, channel, and source region forming a second MOS transistor is formed in a linear region in a side region, and the central portion has a drain region D common to the first and second MOS transistors.
It has become.

A gate electrode portion G is formed on the channel region of the MOS transistor with a gate oxide film 3 interposed therebetween.
Gate electrodes G of a plurality of MOS transistors on the same row
Are continuously formed as word lines WL, and word line WL groups are formed in parallel with each other.

In this case, each word line WL (gate electrode portion G) is, for example, P-doped polysilicon 4 and WSi
It has a two-layer structure of (tungsten silicide) 5 and is protected by a surface insulating film 6 and a side wall insulating film 7.

Further, the surface insulating film 6 and the side wall insulating film 7
An interlayer insulating film 9 and an interlayer insulating film 10 for planarizing the surface
Are formed, and word lines W are formed on interlayer insulating film 10.
The bit lines BL extend in a direction orthogonal to the formation direction of the L group.
Groups are formed.

In this case, a contact hole is formed in the interlayer insulating film 10 so as to correspond to the impurity diffusion region (drain region) D of the second conductivity type (n type in this example) at each central portion of the element region SDG. A bit line BL composed of a barrier metal film 11 and a conductive film 12 is formed on the interlayer insulating film 10 at a position slightly deviated from the contact hole, and each bit line BL is formed in the contact hole. The drain regions D of the plurality of element regions SDG in the same column are in contact with each other.

In FIG. 4 to FIG. 7, the bit line BL is indicated by a solid line only in the above-mentioned contact hole, and is indicated by a dotted line on the interlayer insulating film 10 located behind the illustrated cross section. I have.

Further, an interlayer insulating film 13 for flattening the surface and an insulating film 16 for cap are formed on the bit lines BL, and a strong stack structure is formed on the insulating film 16 for cap for each unit cell. Dielectric capacitor (lower electrode 1
7, a ferroelectric insulating film 18 and an upper electrode 19) are formed,
Further, an insulating film 20 for protecting the capacitor and a passivation film 23 are formed.

In this case, each lower electrode 17 of the plurality of ferroelectric capacitors in the same row covers the central part of the SDG region including the corresponding MOS transistor or the upper part of the adjacent element isolation oxide film 2. And the word line W
In the direction parallel to the formation direction of the L group (that is, the bit line BL
(In a direction perpendicular to the direction of the vertical axis) and the capacitor plate line PL.

The upper electrode 19 of the ferroelectric capacitor for each unit cell is formed, for example, in a rectangular shape via the ferroelectric insulating film 18 on the corresponding lower electrode 17 region.

Then, the upper electrode 1 of the ferroelectric capacitor
Reference numeral 9 denotes an impurity diffusion region (source region) S of the second conductivity type (n-type in this example) at one end of the corresponding MOS transistor.
Are connected to each other via an electrode wiring 22 for local connection.

In this case, the interlayer insulating film 13 for planarizing the surface, the interlayer insulating film 10 for planarizing the surface, the interlayer insulating film 9 and the like correspond to the source regions S at both ends of the element region SDG. A contact hole is opened, and a conductive plug (capacitor contact plug) 15 is embedded in the contact hole. A contact hole is formed in the cap insulating film 16 so as to correspond to the capacitor contact plug 15. The contact hole is formed inside the contact hole, on the insulating film 20 for the capacitor protection film, and on the upper electrode 19. For example, an aluminum-based wiring is formed as the electrode wiring 22 for local connection.

In this embodiment, the capacitor contact plug 15 and the electrode wiring 22 also have the structure in which the barrier metal films 14 and 21 are provided on the base side, similarly to the bit line BL.

At this time, in this example, the material of the capacitor contact plug 15 and the material of the electrode wiring 22 are different. Specifically, the material of the capacitor contact plug 15 is preferably a high melting point metal, and the material of the electrode wiring 22 is preferably an aluminum-based wiring material, a copper-based wiring material, or a conductive polysilicon-based wiring material.

The lower end surface of the electrode wiring 22 has a larger area than the upper end surface of the capacitor contact plug 15, and the upper end surface of the capacitor contact plug 15 and an interlayer insulating film therearound (in this example, an interlayer insulating film). 1
Contact 3). Thereby, the electrode wiring 22
And the contact resistance between the capacitor contact plug 15 and the capacitor contact plug 15 and a margin for mask alignment when a contact hole is opened corresponding to the capacitor contact plug 15 can be secured. Next, a method of manufacturing the cell array will be described in the order of steps with reference to the planar patterns shown in FIGS. 1 to 3 and the cross-sectional views shown in FIGS.

First, as shown in FIGS. 1 and 4, an array of cell MOS transistors is formed on a silicon substrate 1 by a process similar to that of a normal CMOS type DRAM cell.

Here, 2 is an oxide film which forms an element isolation region selectively formed in the surface layer portion of the substrate, and D and S are conductive types opposite to the substrate selectively formed in the element formation region in the surface layer portion of the substrate. 3 is a gate oxide film for a MOS transistor formed on the substrate surface, G is a gate electrode portion for the MOS transistor formed on the gate oxide film 3 (the word line WL Part).

Next, an interlayer insulating film 10 is formed on the substrate including on the gate electrode portion G, and a contact hole is formed in a portion of the interlayer insulating film 10 corresponding to the drain region D. Further, the inside of the contact hole and the interlayer insulating film 1 are formed.
The barrier metal film 11 and the conductive film 12 are sequentially formed on the substrate 0, and the conductive film 12 and the barrier metal film 11 on the interlayer insulating film 10 are patterned to form the bit lines BL.

Next, after an interlayer insulating film (for example, BPSG film) 13 for planarization is deposited to a thickness of about 800 nm on the substrate including on the bit lines, chemical mechanical polishing (Chemical Mechanical Polishing) is performed.
Polishing (CMP) is performed to planarize by polishing about 200 nm.

Next, as shown in FIG. 5, a portion of the interlayer insulating film 13 and the interlayer insulating film 10 corresponding to, for example, 0.8 × 0.8 μm A contact hole for a capacitor plug having an opening area is selectively formed. in this case,
The total thickness of the interlayer insulating films 13 and 10 is 1500 nm, and the aspect ratio of the opening is 1.9.

Further, after depositing a barrier metal film (eg, TiN film) 14 on the inner surface of the contact hole to a thickness of 20 nm, tungsten is deposited by a metal CVD apparatus to a thickness of about 1700 nm which is equal to or greater than the total insulating film thickness. Embedded completely inside.

Thereafter, the tungsten film and the barrier metal film on the interlayer insulating film 13 for planarization are removed by etch-back, so that the capacitor contact plug 15 is obtained as shown in FIG.

The capacitor contact plug 1
Since the barrier metal film 14 is formed on the inner wall of the contact hole when embedding 5, diffusion from the contact plug 15 to the impurity diffusion layer for the source region S can be prevented.

Further, as shown in FIG. 5, after the surface of the interlayer insulating film 13 is sufficiently planarized by CMP, a cap insulating film 16 is deposited to a thickness of 150 nm.

Next, as shown in FIGS. 2 and 6, a capacitor lower electrode 17 is formed on the cap insulating film 16.
A conductive film for the (capacitor plate line PL) and a ferroelectric film 18 for the capacitor insulating film are sequentially formed. Further, a capacitor upper electrode 19 is formed, and a conductive film for the ferroelectric film 18 and the lower electrode 17 is formed. After patterning to form a ferroelectric capacitor, the capacitor protecting insulating film 20 is formed.
To form

At this time, PZT is used as the ferroelectric film 18.
_{(PbZr x Ti 1-x O} 3), PLZT ((Pb, La)
(Zr, Ti) O ₃ ) and SBT (SrBi ₂ Ta ₂ O ₉₎
) Etc. can be used. Further, Pt or the like (Pt or Ir or IrOx, IrO ₂ , RuO ₂ ,
Or a combination thereof).

Next, a portion of the capacitor protection insulating film 20 and the cap insulating film 16 corresponding to the portion above the capacitor contact plug 15 is opened, and a portion of the capacitor protection insulating film 20 corresponding to the portion above the capacitor upper electrode 19. Open. In this case, an opening larger than the upper end area of the capacitor contact plug 15 (16 in FIG. 2)
a) and an opening (19a in FIG. 2) smaller than the area of the capacitor upper electrode 19 is formed.

Then, as shown in FIGS. 3 and 7, the capacitor contact plug 15 and the capacitor upper electrode 1 are formed.
For example, a conductive film such as a TiN film 21 for a barrier metal film and an Al (aluminum) wiring containing a Si.Cu (silicon.copper) component may be used as an electrode wiring material for connecting to the capacitor insulating film 9. 20 are sequentially deposited by, for example, a high frequency sputtering method, a metal CVD method or an MOCVD method, and are patterned to form an electrode wiring 2.
2 and a passivation film 23 is deposited thereon.

In the formation of the ferroelectric film 18, after the ferroelectric material is deposited, the ferroelectric material is crystallized.
In order to enhance ferroelectric characteristics, high-speed heat treatment is usually performed for about 10 seconds in a high-temperature oxygen atmosphere at about 750 ° C.

Further, in order to recover the deterioration of the ferroelectric characteristics which occurs when patterning the capacitor in the process after the deposition of the ferroelectric material, the ferroelectric material is heated in a high-temperature oxygen atmosphere at 600 ° C.
Anneal for about 0 minutes.

During the treatment in the high-temperature oxygen atmosphere, the cap insulating film 16 becomes a ferroelectric film 18.
Since the contact hole for forming the electrode wiring is not opened until the thermal treatment step of the ferroelectric substance at the time of forming the capacitor is completed, it has a function of preventing the capacitor contact plug material from being oxidized.

However, even if the capacitor contact plug 15 is covered with the cap insulating film 16, slight partial oxidation of the surface of the capacitor contact plug material cannot be avoided by annealing in a high-temperature oxygen atmosphere.

Therefore, preferably, before depositing the electrode wiring material on the capacitor contact plug 15, a step of etching the surface oxide film of the capacitor contact plug 15 is added before the material is deposited. Stable connection with the wiring material becomes possible. The etching at this time can be performed by replacing the electrode of the normal metal sputtering and performing reverse sputtering.

In general, a 450 ° C. sintering process using a mixed gas of hydrogen and nitrogen to reduce the contact resistance between the MOSFET active layer and the contact plug deteriorates the characteristics of the ferroelectric capacitor in the conventional process example. It was not possible to use it for the reason. On the other hand, according to the manufacturing method of the above embodiment, the capacitor contact plug 1 is formed before the formation of the ferroelectric capacitor.
5, the same sintering process as that of a normal MOS type LSI can be employed before the formation of a ferroelectric capacitor. Specifically, 400 to 400 nm using hydrogen or nitrogen or a mixed gas thereof is used. Sintering at about 500 ° C. can be performed. Thereby, MOSF
There is an advantage that various device parameters such as the gate threshold value Vth of ET and the substrate potential can be commonly controlled.

Further, in the manufacturing method of the above embodiment, the same material as the electrode wiring is not used as the material of the capacitor contact plug 15, and it has oxidation resistance, heat resistance, low contact resistance, and a high aspect ratio contact. It is desirable to use a material that can be buried in the hole, and it is desirable to use a high melting point metal such as tungsten, molybdenum, titanium, and palladium.

This is because, when a material that is easily oxidized such as a polysilicon material or an aluminum material is used as the capacitor contact plug 15, the ferroelectric capacitor is formed after the capacitor contact plug 15 is buried. This is because a high-temperature heat treatment in an oxygen atmosphere is also applied to the capacitor contact plug 15, which causes a problem that the capacitor contact plug 15 is oxidized and its parasitic resistance increases.

In this example, TiN was used as an interlayer between the AlSiCu electrode wiring material and the tungsten contact plug material, but a laminated film of Ti / TiN may be used. Also, as the electrode wiring material, AlSiC
Not only the u wiring, but also an aluminum-based or copper-based wiring material or a conductive polysilicon-based wiring material can be used.

In the manufacturing method of the above embodiment,
In order to reduce the contact resistance between the contact plug for the capacitor and the electrode wiring material, a connection structure is adopted in which the electrode wiring has a wiring area larger than the area of the upper end surface of the contact plug for the capacitor on those contact surfaces. .

That is, in this example, the electrode wiring (AlSiCu / TiN) on the capacitor contact plug is in contact with both the upper end surface of the contact plug (W) and the peripheral insulating film (in this example, the interlayer insulating film 13). The structure is adopted.

Note that the path transistor for charge transfer is not limited to a MOS transistor whose gate insulating film is made of an oxide, and the gate insulating film is made of nitride, oxynitride, or the like.
Alternatively, a MIS having a laminated structure of an oxide and a nitride or the like
A transistor can also be formed.

Next, the PZT material or S
As an upper electrode material of a ferroelectric capacitor using a BT material, Pt or another electrode material (Ir, Ir oxide,
A method of forming an upper electrode of a ferroelectric capacitor as fine as 0.1 micron using Ru oxide or the like will be described with reference to FIGS.
This step can be applied to the formation of other than the ferroelectric capacitor electrode.

First, as shown in FIG. 8A, a lower electrode film 17a of a ferroelectric capacitor and a ferroelectric thin film 18a are sequentially deposited on the cap insulating film 16. In this case, 175 nm of Pt is formed as the lower electrode film 17a, and a 300 nm PZT film is formed as the ferroelectric thin film 18a.

Next, as shown in FIG. 8B, a 300 nm TEOS (tetraethoxysilane) oxide film 20a is deposited on the ferroelectric thin film 18a.

Next, as shown in FIG.
An opening corresponding to a desired upper electrode area is selectively formed in the TEOS oxide film 20a by using (photo etching process).

Next, as shown in FIG. 8D, a Pt film 19a for forming an upper electrode is deposited to a thickness equal to or greater than the TEOS oxide film 20a.

Next, as shown in FIG. 8E, the P on the TEOS oxide film 20a is etched back or CMP.
The t film 19a is removed. Then, a strip-shaped resist pattern is formed using a normal photolithography technique, and the TEOS oxide film 20a / ferroelectric thin film 18a / lower electrode film 17a are formed by anisotropic etching using this resist pattern as a mask. Pattern sequentially.

Thus, the desired strip-shaped ferroelectric thin film 1
8 and the lower electrode 17 are obtained. At this time, the TEOS oxide film 20a and the ferroelectric thin film 18 are formed using the same mask pattern.
a and the lower electrode film 17a are sequentially etched so that the TEOS oxide film 20a is self-aligned.
The ferroelectric thin film 18 and the lower electrode film 17 are formed in substantially the same planar shape.

Next, as shown in FIG. 8F, processing damage due to anisotropic etching at the pattern edges of the ferroelectric thin film 18 and the lower electrode 17 is alleviated, and electrical resistance of the ferroelectric thin film 18 is reduced. The TEOS oxide film 20a, the upper electrode 19,
An insulating film 20 for protecting the capacitor is formed so as to cover the surfaces of the ferroelectric thin film 18 and the lower electrode 17. As the capacitor protection insulating film 20, for example, an SiO ₂ film obtained by decomposition of TEOS by a plasma CVD method or an SiO ₂ film by a thermal oxidation method is formed.

After an opening smaller than the area of the upper electrode 19 is provided in a portion corresponding to the upper electrode 19 of the capacitor protection insulating film 20, the electrode wiring 22 as described above is formed.
Then, a passivation film 23 for final protection is formed.

As described above, in the manufacturing method of the above embodiment, when forming a ferroelectric memory cell, a ferroelectric capacitor is formed after a contact plug layer is buried on one end region of a pass transistor. Electrode wiring for connecting the upper electrode and the upper end of the contact plug can be formed by, for example, a sputtering method.

As a result, it is possible to avoid the step of depositing a wiring film in a reducing atmosphere using a metal CVD device or a MOCVD device after the formation of the ferroelectric memory cell.
Deterioration of electrical characteristics such as the amount of remanent polarization of the capacitor can be prevented.

The capacitor upper electrode 19 is formed on the insulating film 2.
Since the structure is buried in the opening of Oa, the area of the capacitor upper electrode 19 can be reduced, the area of the unit cell can be reduced, and the FRAM can be highly integrated.

In the first embodiment, the capacitor contact plug is formed in one step. However, the capacitor contact plug may be formed in two stages. 9 and 10 are sectional views of FIG.

That is, as shown in FIGS. 9 and 10, the first capacitor contact plugs 11a and 12a are formed simultaneously with the formation of the bit lines BL (11 and 12).
Second capacitor contact plugs 14 and 15 are formed on the insulating layer 13 formed thereon so as to be connected to the upper end surfaces of the first capacitor contact plugs 11a and 12a.

By adopting such a structure, the aspect ratio of each contact hole at the time of embedding the contact plug layer can be reduced, so that the embedding into the contact hole can be easily performed.

The semiconductor device thus formed is formed on a MIS transistor having a drain region and a source region formed of an impurity diffusion region formed on a surface layer of a semiconductor substrate, and on a semiconductor substrate including the MIS transistor. A first insulating film, connected to one of the drain region and the source region via a bit line contact plug buried in the first insulating film;
A bit line formed on the first insulating film;
A first capacitor contact plug having a lower end in contact with the other of the drain region and the source region, and a second capacitor formed on a semiconductor substrate including the bit line. An insulating film, a second capacitor contact plug buried in the second insulating film, and a lower end contacting an upper end of the first capacitor contact plug; and a second capacitor contact plug formed on the second insulating film; A lower electrode, a ferroelectric capacitor having an inter-electrode insulating film using a ferroelectric substance and an upper electrode,
An electrode wiring for connecting between an upper end of the second capacitor contact plug and the ferroelectric capacitor is provided.

In the first embodiment, the contact plug portions of the bit lines BL (11, 12) and the capacitor contact plugs 14, 15 (the first capacitor contact plugs 11a, 12a, the second capacitor contact 9 and 10) may be formed so as to have an inversely tapered side surface in which the upper opening width is wider than the bottom opening width, as shown in FIGS.

As a result, even if the interval between word lines becomes narrower as the cell size is reduced, the interval between the word line and the lower part of the contact plug is maintained as desired, and the opening area of the contact hole (the contact area with the electrode wiring) ) Can be easily secured as desired, and the advantage that the process margin increases.

Next, FIGS. 11 and 12 show one example of a sectional structure of a large-capacity FRAM having an array of FRAM cells according to the second embodiment of the present invention in the order of manufacturing steps of the FRAM cell and other elements. The parts are schematically shown.

FIG. 13 shows an FRA according to the second embodiment.
An example of a planar pattern of a part of an array of M cells is schematically shown.

The manufacturing process shown in FIGS. 11 and 12 is performed to fill a via hole for connecting a second layer wiring (bit line or other wiring) in a two-layer wiring structure.
It is characteristic that at least one material (in this example, aluminum) of Al, AlCu, AlCuSi, and Cu is reflowed. Here, the same parts as those in the manufacturing process shown in FIGS. 4 to 7 are denoted by the same reference numerals.

11 and 12, on a semiconductor substrate 1, a switching MOS transistor 3 for a memory cell is provided.
1 and other MOS for embedded devices other than memory cells
A transistor 32 is formed.

In the first insulating layer 10 which covers each of the transistors and whose surface is flattened (that is, its underlying step is flattened), the drain region D and the source region S of the switching transistor 31 are formed in the first insulating layer 10. Connected bit line contact plug 33 and capacitor contact plug 3
4. A contact plug 35 connected to the gate of another MOS transistor 32 for the embedded device is buried.

The second insulating layer 20 covering the substrate including the lower electrode 17, the ferroelectric film 18 and the upper electrode 19 formed in this order on the surface of the first insulating layer 10 has a bit line contact plug. Holes are selectively formed above the capacitor electrode 33, the capacitor contact plug 34, the embedded device contact plug 35, and the upper electrode 19. A bit line embedded plug connection wiring (bit line connection contact pattern) 3 connected to the bit line contact plug 33 through the hole.
6. Capacitor contact plug 34 and upper electrode 1
An upper electrode lead-out wiring (capacitor electrode wiring) 22 connected to the first wiring 9 and a first layer wiring 37 connected to the contact plug 35 for the embedded device are formed.

The upper electrode lead-out wiring 22 and the bit line embedded plug connection wiring 36 are made of Al, Al
It has at least one material of CuSi, AlCu, W metal, TiN metal, and Ti metal, and is formed in the same wiring layer as the first layer wiring 37. Also,
A metal layer 11 ′ made of any of W metal, TiN metal and Ti metal is selectively formed on the upper surface side of the upper electrode lead-out wiring 22, the bit line embedded plug connection wiring 36, and the first layer wiring 37. These can be formed by a sputtering method or a CVD method that does not damage the ferroelectric film 18.

The third insulating layer 30 covering the upper surface of the substrate including the wirings and having a planarized surface is selectively provided above the bit line embedded plug connection wiring 36 and the first layer wiring 37. A via hole is formed in the substrate. Then, Al, AlCu,
At least one material (Al in this example) of AlCuSi and Cu is reflowed, and the bit line BL connected to the bit line buried plug connection wiring 36 via the via hole and the second via the via hole. A second layer wiring 38 connected to the first layer wiring 37 is formed. Further, a passivation film 39 is formed, and a hole is opened in the pad portion.

A memory cell having a capacitor for information storage and a switching transistor using a ferroelectric film made of a substance having a perovskite or a layered perovskite structure as described above, and a ferroelectric having a multilayer wiring structure of at least two layers or more. In manufacturing the body memory, a step of reflowing at least one material of aluminum (Al in this example) of Al, AlCu, AlCuSi, and Cu to fill a via hole in the multilayer wiring structure in a bit line forming step is used.

At this time, in the case of Al reflow, if the underlying wiring is made of Al, depending on the temperature during sputter deposition,
There is a possibility that melting of the system wiring and generation of voids may occur. For this reason, as a base which directly contacts the via metal, any one of a W metal, a TiN metal, and a Ti metal layer is deposited by sputtering or a CVD method, and then the metal is selectively formed directly below a region to be a via portion of a multilayer wiring. A layer 11 'is formed and used as a molten void prevention film.

Next, steps will be described in detail with reference to the sectional views and plan patterns shown in FIGS.

First, as shown in FIG.
A memory cell transistor 31 and a transistor 32 for another device are formed on the silicon substrate 1 by a process similar to the process of forming the S-type DRAM cell.

Here, 2 is an element isolation region selectively formed in the surface layer portion of the substrate, and D and S are impurity diffusion layers of the opposite conductivity type to the substrate selectively formed in the element formation region in the surface layer portion of the substrate. And 3, a gate oxide film for the MOS transistor formed on the substrate surface, and G a gate electrode portion (part of the word line WL) for the MOS transistor formed on the gate oxide film 3. is there.

The element isolation region 2 includes a LOCOS film (selective oxide film), an STI (Shallow Trench Isolation)
Any structure may be adopted.

Next, after a first interlayer insulating film (for example, a BPSG film) 10 for flattening is deposited on the substrate including on the gate electrode portion G, the surface is flattened by CMP.

Next, a contact hole is selectively formed in the first interlayer insulating film 10. Specifically, a bit line contact hole is formed in a portion corresponding to the drain region D, and a contact hole for a capacitor plug and a contact hole for other wiring are formed in a portion corresponding to the source region S.

Further, after a barrier metal film (Ti, TiN) 11 is deposited on the inside of the contact hole and on the first interlayer insulating film 10 by using a sputtering method, a W film is deposited by using a CVD method. Contact plugs 33, 34 and 35 are formed inside the contact holes.

Next, the surface of the first interlayer insulating film 10 is exposed by performing etch back or CMP. Here, similarly to the first embodiment, if the contact plug is formed in a reverse tapered shape, the process margin can be increased.

Next, as shown in FIG. 12, a Pt / Ti / TiN film is formed on the first interlayer insulating film 10 including the contact plugs as a conductive film for the capacitor lower electrode 17 (capacitor plate line PL). Is sputter deposited. Furthermore, PZ is used as the ferroelectric film 18 for the capacitor insulating film.
A T film is formed. Further, Pt is formed as the capacitor upper electrode 19. Then, the upper electrode 19, the ferroelectric film 18, and the lower electrode 1 are formed by RIE.
Patterning is performed in the order of 7 to form a ferroelectric capacitor. At this time, if the ferroelectric film 18 is damaged, it can be recovered by heat treatment in an oxygen atmosphere at 500 to 600 ° C.

Next, a second interlayer insulating film 20 is formed by plasma CVD, and the contact plugs 33, 3 are formed by chemical dry etching (CDE) and RIE.
Then, contact holes for connection with 4, 35 and the upper electrode 19 are formed.

Then, Al and W are sequentially deposited by sputtering to form the capacitor electrode wiring 22 for connecting the capacitor contact plug 34 and the capacitor upper electrode 19, and at the same time, the bit line connection contact pattern 36 Then, the first layer wiring 37 for the embedded device other than the memory cell is formed.

Further, a third interlayer insulating film 30 is formed,
After the surface is flattened by CMP, a via hole for connection with the bit line connection contact pattern 36 and a via hole for connection with the first layer wiring 37 of the embedded device other than the memory cell are formed. , Ar
After depositing a second wiring layer so as to fill the via hole by a high-frequency magnetron sputtering method (Al reflow method of dissolving Al at a high temperature and embedding a via hole by electrophoresis) at a substrate temperature of 400 to 470 ° C. in an atmosphere, The wiring layer is patterned to form the bit line BL and the second layer wiring 38 for the embedded device.

Thus, the bit line BL is connected to the drain region D of the switching MOS transistor 31 of the memory cell via the via hole / bit line connection contact pattern 36 and the bit line contact plug 33. The second layer wiring 38 for the embedded device is connected to the MOS transistor 32 for the embedded device other than the memory cell via the first layer wiring 37.

The second layer wiring 38 may be patterned by using a film deposited by Al reflow as it is. However, the Al-based metal other than the via portion is polished, removed, and planarized by metal CMP. A metal to be the second layer wiring 38 may be deposited again and patterned.

Thereafter, in the case of a semiconductor integrated circuit having a two-layer wiring structure, a top passivation insulating film 39 is deposited,
Open the pad section. In the case of a semiconductor integrated circuit having a wiring structure of three or four layers or more, the interlayer insulating film 3 as described above is used.
After forming 0, a wiring layer is deposited by an Al reflow method and the step of patterning is repeated a required number of times. Thereafter, a top passivation insulating film 39 is deposited, and a pad portion is opened.

In the present embodiment, the first
A part of the first wiring layer when the layer wiring 37 is formed may be used as a pad part.

FIG. 12 shows the third interlayer insulating film 3.
In the case where a hole is selectively opened corresponding to above the bit line contact plug 33 at 0 and the bit line is brought into contact with the bit line connection contact pattern 36, the bit line connection contact pattern 36 is 1
It is also possible to contact the bit line at a different position by appropriately arranging it on the insulating layer 10. Therefore, the process margin can be increased, which is particularly advantageous in improving the degree of freedom in designing a cell array. Similarly, the first layer wiring 37 of the embedded device other than the memory cell can be routed on the first insulating layer 10.

A structure in which a bit line BL is arranged below a ferroelectric capacitor as shown in FIG.
B: Ferro Capacitor On Bit-line) has a higher degree of freedom in designing the memory cell portion, but the insulating film thickness is increased by the amount of the interlayer insulating film 13 formed on the bit line. This imposes a disadvantageous structure on the embedded device other than the memory.

On the other hand, when the bit line BL is arranged on the upper layer side of the ferroelectric capacitor as shown in FIGS. 11 and 12, and the bit line BL is formed by the second wiring layer, The degree of freedom in the design of the memory cell section is greatly increased, thereby making it possible to reduce the cell area.

Here, description will be made with reference to the plane pattern shown in FIG.

The structure shown in FIG. 13 is different from the structures shown in FIGS. 1 to 3 in that the bit line BL is formed with a certain width in a direction perpendicular to the word line WL above the word line WL. The arrangement and width of the bit lines BL, the contact portions, and the like are different, and the other portions are the same. Therefore, the same reference numerals as in FIGS.

That is, in FIG. 13, reference numeral 41 denotes a bit line B
L is a contact portion connected to a bit line connection contact pattern (36 in FIG. 12) in the lower layer portion;
Reference numeral 2 denotes a word line WL for an upper electrode (19 in FIG. 12) and a capacitor contact plug (34 in FIG. 12) of a capacitor having a stack structure formed for each unit cell.
This is a contact portion to which an electrode wiring (22 in FIG. 12) for local connection formed in an intermediate layer between the gate electrode and the bit line BL is connected. PL is a capacitor plate line formed so that the lower electrodes (17 in FIG. 12) of the capacitor are continuous.

That is, if the structure in which the bit lines are arranged on the upper layer side of the ferroelectric capacitor as shown in FIGS. 11 and 12, it is possible to form a cell array as shown in FIG. Since the width of the bit line BL can be made wider and the bit line resistance can be reduced as compared with the FCOB structure, it is extremely advantageous in memory operation.

Therefore, when the FRAM memory and another LSI are mixedly mounted, the bit line BL is disposed in a second layer lower than the FCOB structure below the ferroelectric capacitor or in the first layer.
It is more advantageous to form it after the wiring layer.

Further, for comparison with the present invention, via filling with Ti (sputter) / TiN (sputter) / W (CVD) was carried out instead of via filling with Al reflow in the second embodiment of the present invention. In the case of using (Comparative Example), the effect of the difference in the process on the polarization of the ferroelectric film of the ferroelectric capacitor was examined.

As a result, the polarization amount of the ferroelectric film of the ferroelectric capacitor obtained according to the second embodiment is 30 μm.
Whereas a C / cm ^2, in the comparative example, the amount of polarization was vigorously deteriorated with ~3μC / cm ^2.

In the FRAM device, the amount of polarization of the ferroelectric material is directly effective for the sense margin, and the larger the value, the higher the reliability. Therefore, the superiority of the second embodiment is apparent. .

FIG. 14 shows a large capacity FR having an array of FRAM cells according to the third embodiment of the present invention.
1 schematically illustrates a part of a cross-sectional structure (including an SDG region and a cell capacitor) in an AM.

The structure of the FRAM cell shown in FIG.
2 is basically the same as the structure of the FRAM cell described above with reference to FIG. 2, but a ferroelectric capacitor is formed on the first interlayer insulating film 10 with a first SiO ₂ film 51 interposed therebetween. That the second Si layer is formed on the ferroelectric capacitor.
The difference is that the O ₂ film 52 is formed.

The manufacturing process of the FRAM cell shown in FIG. 14 is different from the manufacturing process described above with reference to FIGS. 11 and 12 in that (1) the first interlayer insulating film 1 is etched back.
After exposing the surface of the ferroelectric capacitor, the first SiO ₂ film 51 is deposited on the entire surface by sputtering. (2) After the ferroelectric capacitor is formed as described above, the second surface is deposited on the entire surface by sputtering. A step of depositing a SiO ₂ film 52 of about 100 nm is added;
When a _second interlayer insulating film 13 is deposited on the iO ₂ film 52 and a hole is selectively formed in the second interlayer insulating film 13, a lower second Si film is formed.
O ₂ film 52 or second SiO ₂ film 52 / first Si
The difference is that holes are also opened in the O ₂ film 51.

The SiO ₂ films 51 and 52 formed by the sputtering method as described above do not contain a hydrogen group,
It is difficult to pass hydrogen groups. That is, in the subsequent steps, even if the hydrogen groups reach the vicinity of the ferroelectric capacitor, they do not directly reach the ferroelectric capacitor, so that the deterioration of the ferroelectric characteristics (polarization amount) is minimized. can do.

FIG. 15 is a sectional view of a semiconductor device according to the fourth embodiment of the present invention. In the present embodiment, the FRAM
Provided is a manufacturing method suitable for a semiconductor device in which a cell array, a logic circuit, and the like are mixed.

The manufacturing method of this embodiment is characterized in that a contact plug from the first layer wiring to the semiconductor substrate or the gate electrode of the transistor in the two-layer wiring structure is formed twice. That is, in the contact plug of this embodiment, first, a lower layer portion is formed before the ferroelectric capacitor of the FRAM cell is formed, and then, after the ferroelectric capacitor is formed, the remaining upper layer portion is formed.

By employing such a method of forming a contact plug, the ratio of the depth to the opening diameter (aspect ratio) of the contact hole can be reduced, and the processing and filling of the contact hole becomes easy. This advantage is advantageous when mixed with a logic product in which patterns are arranged using a very strict rule in processing.

The process in the first half of this embodiment is the same as that in FIG. 11 described in the second embodiment. That is, a MOS transistor 31 for switching a memory cell and another MOS transistor 32 for an embedded device other than the memory cell are formed on the semiconductor substrate 1.

A first bit line contact plug 33 connected to the drain / source region of the switching transistor 31 and a first capacitor are covered in the planarized first interlayer insulating film 10 covering these transistors. A contact plug 34 and a first contact plug 35 connected to a source or drain region or a gate electrode of another transistor 32 for an embedded device are buried.

The surface of the first interlayer insulating film 10 has
As shown in FIG. 15, a thin silicon nitride film layer 121 and a thin silicon oxide film layer 122 are formed, on which a lower electrode 17, a ferroelectric film 18 and an upper electrode 19 are formed in this order. Is formed. This capacitor has a second interlayer insulating film 13 having a planarized surface.
Further, inside the second interlayer insulating film 13, the second bit line contact plug 133, the second capacitor contact plug 134, and the second transistor 32 connected to the other transistor 32 for the embedded device are connected. Contact plug 135 is buried.

The surface of the second interlayer insulating film 13 has
Upper electrode lead-out wiring, bit line embedded plug connection wiring, and first layer wirings 22, 36, 3 for embedded devices
Seven first wiring layers are formed.

The third interlayer insulating film 30, which is formed on the second interlayer insulating film 13 so as to cover the first wiring layer and has a planarized surface, has a bit line embedded plug connection wiring 36.
A via hole is formed immediately above the first layer wiring 37. This via hole is made of Al, AlCu, AlS
It is embedded with at least one of iCu and Cu. Further, the second wiring layers 38 and BL are formed on the surface of the third interlayer insulating film 30, and a passivation film 39 is formed thereon.

Next, the manufacturing method of this embodiment will be described in the order of steps. As described above, the first half of the process is the same as in the second embodiment (FIG. 11). First, the normal CMOS type DR
Similarly to AM, a memory cell transistor 31 and a transistor 32 for another device are formed on a silicon substrate 1. That is, the gate and the diffusion layer region of the transistor are formed, and the first interlayer insulating film 10 and the contact hole are formed.

Subsequently, a contact plug is buried in the contact hole. As described above, in the present embodiment, the contact plug from the first wiring layer to the substrate surface is formed twice, but the contact plug of the first stage (lower layer portion) is formed up to the stage shown in FIG. Complete.

Next, as shown in FIG. 15, a thin silicon nitride film layer 121 is formed on first interlayer insulating film 10 by LPCVD. This silicon nitride film layer 121
Has a role of preventing oxidation of a contact plug material (for example, W) due to annealing in an oxygen atmosphere which is performed later in a ferroelectric capacitor formation step, and a function of preventing a change in transistor characteristics due to annealing. Subsequently, an LPCVD method and a plasma CVD
A thin silicon oxide film layer 122 is formed by a CVD method or a normal pressure CVD method.

Next, as a conductive film for the capacitor lower electrode 17, TiN, Ti, Pt is formed on the silicon oxide film layer 122.
Are sequentially sputtered. A PZT film is formed thereon as a ferroelectric film 18 for a capacitor insulating film. Furthermore, Pt is sputtered thereon as the capacitor upper electrode 19.

Subsequently, the upper electrode 19, the capacitor insulating film 18, and the lower electrode 17 are patterned in this order by RIE to form a ferroelectric capacitor. At this time, if the ferroelectric film 18 is damaged and changes its original characteristics, it can be recovered by annealing in an oxygen atmosphere at about 500 ° C.

Next, a second interlayer insulating film 13 is formed by plasma CVD, and its surface is planarized by CMP or the like. Subsequently, contact holes for connecting the contact plugs 33, 34, 35 to a first wiring layer to be formed later are formed. At this time, the capacitor lower electrode 1
A contact hole (not shown) for connecting the first wiring layer 7 to the first wiring layer is also formed at the same time.

Next, T was used as a barrier layer by sputtering.
After the iN film 111 is formed on the entire surface, Al is deposited by a sputtering method so as to fill the contact hole.
Reflow at a temperature of about 400 ° C. Subsequently, the TiN film and Al other than the inside of the contact hole are removed by the CMP or the etch back method. Up to this point, both the lower layer portion and the upper layer portion of the contact plug are formed, and the characteristic structure of this embodiment is completed.

Next, on the capacitor upper electrode 19, the RI
E forms a contact hole. This contact hole is also formed at the same time as the contact hole described above.
Although it is possible to bury them by l or the like, in this embodiment, they are not formed at the same time but formed separately after the formation of the contact holes. The reason for this is that the aspect ratio of the contact hole to the upper electrode 19 is smaller than that of the other contact holes, so that it is not necessary to embed the contact hole. It is expected that simultaneous embedding is difficult, and it is desirable to minimize damage to the ferroelectric capacitor during embedding.

Next, Ti, TiN, AlCu, and TiN are sequentially deposited on the entire surface by sputtering to form a first wiring layer. By processing this by RIE, the capacitor wiring 22 connecting the capacitor contact plug 134 and the upper electrode 19, the bit line embedded plug connection wiring 36, and the first layer connection wiring 37 for the embedded device are formed. Here, TiN on the uppermost layer of the first wiring layer functions as an anti-reflection film for preventing reflection of light from Al when forming a resist pattern for lithography.

Subsequently, a third interlayer insulating film 30 is formed, and the surface thereof is flattened by CMP. Then, a via hole for connecting the above-mentioned first wiring layer and the below-mentioned second wiring layer is opened. Further, the via hole is buried with Al using the same Al reflow technique as in the case of the contact hole formed in the second interlayer insulating film 13, and then Ti, T
iN and Al are sequentially sputtered to form a second wiring layer.
This second wiring layer is processed by RIE to form a second layer wiring 38, a bit line BL and the like.

Thereafter, in the case of a device having a two-layer wiring structure, a top passivation film 39 is deposited, and a pad portion is selectively opened. In the case of a device having a multi-layer wiring structure, a wiring layer and an insulating layer are formed by repeating the above-described method, a top passivation film 39 is finally deposited, and a pad portion may be selectively opened.

FIG. 16 is a sectional view of a semiconductor device according to the fifth embodiment of the present invention. In the present embodiment, the FRAM
Another structure suitable for a semiconductor device in which a cell array, a logic circuit, and the like are mounted and a method for manufacturing the same are provided. Basically, it is similar to the third embodiment, and the same parts as those in FIG. 14 are denoted by the same reference numerals, and redundant description will be omitted.

The process in the first half of this embodiment is almost the same as that in FIG. 11 described in the second embodiment. That is, a transistor 31 for switching a memory cell, another transistor 32 for an embedded device other than the memory cell, and an element isolation oxide film 2 formed by STI (shallow trench isolation) are formed on the semiconductor substrate 1.

A silicon oxide film layer 10 is deposited so as to cover these transistors, and the surface is flattened by using the CMP method. Thereon, LPCV the _Si x _{N y} film 121
By D method, for example, 150 nm is deposited (FIG. 16). This S
i _x N _y film 121, to reduce damage (threshold shift) to the transistor due to oxygen annealing time of the ferroelectric capacitor formed.

Next, the source region S,
A contact hole to the drain region D is formed by RIE. As the barrier layer 11, Ti and TiN are sequentially deposited by sputtering, and then W is buried as the contact plugs 33, 34, and 35 by the CVD method. Further, Ti, TiN, and W on the insulating film 10 are removed by using, for example, a CMP method.

Next, a silicon oxide film layer (SiO ₂
) 122 is deposited to a thickness of 100 nm. A Pt layer 17, a PZT layer 18, and a Pt layer 19 constituting a ferroelectric capacitor are sequentially deposited thereon by sputtering. These layers are heat-treated in oxygen, and the PZT layer is crystallized to have a perovskite structure. These layers are then processed by RIE into the shape of the capacitor.

Next, a silicon oxide film 13 is deposited on the entire surface by a plasma CVD method, and contact plugs 33, 3 are formed.
Openings are formed on the upper portions 4 and 35 and the upper electrode 19 of the capacitor. Thereafter, Ti and TiN to be barrier layers 111, Al to be wiring layers 22, 36 and 37,
W to be the metal layer 11 'is sequentially deposited by sputtering,
Capacitor and contact plug 3 processed by RIE
Then, a first wiring layer including a wiring with No. 4 and other electrodes for extracting contact plugs is formed.

Next, a silicon oxide film layer 30 is deposited on the entire surface by a plasma CVD method. Contact plugs 33, 35
An opening is formed in the silicon oxide film layer 30 immediately above the
A portion corresponding to 36 of the wiring layer is exposed. Subsequently, Ti and TiN to be the barrier layers 112 and Al to be the wirings 38
Are sequentially deposited by sputtering. Thereafter, Al is reflowed by a heat treatment at about 400 ° C. to bury the opening having a high aspect ratio formed in the silicon oxide film 30. At this time, W is not buried by the CVD method in order to eliminate damage to the ferroelectric capacitor due to hydrogen. A
If 1 reflow is used, no hydrogen is generated, and damage to the ferroelectric capacitor can be avoided.

Subsequently, the Ti, TiN, and Al layers were replaced with R
Process by IE to form a second wiring layer. Thereafter, a silicon oxide film 39 is deposited by the CVD method, and the semiconductor structure shown in FIG. 16 is completed.

FIG. 17 is a sectional view of a semiconductor device according to the sixth embodiment of the present invention. In the present embodiment, the FRAM
Still another structure suitable for a semiconductor device in which a cell array, a logic circuit, and the like are mounted, and a method of manufacturing the same are provided.
Basically, the fourth embodiment is similar to the fourth embodiment, and the same parts as those in FIG. 15 are denoted by the same reference numerals, and redundant description will be omitted.

The steps up to the step of forming the silicon oxide film 122 are performed in the same manner as in the fifth embodiment. Subsequently, the Pt layer 17 and the PZT layer 1 constituting the ferroelectric capacitor are formed on the entire surface.
8. Pt layer 19 is sequentially deposited by sputtering. These layers are heat-treated in oxygen, and the PZT layer is crystallized to have a perovskite structure. These layers are then processed by RIE into the shape of the capacitor.

Next, a silicon oxide film 13 is deposited on the entire surface by a plasma CVD method, and contact plugs 33 and 3 are formed.
An opening is formed in the upper part of 4,35. Thereafter, Ti and TiN to be barrier layers 111 and wiring layers 22, 36, 3
The Al to be 7 is sequentially deposited by sputtering, and the Al is reflowed by a heat treatment at about 400 ° C. to fill the opening. Thereafter, a W metal layer 11 'serving as a barrier is deposited by using the CVD method. These Ti, TiN, Al and W layers are subjected to RIE.
To form a first wiring layer including via contacts with the contact plugs 33, 34, 35 and the like. The feature of this embodiment is that an opening (via hole) formed in the silicon oxide film layer 13 is filled with reflowed Al. Here, similarly to the second embodiment, a TiN metal or a Ti metal is formed of a metal layer 11 ′.
Can also be used.

Next, a silicon oxide film layer 30 is deposited on the entire surface by a plasma CVD method. An opening is formed in the silicon oxide film layer 30 immediately above the drain region D of the transistor, and the corresponding W metal layer 11 'on the first wiring layers 36 and 37 is exposed. Subsequently, similarly to the fifth embodiment, the barrier layer 11
Ti and TiN to be 1 and Al to be the wiring 38 are sequentially deposited by sputtering. Thereafter, Al is reflowed by a heat treatment at about 400 ° C. to fill an opening (via hole) having a high aspect ratio formed in the silicon oxide film 30. The W metal layer 1 formed on the first wiring layer
1 'functions to prevent the Al of the first wiring layer from being dissolved when the Al of the second wiring layer is reflowed.

Subsequently, the Ti, TiN, and Al layers were replaced with R
Process by IE to form a second wiring layer. Thereafter, a silicon oxide film 39 is deposited by the CVD method, and the semiconductor structure shown in FIG. 17 is completed.

FIG. 18 is a sectional view of a semiconductor device according to the seventh embodiment of the present invention. In the present embodiment, the FRAM
Still another structure suitable for a semiconductor device in which a cell array, a logic circuit, and the like are mounted, and a method of manufacturing the same are provided.
The structure of the present embodiment is basically similar to that of the third embodiment, and the same parts as those in FIG. 14 are denoted by the same reference numerals, and redundant description will be omitted.

The process in the first half of this embodiment is almost the same as that in FIG. 11 described in the second embodiment. That is, a transistor 31 for switching a memory cell, another transistor 32 for an embedded device other than the memory cell, and an element isolation oxide film 2 formed by STI are formed on the semiconductor substrate 1.

A silicon oxide film layer 10 is deposited so as to cover these transistors, and the surface is flattened by using the CMP method. Thereon, LPCV the _Si x _{N y} film 121
By D method, for example, 150 nm is deposited (FIG. 18). This S
i _x N _y film 121, to reduce damage (threshold shift) to the transistor due to oxygen annealing time of the ferroelectric capacitor formed.

Next, a silicon oxide film layer (SiO ₂
) 122 is deposited to a thickness of 100 nm. A Pt layer 17, a PZT layer 18, and a Pt layer 19 constituting a ferroelectric capacitor are sequentially deposited thereon by sputtering. These layers are heat-treated in oxygen, and the PZT layer is crystallized to have a perovskite structure. These layers are then processed by RIE into the shape of the capacitor.

Next, a silicon oxide film 13 is deposited on the entire surface by a plasma CVD method, and contact holes to the source region S and the drain region D of the transistor are formed by RIE. Ti and TiN as the barrier layer 11 and Al as the wirings 22, 36 and 37 are sequentially deposited by sputtering, and Al is reflowed by a heat treatment at about 400 ° C. to fill the contact holes. Then CVD
A W metal layer 11 'as a barrier layer is deposited by a method. These Ti, TiN, Al, and W layers are processed by RIE, and the source region S and the drain region D of the transistor are formed.
A first wiring layer including a contact with the first wiring layer is formed. The feature of this embodiment is that the openings (contact holes) formed through the insulating layers 10, 121, 122, and 13 are filled with reflowed Al.

Next, a silicon oxide film layer 30 is deposited on the entire surface by a plasma CVD method, and is planarized by CMP. An opening is formed in the silicon oxide film layer 30 immediately above the drain region D of the transistor, and the W on the corresponding first wiring layers 36 and 37 is formed.
The metal layer 11 'is exposed. Subsequently, similarly to the fifth embodiment, Ti and TiN serving as the barrier layer 112 and Al serving as the wiring 38 are sequentially deposited by sputtering. After this, about 4
Al is reflowed by a heat treatment at 00 ° C. to fill an opening having a high aspect ratio formed in the silicon oxide film 30. The W metal layer 1 formed on the first wiring layer
1 ′ functions to prevent the dissolution of Al in the first wiring layer when reflowing Al in the second wiring layer, and uses TiN or Ti other than W in the same manner as in the sixth embodiment. be able to.

Subsequently, the Ti, TiN, and Al layers were replaced with R
Process by IE to form a second wiring layer. Thereafter, a silicon oxide film 39 is deposited by the CVD method, and the semiconductor structure shown in FIG. 18 is completed.

Next, as an eighth embodiment of the method of manufacturing a semiconductor device according to the present invention, for example, as shown in FIG.
The ferroelectric film and the electrode film of the charge storage capacitor of the AM cell or the high dielectric constant film and the electrode film of the charge storage capacitor of the DRAM cell as shown in FIG. A description will be given of a plurality of embodiments of the process for realizing the embodiment.

That is, a capacitor using a dielectric film made of a composite oxide film containing at least two kinds of metal elements is formed between a pair of electrodes, and an insulating oxide film and a wiring layer are further formed on the capacitor. When manufacturing a laminated semiconductor device, (a) the step of forming the capacitor includes a step of forming a first electrode, a step of forming a dielectric film, and 0.5 Torr
The method includes a step of performing an RTA process (Rapid Thermal Anneal; rapid heat treatment) under a reduced pressure of not less than (0.5 × 133.322 Pa) and not more than 500 Torr, and thereafter, a step of forming a second electrode.

(B) The step of forming the capacitor comprises the following steps:
Forming an electrode, and forming a dielectric film,
The method includes a step of forming a second electrode, and a step of thereafter performing an RTA process under a reduced pressure of 0.5 Torr or more and 500 Torr or less.

(C) The step of forming the capacitor comprises the following steps:
Forming an electrode of 0.5 Torr or more and 500 Torr
The method includes the following steps of performing an RTA process under reduced pressure, a step of forming a dielectric film, and a step of subsequently forming a second electrode.

(D) In any of the above steps (a) to (c), a composite oxide film containing at least two kinds of metal elements is formed on the first electrode by sputtering, CV
D (Chemical Vapor Deposition) method,
Or LSMCD (Liquid Source Misted Chemical
Deposition) method.

(E) In any of the above steps (a) to (c), the RTA treatment under reduced pressure is performed under an oxygen partial pressure of 0.5 Torr to 500 Torr.

(F) In any one of the steps (a) to (c), the RTA treatment under reduced pressure is performed under an ozone partial pressure of 0.5 Torr to 500 Torr.

(G) In any one of the above steps (a) to (c), RT is performed in an atmosphere having an ozone partial pressure ratio of 1% or more.
A processing is performed.

Here, the RTA treatment is performed at a temperature rising rate of 1
Heat treatment at 0 ° C./sec or more. This heat treatment rate significantly increases the crystallinity of the film. In particular, in the case of a lead-based dielectric film such as PZT, the generation of a pyrochlore phase having a low dielectric constant can be avoided, which is an advantageous method for crystallization. However, the heat treatment by RTA has a disadvantage that the crystallization proceeds with insufficient volatilization of the taken-in gas because the rate of temperature rise is high.

In the method of forming a dielectric film according to the eighth embodiment, the RTA process is performed at 0.5 Torr or more and 500 Torr.
Since it is performed under the following reduced pressure, even in a short crystallization process,
Crystallization can be promoted while eliminating the residual gas taken in the deposition film, and a dielectric film having good crystallinity can be formed at a high density. When the dielectric film is crystallized, the crystallization of the electrode film also proceeds at the same time, but the gas taken in the electrode film can also be eliminated by this heat treatment, and the resistance value of the electrode film can be reduced.

In the RTA process, crystallization proceeds.
If the supply of oxygen is insufficient, the dielectric film may become a semiconductor. In particular, a Pb-based dielectric film such as PZT, a barium titanate film, or the like is easily converted into a semiconductor, and the film resistance is significantly reduced.

As the heat treatment in such a case, it is desirable to perform annealing under reduced pressure under an oxygen partial pressure of 0.5 Torr or more and 500 Torr or less. In addition, IrO ₂ or RuO
₂ , a conductive oxide film of ITO, SnO ₂ or the like, if the supply of oxygen is insufficient, the film resistance changes greatly in the subsequent process and the characteristics become unstable. Annealing with an oxygen partial pressure in the range is effective.

Further, annealing under reduced pressure is performed for 0.5 Torr.
When performed under an ozone partial pressure of 500 Torr or less, the leakage current of the film can be reduced. This is particularly important for forming a capacitor in a memory such as a DRAM that requires a refresh operation, and power consumption can be reduced. .

The RTA treatment under these reduced pressures is, in particular,
This is particularly effective when a sputtering method, a CVD method, or an LSMCD method is used in the step of forming a dielectric film made of a composite oxide film containing at least two or more metal elements on the first electrode. This is because when the film is formed by these film forming methods, the influence of the taken-in gas cannot be avoided.

On the other hand, a sol-gel method or a MOD method can be applied to the method of forming a dielectric film according to the eighth embodiment of the present invention.
In the method D, since the organic group has a large amount of volatilization, if the heat treatment is performed under reduced pressure from the beginning, the film surface may be roughened. Therefore, in these cases, 3
It is desirable to perform a heat treatment at a temperature of 50 ° C. or higher and then perform the RTA treatment under reduced pressure as described above.

Next, the method and effect of ozone annealing will be described. An ozone / oxygen mixed gas generated using an ozone generator is introduced into a heat treatment section heated to 100 to 400 ° C. For example, an ozone / oxygen mixed gas is introduced while heating the back surface of the wafer to 300 ° C.
Irradiate with low pressure mercury light of mW / cm ² for 30 to ²⁰⁰ minutes. Mercury light having a wavelength of 320 nm or less is effective.

In this case, if the heat treatment is performed in a mixed gas atmosphere having an ozone partial pressure ratio of 1% or more, the number of oxygen vacancies existing during the film formation is reduced, and the leak current can be reduced. Further, if a heat treatment in oxygen at 600 ° C. or higher is performed thereafter, the variation in the wafer surface can be reduced, which is more effective.

(Example 1) FIG. 19 shows a sectional structure of an FRAM cell having a capacitor formed by a manufacturing method according to an eighth embodiment of the present invention.

In manufacturing the FRAM cell of FIG.
The MOS transistor 70 is formed by forming the element isolation insulating film 2 on the semiconductor substrate 1 by LOCOS, and thereafter forming the diffusion layer for the source S / drain D region, the gate insulating film 3 and the gate electrode part G. . After this, C
An interlayer insulating film 71 made of SiO ₂ is deposited by using the VD method.

Next, the information storage capacitor 72 of the memory cell is formed. First, on the interlayer insulating film 71,
Ti by continuous DC sputtering in Ar of 2.5 mTorr
/ Pt is formed as a lower electrode film.

Next, a thickness of 180 nm or 210 n
A PZT film of m or 240 nm is formed by RF (high frequency) sputtering in Ar of 2.5 mTorr. After that, the first RTA treatment is performed at a heating rate of 100 ° C./sec.
Perform at 800 ° C. for 10 seconds in oxygen of orr.
After forming a Pt film as an upper electrode film on the ZT film by DC sputtering, a second annealing is slowly performed at 600 ° C. using a diffusion furnace.

Next, the laminated lower electrode film, PZT film, and upper electrode film are etched by RIE and patterned into a desired shape to form a lower electrode 17, a dielectric film 18, and an upper electrode 19. Capacitor 7
Form 2 Here, in order to remove etching damage, third annealing was slowly performed at 600 ° C. using a diffusion furnace.

Next, an insulating film 73 is deposited by a CVD method so as to cover the capacitor 72, and one of the source S / drain D diffusion layers of the MOS transistor 70 and the upper electrode 19 and the lower electrode After a contact hole exposing the electrode 17 was formed by etching, a fourth annealing was slowly performed at 600 ° C. using a diffusion furnace.

Next, the source S of the MOS transistor 70 is
An internal wiring 74a for connecting one of the diffusion layers for the drain D and the upper electrode 19 and an internal wiring 74b serving as an extraction electrode from the lower electrode 17 are formed, and a passivation film 75 is deposited on the entire device. Thereafter, a contact hole is formed in the passivation film 75 by RIE, and an aluminum wiring 77 is formed via the barrier layer 76. The gate electrode portion G of the MOS transistor 70 is used as a word line, and the internal wiring 74b, the barrier layer 76, and the aluminum wiring 77 are used as plate lines.

Here, of the four annealings described above,
The first is a heat treatment for crystallizing the dielectric film, and the second is a heat treatment for making the state of the interface between the ferroelectric film 18 and the upper electrode 19 similar to that of the lower electrode 17 and the ferroelectric film 18. Yes, the third and fourth times are for process damage recovery.

The above embodiment is referred to as the first embodiment, and the thickness 18
Examples corresponding to three types of PZT films of 0, 210, and 240 nm are referred to as Examples 1-1, 1-2, and 1-3, respectively.

Examples in which the following steps are changed are described in Examples 2 to 6.
Examples n−1, n−2 and n−3, respectively, from the thinner one with the changed dielectric film thickness. The comparative example was formed in the same manner.

(Example 2) A semiconductor device of Example 2 was formed by forming the information storage capacitor 72 of Example 1 as follows. First, on the interlayer insulating film 71,
Ti by continuous DC sputtering in Ar of 2.5 mTorr
/ Pt is formed as a lower electrode film. Then, PZT
A film is formed by RF sputtering in an Ar / O ₂ atmosphere at a substrate temperature of 500 ° C. After forming a Pt film on the PZT film by DC sputtering, the first RTA annealing is performed at a heating rate of 100 ° C.
C./sec. At 800.degree. C. for 10 seconds in 10 Torr of oxygen.

Example 3 A semiconductor device of Example 3 was formed by forming the information storage capacitor 72 of Example 1 as follows. First, on the interlayer insulating film 71,
Ti by continuous DC sputtering in Ar of 2.5 mTorr
/ Pt is formed as a lower electrode film. The first RTA anneal is performed at a temperature increase rate of 100 ° C./second in oxygen of 10 Torr at 800 ° C. for 10 seconds, and then a PZT film is formed by RF sputtering in Ar at a substrate temperature of 500 ° C. and 2.5 mTorr. Then, after forming a Pt film on the PZT film by DC sputtering, a second annealing is performed slowly at 600 ° C. using a diffusion furnace.

(Example 4) A semiconductor device of Example 4 was formed by forming the information storage capacitor 72 of Example 1 as follows. First, on the interlayer insulating film 71, I
r resinate by spin-coating in an atmosphere of 760 Torr for 8 hours.
Heat treatment is performed at 00 ° C. to form a lower electrode film of IrO ₂ . Next, an SBT film is formed by using the LSMCD method in which an organometallic compound mixed raw material is atomized and deposited on a rotating substrate. Subsequently, after performing a heat treatment at 450 ° C. in the air of 760 Torr in advance, RTA annealing is performed at a temperature increasing rate of 50 ° C. /
This was performed at 800 ° C. for 10 seconds in oxygen of 500 Torr. Thereafter, Ir resinate is spin-coated on the SBT film again, and heat-treated at 800 ° C. in the atmosphere of 760 Torr.
An upper electrode film of IrO ₂ is formed.

(Example 5) A semiconductor device of Example 5 was formed by forming the information storage capacitor 72 of Example 4 as follows. First, Ir resinate is spin-coated on the interlayer insulating film 71 and heat-treated at 800 ° C. in an atmosphere of 760 Torr to form a lower electrode film of IrO ₂ . Next, an SBT film is formed by using the LSMCD method in which an organometallic compound mixed raw material is atomized and deposited on a rotating substrate. Then, 450m in the air of 760 Torr
RTA annealing at a temperature rising rate of 80 ° C.
This was carried out at 800 ° C. for 10 seconds in a mixed atmosphere of 10% ozone and 90% oxygen at 5 ° C./sec and 5 Torr. Then again,
Ir resinate is spin-coated on the SBT film, and 760 Torr
A heat treatment is performed at 800 ° C. in the atmosphere of r to form an IrO ₂ upper electrode film.

Example 6 A semiconductor device of Example 6 was formed by forming the information storage capacitor 72 of Example 1 as follows. First, on the interlayer insulating film 71,
Ti by continuous DC sputtering in Ar of 2.5 mTorr
/ Pt is formed as a lower electrode film. Then, PZT
The film is formed by RF sputtering in Ar of 2.5 mTorr. The first RTA anneal was performed at a heating rate of 100 ° C./sec.
Performed at 800 ° C. for 10 seconds in oxygen of 0 Torr, and then, after forming a Pt film on the PZT film by DC sputtering,
Second annealing, 10% ozone using diffusion furnace
Slowly at 550 ° C. in a mixed atmosphere of 90% oxygen.

(Comparative Example 1) A semiconductor device of Comparative Example 1 was formed by forming the information storage capacitor of Example 1 as follows. First, a 2.5 mT
A lower electrode film made of Ti / Pt is formed by continuous DC sputtering in Ar of orr. Next, the PZT film is
It is formed by RF sputtering in Ar of mTorr. First R
TA annealing is performed at 800 ° C. for 10 seconds in oxygen of 760 Torr at a temperature increase rate of 100 ° C./sec. After that, a Pt film is formed on the PZT film by DC sputtering, and then a second annealing is performed using a diffusion furnace. Slowly at 600 ° C.

Comparative Example 2 A semiconductor device of Comparative Example 2 was formed by forming the information storage capacitor of Example 4 as follows. First, Ir resinate is spin-coated on the interlayer insulating film and heat-treated at 800 ° C. in an atmosphere of 760 Torr to form a lower electrode film of IrO ₂ . Next, a PZT film having a thickness of 180 nm is formed using the LSMCD method in which the organometallic compound mixed raw material is atomized and deposited on a rotating substrate. Subsequently, after a heat treatment at 450 ° C. in an atmosphere of 760 Torr in advance, RTA annealing is performed at a temperature increasing rate of 50 ° C./sec and 800 ° C. in oxygen of 760 Torr at 10 ° C.
Seconds. Thereafter, Ir resinate is spin-coated on the PZT film again, and heat-treated at 800 ° C. in the atmosphere of 760 Torr to form an IrO ₂ upper electrode film.

(Evaluation of Examples and Comparative Examples) FIG.
The capacitances of the capacitors in Examples 1 to 6 and Comparative Examples 1 and 2 are measured, and the relationship between the film thickness (dielectric thickness) t and the reciprocal (1 / C) of the capacitance C is shown in a graph.

The following relationship holds between the capacitance C, the dielectric constant ε of the dielectric, and the dielectric thickness t.

C = εo × ε × S / t where εo is the dielectric constant of vacuum and S is the electrode area. In other words, 1 / C = k × (1 / ε) × t where k = 1 / (εo × S). In an actual graph, a straight line of 1 / C = k × (1 / ε) × t + n is obtained. If n = 1 / C ′, a circuit in which capacitors for C ′ are connected in series is obtained. is expected.

In the working example according to the eighth embodiment of the present invention, the capacitor component corresponding to C ′ is small, so that no extra low dielectric constant layer exists at the interface with the electrode, It can be seen that a dielectric film capable of coping with the formation is formed.

On the other hand, in the comparative example, a capacitor component corresponding to C 'is large, and thus, a sufficient capacitance cannot be obtained, and it is impossible to cope with thinning. In order to drive the device at a low voltage, it is necessary to use the device in a region where the dielectric is sufficiently saturated, that is, to apply a sufficiently large electric field by thinning the film. Then, it cannot respond to thinning.

When the cross sections of the dielectric portions of Examples 1 to 6 and Comparative Examples 1 and 2 were examined with a transmission electron microscope, the thickness of the interface between the dielectric and the electrode in Comparative Example was 1/10 to 1/5. Although many large voids were observed, the voids were small in the examples, and it was found that these voids reduced the density of a part of the film and caused the low dielectric constant layer.

In addition, the operating speed characteristics, fatigue characteristics, etc. of each element were examined. The operation speed was the fastest in Example 3, and no defective bit was generated even when the writing time was reduced to 140 ns. In another embodiment, 150
If it is not longer than ns, a defective bit occurs in the reliability test.
Further, in Examples 4 and 5, the number of times of rewriting could be at least 10 ¹² times, but in other examples, defective bits appeared from 10 ¹⁰ times. 10 ⁷ times fatigue of long after the test allowed produced no defective bit when examining the imprint characteristics were Examples 5 and 6.

(Other Embodiments) In the process of forming the trench type DRAM cell shown in FIG.
A source S / drain D region of a MOS transistor for a transfer gate of a memory cell;
A capacitor having a trench structure of the memory cell is formed. When forming the capacitor 82, the lower electrode 83
Was formed by DC sputtering, and a BST film 84 was obtained as a 100 nm deposited film at a substrate temperature of 450 ° C. by a CVD method using an organometallic compound as a source material and an Ar carrier gas. Thereafter, the N ₂ partial pressure is increased to 450 Torr.
RTA annealing was performed at 600 ° C. in the middle, and Ru of the upper electrode 85 was formed by DC sputtering to obtain a three-dimensional laminated structure. After that, the formation of the SiO ₂ insulating film 86 and the formation of the word lines WL and the bit lines BL are performed, and the DRA is formed.
An M structure was formed. In this case, a dense B having a dielectric constant of 250
An ST dielectric film was obtained.

Next, the FRAM as described above is replaced with RF-I
An example applied to the D system is shown.

The RF-ID system is a non-contact tag system (identifier) using radio waves, and is generally called a non-contact data carrier system or the like. Figure 27 shows the overall system configuration of
Shown in

[0258] The RF-ID system includes a host side including a personal computer, a controller, an antenna, and the like, and a data carrier called a transponder. The transponder has a simple configuration in which a monolithic RF-ID chip in which an FRAM and an ASIC are integrated into one chip and an antenna that performs power reception and data reception / transmission are built.

The host transmits commands and data on a carrier as necessary, and the transponder generates necessary power by the carrier and uses it for writing, reading and transmission of data to the host. Returns information.

The non-contact type tag does not require a battery,
By reading the stored contents of the AM in a non-contact manner using radio waves and rewriting the contents, it is possible to utilize it for management such as entering and leaving a person. For example, a ticket gate with the contactless tag for commuter pass in the pocket of the clothes, or running with the contactless tag attached to the car, so that you do not have to stop to pay each time at the tollgate on the highway. It is intended for applications such as monitoring and managing the entrance and exit of parking lots without human intervention. It can also be used to manage the behavior of livestock and migratory fish.

FIG. 28 shows details of the internal circuit of the transponder.

That is, an LC circuit for detecting an electromagnetic wave input from the outside, a circuit 58 for generating a signal from the electromagnetic wave detected by the LC circuit, a circuit 59 for generating a power supply voltage from the electromagnetic wave detected by the LC circuit, a power supply A power-on circuit 60 for detecting a rise in voltage and outputting a power-on signal
And a plurality of memory cells each comprising a ferroelectric capacitor having a ferroelectric substance between electrodes and a MOS transistor for charge transfer are arranged in a matrix, and for example, the MOS transistors of the memory cells belonging to the same row are replaced with the same word. Lines, and one electrode of the ferroelectric capacitors of the memory cells belonging to the same row are commonly connected to the same capacitor plate line.
It is composed of an FRAM cell array 61 and the like in which one terminal of the S transistor is commonly connected to the same bit line.

Note that the present invention is not limited to the FRAM as described above, but may be an FPGA (Field Programmable Gate Array).
It is also applicable to a method of forming a ferroelectric memory cell which is used in a small amount in a logic program storage portion in a logic LSI having a static RAM or the like.

The present invention is not limited to the case where a ferroelectric memory cell is formed on a semiconductor substrate as described above.
It is also applicable to the case where a ferroelectric memory cell is formed on a semiconductor layer on an insulating substrate, such as I.

Further, as a switching transistor for charge transfer, a MOS in which a gate insulating film is made of an oxide is used.
The transistor is not limited to a transistor, and an MIS transistor in which a gate insulating film includes a nitride, a nitride oxide, a stacked structure of an oxide and a nitride, or the like can be formed.

[0266]

As described above, according to the method of manufacturing a semiconductor device of the present invention, when forming a ferroelectric memory cell, a ferroelectric capacitor is formed after a contact plug layer is buried on one end region of a pass transistor. Is formed, and the upper electrode of the capacitor and the upper end of the contact plug are connected by electrode wiring, so that the effects of processing in a reducing atmosphere after the formation of the ferroelectric capacitor can be avoided, and the ferroelectric capacitor can be easily manufactured. Can be formed.

Further, according to the method of manufacturing a semiconductor device of the present invention, it is possible to realize fine processing of the capacitor upper electrode (Pt or the like), and further, miniaturization of the pattern of the ferroelectric memory cell.

Therefore, according to the semiconductor device manufactured by the semiconductor device manufacturing method of the present invention, the reliability of the electrode wiring for connecting the capacitor upper electrode and the upper end of the contact plug is high, and the ferroelectric capacitor It has a structure that can be miniaturized.

[Brief description of the drawings]

FIG. 1 is a view schematically showing an example of a planar pattern of a part of a cell array in a cell array manufacturing process for a large-capacity FRAM employing a ferroelectric memory cell according to a first embodiment of the present invention.

FIG. 2 is a view showing a part of a plane pattern in a step that follows the step of FIG. 1;

FIG. 3 is a view showing a part of a plane pattern in a step that follows the step of FIG. 2;

FIG. 4 is a view showing a part of a cross section in an example of a manufacturing process of the cell shown in FIGS. 1 to 3;

FIG. 5 is a view showing a part of a cross section in a step that follows the step of FIG. 5;

FIG. 6 is a view showing a part of a cross section in a step that follows the step of FIG. 5;

FIG. 7 is a view showing a part of a cross section in a step that follows the step of FIG. 6;

8 is a cross-sectional view showing a part of the section in detail by extracting a part in the process of FIG. 7;

FIG. 9 is a view showing a part of a cross section in a method of manufacturing a modification of the cell shown in FIGS. 4 to 8;

FIG. 10 is a view showing part of a cross section in a method of manufacturing a modification of the cell shown in FIGS. 4 to 8;

FIG. 11 is a diagram showing a part of a cross section in an example of a cell array manufacturing process for a large-capacity FRAM employing the FRAM cell according to the second embodiment of the present invention.

FIG. 12 is a view showing a part of a cross section in a step that follows the step of FIG. 11;

FIG. 13 is a diagram showing a part of a plane pattern of an FRAM including the FRAM cells shown in FIGS. 11 and 12;

FIG. 14 is a sectional view showing the structure of an FRAM cell according to a third embodiment of the method of manufacturing a semiconductor device of the present invention.

FIG. 15 is a sectional view showing the structure of an FRAM cell according to a fourth embodiment of the method of manufacturing a semiconductor device of the present invention.

FIG. 16 is a sectional view showing the structure of an FRAM cell according to a fifth embodiment of the method of manufacturing a semiconductor device of the present invention.

FIG. 17 is a sectional view showing the structure of an FRAM cell according to a sixth embodiment of the method of manufacturing a semiconductor device of the present invention.

FIG. 18 is a sectional view showing the structure of an FRAM cell according to a seventh embodiment of the method of manufacturing a semiconductor device of the present invention.

FIG. 19 is a sectional view showing the structure of an FRAM cell according to an eighth embodiment of the method of manufacturing a semiconductor device of the present invention.

FIG. 20 is a graph showing capacitor characteristics of an example according to the eighth embodiment and a comparative example.

FIG. 21 is a sectional view showing the structure of a DRAM cell according to an eighth embodiment of the method of manufacturing a semiconductor device of the present invention.

FIG. 22 is a circuit diagram showing an equivalent circuit of a ferroelectric memory cell having one transistor and one capacitor.

23 is a circuit diagram showing an equivalent circuit of a part of the array of the ferroelectric memory cells of FIG. 22 and peripheral circuits thereof.

24 shows states of an applied electric field and electric polarization of a ferroelectric capacitor in order to explain a principle of a write operation of a two-transistor / two-capacitor type ferroelectric memory cell using two memory cells of FIG. 22; FIG.

25 shows states of an applied electric field and electric polarization of a ferroelectric capacitor in order to explain the principle of a read operation of a two-transistor, two-capacitor type ferroelectric memory cell using two memory cells of FIG. 22; FIG.

26 is a waveform chart showing an example of a voltage waveform applied to a plate line PL in the write operation shown in FIG. 24 and the read operation shown in FIG. 25.

FIG. 27 is a diagram showing the overall system configuration of an RF-ID system.

FIG. 28 is a diagram showing details of an internal circuit of the transponder.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Semiconductor substrate, 2 ... Element isolation oxide film, 3 ... Gate oxide film, 4 ... P-doped polysilicon, 5 ... WSi, 6, 7 ... Insulating film for gate electrode protection, 9, 10 ... Insulating film, 11: barrier metal film, 13: insulating film for planarization, 14: barrier metal film, 15: capacitor contact plug, 16: insulating film for cap, 17: lower electrode, 18: ferroelectric thin film, 19: upper part Electrodes, 16a, 19a: opening for connecting electrode wiring, 20a: insulating film for embedding upper electrode, 20: insulating film for protecting capacitor, 21: barrier metal film, 22: electrode wiring, 23: passivation film, SDG ... Active region, D: impurity diffusion layer (drain region), G: gate electrode portion, S: impurity diffusion layer (source region), BL: bit line, WL: word line, PL: plate

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Iwao Kunishima 1 Kosaka Toshiba-cho, Saiwai-ku, Kawasaki City, Kanagawa Prefecture Inside the Toshiba R & D Center (72) Inventor Susumu Suto, Komukai Toshiba, Saiwai-ku, Kawasaki City, Kanagawa Prefecture No. 1 in the town Toshiba R & D Center (72) Inventor Kumi Okwada 1 in Komukai Toshiba-cho, Koyuki-ku, Kawasaki-shi, Kanagawa Prefecture In-house Toshiba R & D Center (72) Inventor Osamu Hidaka Kawasaki, Kanagawa No. 1 Komukai Toshiba-cho, Ichiyuki-ku F-term (reference) in the Toshiba R & D Center 5F083 AD21 AD48 AD49 FR02 FR03 GA09 JA15 JA17 JA35 JA36 JA37 JA38 JA39 JA40 JA43 JA53 JA56 KA20 MA01 MA06 MA15 MA16 MA17 MA20 PR18 PR34 PR40 PR42 PR52 ZA11 ZA12

Claims (4)

[Claims] 1. A capacitor using a dielectric film composed of a composite oxide film containing at least two or more metal elements between a pair of electrodes is formed, and an insulating oxide film and a wiring layer are further formed on the capacitor. When manufacturing a laminated semiconductor device, the step of forming the capacitor includes: a first electrode forming step of forming a first electrode; and a dielectric film forming step of forming the dielectric film on the first electrode. A second electrode forming step of forming a second electrode on the dielectric film; a dielectric film forming step and a second electrode forming step between the first electrode forming step and the dielectric film forming step And at any time after the second electrode forming step, the temperature is increased at a rate of 0.5 × 133.322 Pa or more and 500 × 133.322 Pa or less under a reduced pressure.
Performing a rapid heat treatment at 0 ° C./sec or more. 2. The method for manufacturing a semiconductor device according to claim 1, wherein said rapid heat treatment under reduced pressure is performed at 0.5 × 133.322 Pa.
A method for manufacturing a semiconductor device, wherein the method is performed under an oxygen partial pressure of 500 × 133.322 Pa or less, an ozone partial pressure, or an atmosphere having an ozone partial pressure ratio of 1% or more. 3. The method of manufacturing a semiconductor device according to claim 1, wherein said dielectric film is a ferroelectric film,
The method of manufacturing a semiconductor device according to claim 1, wherein the capacitor is a capacitor for storing electric charge of a memory cell of an FRAM. 4. The method of manufacturing a semiconductor device according to claim 1, wherein said dielectric film is a high dielectric constant dielectric film, and said capacitor is a capacitor for storing electric charge of a memory cell of a DRAM. A method for manufacturing a semiconductor device, comprising: