JP2001358225A - Dual-gate semiconductor device having barrier layer containing nitrogen and oxygen and method of manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a dual-gate semiconductor device capable of solving a problem associated with boron diffusion, and a method of manufacturing the same. SOLUTION: In a form of embodiment, the dual-gate semiconductor device contains a low-voltage region where a first gate dielectric are formed thereon and a diffusion barrier layer containing nitrogen and oxygen is formed on the first gate dielectric, and a high-voltage region where a second gate dielectric having a thickness thicker than that of the first gate dielectric is formed thereon and the diffusion barrier layer does not exist.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

FIELD OF THE INVENTION The present invention relates generally to semiconductor devices, and more particularly to a dual gate semiconductor device having a nitrogen and oxygen containing barrier layer formed on a gate dielectric.

[0002]

2. Description of the Related Art In the integrated circuit (IC) industry, it has become necessary to integrate dual gate oxide layers on a single integrated circuit device. One motivation for performing dual gate oxide processing is that high performance transistors require thin gate dielectric regions and require low voltage (eg,
While operating at 1.8V to 2.5V), most conventional external peripherals generally require higher operating voltages, such as 3.3V to 5.0V. When interfacing a low voltage, high performance metal oxide semiconductor (MOS) transistor to a higher voltage device, the input and output (I / O) buffers of the IC typically require higher external peripheral device voltages. Designed to include a thicker gate dielectric region compatible with
Low voltage transistors with ultra-thin gate oxides have been designed. Further, modern microcontroller units and digital signal processors integrate several different types of technology on a single integrated circuit. For example, high-speed logic, power logic, static random access memory, non-volatile memory, embedded dynamic random access memory, analog circuits,
And other devices and technologies are contemplated for integration on the same integrated circuit die. Many of these devices require different gate dielectric processing and different gate dielectric layers.

[0003]

While dual gate semiconductor devices have adequately addressed design problems, they are not without their problems. For example, the gate oxide thickness of low voltage transistors has substantially decreased and continues to decrease. These ultra-thin oxides have been found to have boron diffusion problems that are often not associated with thicker gate oxides. Furthermore, ultra-thin gate oxides have been challenging to achieve high quality. As will be readily appreciated, the gate electrode is generally doped by the same ion implantation process as the source and drain regions. For example, boron is often implanted to form the source and drain in a P-channel metal oxide semiconductor field effect transistor (MOSFET) and creates a P-type polysilicon gate electrode by being implanted into the MOSFET gate electrode. I do. However, because boron is such a "light" atom, boron implanted into the polysilicon gate electrode can easily diffuse down along the grain boundaries and into the gate oxide. Since the gate oxide of non-I / O transistors is continuously reduced, it is not currently possible to prevent boron from diffusing into the underlying channel region. Additional boron diffusion from the gate electrode to the channel region can affect device parameters of the semiconductor device, particularly the threshold voltage, gate leakage current and transistor reliability.

Therefore, what is needed in the art is a dual gate semiconductor device that does not suffer from the problems associated with current dual gate semiconductor devices.

[0005]

SUMMARY OF THE INVENTION To address the above-mentioned shortcomings of the prior art, the present invention provides a dual gate semiconductor device and a method of manufacturing the same. In one embodiment, a dual gate semiconductor device comprises a low voltage region having a first gate dielectric formed thereon having a diffusion barrier layer having nitrogen and oxygen formed thereon, and a first gate region. A second gate dielectric thicker than the dielectric is formed thereon and includes a high voltage region without a diffusion barrier layer.

Accordingly, in one aspect, the present invention provides:
Dual gate semiconductor device having a diffusion barrier layer containing nitrogen and oxygen formed on a first gate dielectric and a method of fabricating the same to reduce gate leakage and limit boron implantation Extend the life of the device.

[0007] In one particular embodiment, the second gate dielectric has a thickness of about 3.5 nm and the first gate dielectric ranges from about 1.0 nm to about 2.0 nm. Having a thickness. In an alternative embodiment, the first gate dielectric is a densified oxide. In another embodiment, the first gate dielectric comprises a boron-doped source /
The drain region is relevant. In other embodiments, the diffusion barrier layer has a thickness ranging from about 0.5 nm to about 1.0 nm, and includes a low pressure chemical vapor deposition (LPCVD) process, a plasma chemical vapor deposition (PECVD) process, It may be deposited using other similar processes. In a preferred embodiment, the diffusion barrier layer is an oxynitride barrier layer.

[0008] In another aspect, the first and second gate dielectrics comprise an oxide, but in a preferred aspect, the first and second dielectrics comprise silicon dioxide. In another aspect, a first gate is formed over the diffusion barrier layer. In an alternative aspect, the first gate forms a gate of a P-type channel metal oxide semiconductor (PMSO) device. In an alternative aspect, a second gate is formed over the second gate dielectric.

Another embodiment of the present invention provides an integrated circuit in which the above-described dual gate semiconductor device is provided. The present integrated circuit includes (1) the dual gate semiconductor device formed on a substrate, (2) a dielectric layer formed on a dual gate transistor, and (3) a dual gate semiconductor formed in the dielectric layer. An interconnect structure forming an arithmetic integrated circuit by interconnecting the transistors. In another embodiment, the integrated circuit further comprises C
Includes MOS devices, BiCMOS devices, bipolar devices or other similar devices.

The foregoing has outlined rather broadly preferred and alternative features of the present invention so that those skilled in the art may better understand the detailed description of the invention that follows. Additional features of the invention forming the subject of the claims of the invention are set forth below. Those skilled in the art will appreciate that the disclosed concepts and particular embodiments can be readily used as a basis for designing or modifying other configurations that accomplish the same purpose of the invention. . Also, those skilled in the art will recognize that such equivalent constructions do not depart from the spirit and scope of the invention in its broadest form.

For a more complete understanding of the present invention, reference is now made to the following description taken in conjunction with the accompanying drawings.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring first to FIG. 1A, there is shown a partial cross-sectional view of a dual gate semiconductor device 100 at an early stage of fabrication. Dual gate semiconductor 10
0 includes a semiconductor wafer substrate 105 on which a shallow trench isolation structure 110 is formed. Shallow trench isolation structure 110 may be formed by selectively reactive ion etching trench 120 in a portion of substrate 105. If desired, a liner 115 may be formed in the trench 120. Preferably, liner 115 is a thin thermally grown silicon dioxide layer or an oxynitride layer. Most of the trenches are then filled with a dielectric fill material 122 such as tetraethylorthosilicate (TEOS) using high density plasma or a similar process. The TEOS material is chemically mechanically polished (CMP) or planarized using a similar procedure provided with the trench isolation structure 110. Note that the illustrated trench isolation structure 1
Instead of 10, other isolation schemes such as local oxidation of silicon (LOCOS) or polysilicon buffer (PBL) may be used. Further, the semiconductor wafer substrate 105 includes a dual gate semiconductor device 10 including a substrate arranged at a wafer level or a substrate arranged above a wear level.
Any substrate located at zero.

After the formation of the shallow trench isolation structure 110, a first layer 135 of a thin dielectric material is grown in a conventional manner over the entire surface of the dual gate semiconductor device 100, including the low voltage region 125 and the high voltage region 130. .
Further, those skilled in the art know that any other deposition technique known to be consistent with the design of dual gate semiconductor device 100 may be used. 1
In one embodiment, the first layer 135 of dielectric material may be an oxide layer, such as a silicon dioxide layer. However,
Other dielectric materials may be used if desired. In a preferred embodiment, the first layer 135 of dielectric material comprises
It has a thickness ranging from about 1.0 nm to about 2.0 nm.

Returning to FIG. 1B, a first layer 13 of dielectric material
FIG. 1A shows the partially completed dual gate semiconductor device 100 shown in FIG. 1A after the deposition of a diffusion barrier layer 140 containing oxygen and nitrogen on 5. Diffusion barrier layer 140
May be deposited using a number of conventional techniques.
For example, a low pressure chemical vapor deposition (LPCVD) process, a plasma enhanced chemical vapor deposition (PECVD) process, a rapid thermal CVD (RTCVD) process, or any other similar process may be used. The diffusion barrier layer 140
It preferably has a thickness ranging from about 0.5 nm to about 1.0 nm, but other thicknesses are within the scope of the invention. In a preferred embodiment, the nitrogen and oxygen diffusion barrier layers are oxynitride films having the chemical formula SiO _x N _Y. Here, x and y may be varied by changing gas flow rates, temperatures, and other conditions to obtain superior benefits.

As shown in FIG. 2, a photoresist layer is deposited, patterned, and washed away in a conventional manner, leaving a patterned photoresist region 210 over low voltage region 125. Photoresist area 2
10 protects the low voltage region 125 from a subsequent oxidation process. The first layer 135 of dielectric material and the diffusion barrier layer 140 (FIG. 1B) are then etched using conventional methods to form the first layer 220 of dielectric material on the low voltage layer 125. A part and a part of the diffusion barrier layer 230 remain. For example, plasma etching can be used to remove nitrogen and oxygen containing materials, and hydrofluoric acid etching can be used to remove the first dielectric material. Following the etching, the photoresist region 21
0 is removed.

Referring to FIG. 3, a second layer 3 of dielectric material
Following the growth of 10 is the partially completed dual gate structure 100 shown in FIG. Second of dielectric material
Layer 310 is a first layer 135 of the dielectric material in FIG. 1A.
And grown in a conventional manner. The second layer of dielectric material 310 is preferably grown to a thickness greater than the first layer 135 of dielectric material, more preferably to a thickness of about 3.5 nm, but may be other thicknesses. Furthermore,
Since the portion of the diffusion barrier layer 230, which is a nitrogen and oxygen containing layer, blocks oxygen diffusion, the thickness of the portion of the diffusion barrier layer 230 and the portion of the first layer 220 of the dielectric material is equal to the thickness of the second layer of the dielectric material. If any is affected by layer 310, the effect is minimal. Conversely, portions of the nitrogen and oxygen containing layer or diffusion barrier layer 230 and portions of the first layer 220 of dielectric material may be densified, forming a slightly oxidized portion 320 on top. Therefore, the second layer 310 of the dielectric material is provided only on the high voltage region 130.

Referring to FIG. 4, there is shown the partially completed dual gate semiconductor device 100 shown in FIG. 3 after the gate material 410 has been deposited in a conventional manner. The gate material 410 may be any material currently used or future used as a gate of a transistor device, such as polysilicon. Portion of diffusion barrier layer 230 which is a nitrogen and oxygen containing layer and first layer 2 of dielectric material
The implantation of boron into the low voltage region 125, including the 20 portions, is not shown. After completion of all implant steps in both regions 125, 130, a thin capping layer 420, such as tungsten silicide (WSi), may be deposited in a conventional manner. The photoresist is then deposited, patterned, and washed away in a conventional manner to form a photoresist structure 430.

Then, the partially completed dual gate semiconductor device 100 shown in FIG. 4 is etched by a conventional method, and the photoresist 430 is removed, thereby completing the completed dual gate semiconductor device 50 shown in FIG.
0 remains. Completed dual gate semiconductor device 500
Are the low voltage region 125 and the high voltage region 130, respectively.
, A low-voltage transistor device 510 and a high-voltage transistor device 540. Low voltage transistor device 510 includes a first gate dielectric 515 and a barrier layer 520 formed over first gate dielectric 515. As described above, the first gate dielectric has a thickness ranging from about 1.0 nm to about 2.0 nm, and the barrier layer 520 has a thickness ranging from about 0.5 nm to about 1.0 nm. are doing.
The low voltage transistor device 510 further includes a barrier layer 520
The first gate 525 and the first gate 52 formed thereon
5 formed on the first capping layer 530. As described above, boron is diffused in the first gate 525. Thereby, the first gate 525
May form a gate of a P-type channel metal oxide semiconductor (PMOS). As such, the barrier layer 520 prevents boron from diffusing into the underlying channel region. Thus, threshold voltage, gate leakage current and transistor reliability are not affected, and low voltage transistor 510 can operate at very high speed and low voltage.

The high voltage transistor device 540 includes a second gate dielectric 545 and the second gate dielectric 545.
A second gate 550 is formed on the substrate. Furthermore,
The high voltage transistor device 540 does not have a barrier layer 520. As mentioned above, the second gate dielectric preferably has a thickness of about 3.5 nm. First gate 525
Similarly, a second capping layer may be formed on the second gate 550. High voltage transistor device 54
0 has a sufficient oxide thickness to provide an appropriate amount of drive current to operate dual gate semiconductor device 500.

Referring briefly to FIG. 6, there is shown a cross-sectional view of a conventional integrated circuit 600 that may be manufactured in accordance with the principles of the present invention. Integrated circuit 600 may be a CMOS device, a BiCMOS device, a bipolar device, or any other type of similar device. FIG. 6 shows a low-voltage transistor 510 and a high-voltage transistor 5.
The components of a conventional integrated circuit 600 are shown, including 40, a first gate dielectric 515, a second gate dielectric 545, a barrier layer 520 and a dielectric layer 615. An interconnect structure 620 may be formed in the dielectric layer 615. The interconnect structure 620 includes the transistor 51
0,540 are connected to other areas of the integrated circuit 600. Also shown are tabs 623, 625, source region 633, and drain region 635 formed in a conventional manner, all of which are formed on substrate 640.

Having described the invention in detail, those skilled in the art will appreciate that various modifications and substitutions can be made in this specification without departing from the spirit and scope of the invention in its broadest form. You should understand.

[Brief description of the drawings]

FIG. 1A shows a partial cross-sectional view of a dual gate semiconductor device at an early stage of manufacturing.

FIG. 1B shows the partially completed dual-gate semiconductor device shown in FIG. 1A after a conventional method of depositing a nitrogen and oxygen containing layer on a first layer of dielectric material.

FIG. 2 illustrates a process for etching a nitrogen and oxygen containing layer and a first layer of a dielectric material.

FIG. 3 shows the partially completed dual gate structure shown in FIG. 2 following the growth of a second layer of dielectric material.

FIG. 4 after deposition of the gate material in a conventional manner;
4 shows the partially completed dual gate semiconductor device shown in FIG.

FIG. 5 shows a completed dual gate semiconductor device.

FIG. 6 illustrates a cross-sectional view of a conventional integrated circuit that may be manufactured in accordance with the principles of the present invention.

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Silesh Chitipeddi United States 18104 Pennsylvania, Allentown, Leneip Trail 308 (72) Inventor Ema United States 32837 Florida, Orlando, Runyon Circle 2569 (72) Inventor Plastic Dip K. Roy United States 32819 Florida, Orlando, Hidden Ivy Court 7706 F-term (reference) 4M104 AA01 BB01 CC05 EE03 EE14 FF14 GG09 GG10 GG13 GG14 GG15 GG16 HH04 5F048 AA07 AC01 AC03 AC05 BA01 BB01 BB07 BB08 BB11 BB11 BB11 BB11 BB11 BB11 BB11 BB11 BB11 BD04 BD15 BF04 BF07 BF25 BF29 BF30 BJ01

Claims (34)

[Claims] 1. A dual-gate semiconductor device, wherein a first gate dielectric is formed thereon, and a diffusion barrier layer containing nitrogen and oxygen is formed on the first gate dielectric. A low-voltage region and a high-voltage region having a second gate dielectric having a greater thickness than the first gate dielectric formed thereon and without the diffusion barrier layer. Dual-gate semiconductor device. 2. The method of claim 2, wherein the second gate dielectric has a thickness of about 3.5n.
m, and the first gate dielectric has a thickness of about 1.0 m.
The dual gate semiconductor device according to claim 1, having a thickness ranging from about nm to about 2.0 nm. 3. The diffusion barrier layer according to claim 1, wherein the diffusion barrier layer is an oxynitride barrier layer having the general formula SiO _X N _Y , wherein X and Y may be changed by changing a gas flow rate and a temperature. Dual gate semiconductor device. 4. The dual gate semiconductor device according to claim 3, wherein said oxynitride barrier layer has a thickness ranging from about 0.5 nm to about 1.0 nm. 5. The dual gate semiconductor device according to claim 1, wherein said first and second gate dielectrics are oxides. 6. The method according to claim 5, wherein the oxide is silicon dioxide.
The dual gate semiconductor device according to the above. 7. The dual gate semiconductor device according to claim 1, further comprising a first gate formed on said diffusion barrier layer. 8. The dual gate semiconductor device according to claim 7, further comprising a second gate formed on said second gate dielectric. 9. The dual gate semiconductor device according to claim 7, wherein said first gate forms a gate of a P-type channel metal oxide semiconductor (PMOS) device. 10. The dual gate semiconductor device of claim 9, further comprising a boron doped source / drain region associated with said first gate. 11. The dual gate semiconductor device according to claim 10, wherein said diffusion barrier layer suppresses boron implantation. 12. The dual gate semiconductor device according to claim 1, wherein said first gate dielectric is a densified oxide. 13. A method for forming a dual gate semiconductor device, comprising: forming a first gate dielectric over at least a portion of a low voltage region of the dual gate semiconductor device; Forming a diffusion barrier layer comprising nitrogen and oxygen on the gate dielectric; and forming a second gate over at least a portion of the high voltage region of the dual gate semiconductor device, the second gate being thicker than the first gate dielectric. Forming a dielectric and not forming said diffusion barrier layer in said high voltage region. 14. The method of claim 1, wherein forming the first and second gate dielectrics comprises removing the first gate dielectric by about 1.0 nm.
To a thickness ranging from about 2.0 nm to about 2.0 nm;
Forming said gate dielectric to a thickness of about 3.5 nm. 15. Forming a diffusion barrier layer comprises forming an oxynitride diffusion barrier layer having the general formula SiO _x N _Y , wherein X and Y can be changed by changing gas flow rates and temperatures. 14. The method according to claim 13, wherein the method comprises: 16. The step of forming an oxynitride diffusion barrier layer comprises forming the oxynitride film diffusion barrier layer from about 0.5 nm to about 1.
The method of claim 15 including forming to a thickness of over 0 nm. 17. The method of claim 13, wherein forming the diffusion barrier layer comprises forming the diffusion barrier layer to a thickness ranging from about 0.5 nm to about 1.0 nm. 18. The method of claim 13, wherein forming the first and second gate dielectrics comprises forming an oxide. 19. The method of claim 18, wherein forming an oxide comprises forming silicon dioxide. 20. The method of claim 13, further comprising forming a first gate over said diffusion barrier layer. 21. The method of claim 13, further comprising forming a second gate over said second gate dielectric. 22. The method of claim 20, wherein forming the first gate comprises forming a P-type channel metal oxide semiconductor (PMOS) device. 23. The method of claim 22, further comprising forming a boron-doped source / drain region associated with the first gate. 24. The method of claim 13, wherein forming the diffusion barrier layer reduces gate leakage and suppresses boron implantation.
The described method. 25. The method of claim 13, wherein forming the diffusion barrier layer comprises forming the diffusion barrier layer using a low pressure chemical vapor deposition (LPCVD) process or a plasma chemical vapor deposition (PECVD) process. the method of. 26. The method of claim 13, further comprising densifying said first gate dielectric during formation of said second gate dielectric. 27. A low-voltage region having a first gate dielectric formed thereon, and a diffusion barrier layer comprising nitrogen and oxygen formed on the first gate dielectric; A dual gate transistor provided on a substrate having a second gate dielectric having a thickness greater than the thickness of the gate dielectric formed thereon and including a high voltage region without the diffusion barrier layer; A dielectric layer formed on the gate transistor, and an interconnect structure formed in the dielectric layer and interconnecting the dual gate transistors to form an arithmetic integrated circuit. Integrated circuit. 28. The method of claim 28, wherein the first gate dielectric has a thickness of about 1.0.
28. The semiconductor device of claim 27, wherein the second gate dielectric has a thickness ranging from about 3.5 nm to about 2.0 nm and the second gate dielectric has a thickness of about 3.5 nm.
An integrated circuit as described. 29. The diffusion barrier layer of the general formula SiO _x N _Y
28. The integrated circuit according to claim 27, wherein the oxynitride barrier layer comprises: X and Y can be varied by changing gas flow rates and temperatures. 30. The semiconductor device of claim 2, further comprising a second gate formed over the second gate dielectric.
7. Integrated circuit. 31. A first electrode formed on the diffusion barrier layer.
28. The integrated circuit according to claim 27, further comprising a gate. 32. The integrated circuit of claim 31, wherein said first gate forms a gate of a P-type channel metal oxide semiconductor (PMOS) device. 33. The integrated circuit of claim 27, wherein said diffusion barrier layer reduces gate leakage and suppresses boron implantation. 34. The integrated circuit of claim 27, further comprising a device selected from the group consisting of a CMOS device, a BiCOMS device, and a bipolar device.