JP2001358060A - Method for manufacturing semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enhance overlapping precision in a multiple exposure step. SOLUTION: A method for overlapping comprises a first step L1 of collecting and storing information of a photomask for forming a first pattern, information of an exposure device used to form the first pattern and information of exposure conditions and collecting and storing information of a photomask for forming a second pattern, information of the exposure device used to form the second pattern and information of the exposure conditions, a second step L2 of measuring and storing positional deviation amounts of the first and second patterns, and a step S4 of thereafter calculating a corrected value of a superposition from the information of the exposure device used for the exposure, the information of the exposure conditions and the positional deviation amount of the step L2. Thus, unevenness in the overlapping allowance and a wafer overlapping precision can be suppressed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device manufacturing technique, and more particularly, to an overlay technique in an exposure process.
For example, the present invention relates to a technique effective for forming a circuit pattern on a wafer in a method of manufacturing a semiconductor integrated circuit device (hereinafter, referred to as an IC).

[0002]

2. Description of the Related Art In general, an IC manufacturing method includes a process in which a pattern (hereinafter, referred to as a mask pattern) drawn on a photomask (hereinafter, referred to as a mask) called a reticle is transferred to a wafer by lithography and etching. It is repetition. In this lithography and etching process, the first pattern transferred to the wafer in the previous step and the second pattern transferred to the subsequent step need to be overlapped with high accuracy.

Therefore, in an exposure step in an IC lithography process, the following superposition method is employed to superimpose the first pattern and the second pattern with high accuracy. The first pattern and the second pattern are formed on the wafer by lithography and etching processes, and the amount of misalignment between the first pattern and the second pattern is measured by a misalignment measuring device. A correction value that minimizes the shift amount is obtained. Then, in the step of exposing each wafer to the lot, the correction based on this correction value is performed.

Japanese Patent Application Laid-Open No. 3-96219 discloses an example of a method of aligning an exposure apparatus.

[0005]

However, in the above-described overlay method, there is a limit in improving the overlay accuracy because differences in the exposure apparatus used and variations in exposure conditions are not taken into account.

An object of the present invention is to provide a method of manufacturing a semiconductor device capable of further improving the overlay accuracy.

[0007] The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0008]

The outline of a typical invention among the inventions disclosed in the present application is as follows.

That is, a displacement amount storing step of measuring and storing a displacement amount between a first pattern and a second pattern formed by being superimposed on the same wafer, respectively, and a step for storing the first pattern. A first pattern exposure information storing step of collecting and storing information on the first pattern forming photomask, information on the exposure apparatus used for forming the first pattern, and information on the exposure conditions; and A second pattern exposure information storing step of collecting and storing information on the second pattern forming photomask used for forming, information on the exposure apparatus used for forming the second pattern, and information on exposure conditions, and ,
When the second pattern is formed by being superimposed on the first pattern on a wafer using the second pattern forming photomask, information on an exposure apparatus and information on exposure conditions used for the exposure, Calculating a correction value for superposition from the positional deviation amount in the positional deviation amount storage step.

According to the above-described means, when performing an exposure process on a wafer, an appropriate correction value is calculated for each exposure process based on past actual data in the same exposure process, so that the wafers are superimposed in relation to each other. Since the overlay accuracy of the first pattern and the second pattern can be increased, the overlay margin (margin) can be set small, and the variation in overlay accuracy between wafers can be reduced. Can be.

Other aspects of the invention disclosed in the present application are as follows.

In a method for manufacturing a semiconductor device in which a pattern is formed by exposure using 1.2 or more masks, (1) 1
A step of measuring and storing the amount of displacement between the pattern formed on the first sheet and the pattern formed on the second sheet, (2) information on an exposure apparatus, mask information, and wafer exposure used for exposing the first sheet A step of collecting and storing information, (3) a step of collecting and storing exposure apparatus information, mask information, and wafer exposure information used for exposing the second image, and (4) a step of exposing the second image this time. Calculating an alignment target value from a combination of the exposure apparatus information, mask information, wafer exposure information, and the information (1) used for forming the first pattern in this lot, based on the alignment target value A method for manufacturing a semiconductor device, comprising: aligning to form an exposure pattern.

2. In the method of manufacturing a semiconductor device in which a pattern is formed by exposure using three or more masks, in performing the alignment for the third exposure, the following steps (1) and (2) are performed. A step of collecting and storing exposure apparatus information, mask information, and wafer exposure information used for exposing the third sheet, (2) exposure apparatus information, mask information, and wafer exposure information used for exposing the third sheet this time And information used by the lot for forming the first and second patterns and 1
A method for manufacturing a semiconductor device, comprising: a step of calculating a target value for alignment from a positional deviation amount between a first sheet and a second sheet; and forming an exposure pattern by performing alignment based on the target value for alignment.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a flow chart showing an overlay method in an IC manufacturing method according to an embodiment of the present invention. FIG. 2 is a block diagram showing a system used for the superposition method. FIG. 3 is a process chart showing a method of manufacturing an IC for explaining the method of superposition. FIG. 4 is a plan view and a cross-sectional view showing a pattern formed by the process.

As shown in FIG. 2, the system used in the overlaying method according to the present embodiment includes a first exposure device 1, a second exposure device 2, and a displacement measuring device 3. Are connected to a host computer 5 by a network 4. Host computer 5
Is connected to a data storage unit 6.
Stores various data described later, and transmits the stored data to the host computer 5 according to the instruction. Note that a reduced projection exposure apparatus (stepper) is used as each of the first exposure apparatus 1 and the second exposure apparatus 2, and both of them have individual differences, though slightly.

In this embodiment, in order to make the explanation easy to understand, the circuit pattern shown in FIG. 4 will be used as a specific example, and the lithography step in the method for manufacturing the IC shown in FIG. 3 will be mainly described. explain.

In FIG. 4, as shown in FIGS. 4A and 4A, an isolation 14 for element isolation is formed on a substrate 11 of a wafer 10. ). As shown in (b) and (b ′), the gate electrode 15 is formed (a second pattern exposure step). Next, the SiO ₂ film 16 is deposited, and a contact hole 17 is formed as shown in (c) and (c ′) (third pattern exposure step).

Next, a method of manufacturing an IC will be described with reference to FIG. 3, and a method of superposition according to the present embodiment will be described with reference to FIG.

First, as shown in FIG. 3, in a first pattern exposure step 21, a resist film (not shown) in which an isolation 14 as a first pattern is deposited on the substrate 11 is formed. Exposed. That is, a first mask (not shown) on which a mask pattern for transferring the isolation 14 is drawn, for example,
The resist pattern attached to the first exposure apparatus 1 exposes a mask pattern of the first mask on the substrate 11.

In the superposition method according to the present embodiment, in the first step L1 of the flow shown in FIG. 1A, the collection and storage of information on the pattern exposure process is executed by the host computer 5. You. That is, the host computer 5 determines the information of the first mask as the information of the mask used for performing the exposure step 21 of the first pattern, the information of the first exposure apparatus 1 as the information of the exposure apparatus, and the exposure conditions at that time. The information and the information of the wafer 10 are collected, and the information is stored in the data storage unit 6 together with the key information. At this time, the first exposure apparatus 1 transmits information on the requested exposure conditions to the host computer 5 via the network 4 and stores the information in the data storage unit 6 via the host computer 5.

The key information includes information on a product name, a lot name, a wafer name, date and time, and the like. Mask information includes mask individual identification marks, mask fabrication errors,
There is information on the type of mask and the like. As the information of the exposure apparatus, the unit, illuminance, exposure illumination wavelength, atmospheric pressure, temperature, length measurement laser wavelength, automatic focus correction value, automatic magnification correction value,
Information on image distortion, device trouble, etc. is available. The exposure condition information includes information on the illumination system σ value, the projection optical system NA, the exposure amount, the used alignment mark, the wafer alignment detection method, the wafer alignment measurement amount, the wafer alignment correction amount, and the like.

As shown in FIG. 3, the transferred wafer 10 is sent to a first pattern developing step 22 where it is developed. By this development, the isolation 14 is made visible in the resist film of the wafer 10.

Next, the wafer 10 on which the pattern of the isolation 14 as the first pattern has been exposed is sent to the first pattern misalignment measuring step 23, where the misalignment of the first pattern is measured. For example, when there is a reference pattern before the isolation 14 pattern is formed, the displacement measurement apparatus 3 measures the displacement between the reference pattern and the isolation 14 pattern. . If there is no such partner, the measurement is skipped.

The displacement amount measuring device 3 which measures the displacement amount in this manner transmits the measured value to the host computer 5.
Via the network 4. In the second step L2 of the flow shown in FIG. 1A, the host computer 5 stores the measured value from the displacement measuring device 3 in the data storage unit 6 as the displacement of the first pattern.

As shown in FIG. 3, the wafer 10 whose positional deviation has been measured in the positional deviation measuring
Is sent to a first pattern etching step 24. In the first pattern etching step 24, the wafer 10 is etched using the resist film in which the pattern of the isolation 14 has been exposed as a mask, and as shown in FIGS. 4A and 4A, the isolation is performed. 14
Is formed.

Next, the wafer 10 is sent to a gate electrode film forming step 25. In the gate electrode film forming step 25,
A gate electrode film is formed on the wafer 10.

As shown in FIG. 3, the wafer 10 that has passed through the gate electrode film forming step 25 is sent to a second pattern exposure step 26. In a second pattern exposure step 26, the gate electrode 15 as a second pattern is exposed on a resist film (not shown) applied on the gate electrode film. That is, a second mask (not shown) on which a mask pattern for transferring the gate electrode 15 is drawn is mounted on, for example, the second exposure apparatus 2, and the mask pattern of the second mask is exposed on the resist film. You.

At this time, in the superposition method according to the present embodiment, in the first step L1 of the flow shown in FIG. 1A, collection and storage of information on the exposure step 26 of the second pattern is performed by the host. It is executed by the computer 5. That is, the host computer 5 transmits the information of the second mask as the information of the mask used for performing the exposure step 26 of the second pattern, the information of the second exposure apparatus 2 as the information of the exposure apparatus, and the exposure conditions at that time. The information and the information of the wafer 10 are collected, and the information is stored in the data storage unit 6 together with the key information. On this occasion,
The second exposure apparatus 2 transmits information on the requested exposure conditions and the like to the host computer 5 via the network 4 and stores the information in the data storage unit 6 via the host computer 5.

The contents of key information, mask information, exposure apparatus information, and exposure condition information are the same as those in the first pattern exposure step.

As shown in FIG. 3, the transferred wafer 10 is sent to a second pattern developing step 27 where it is developed. By this development, the pattern of the gate electrode 15 is revealed on the resist film of the wafer 10.

The wafer 10 in which the pattern of the gate electrode 15 as the second pattern has been exposed is sent to the second pattern misalignment measuring step 28, where the misalignment of the second pattern is measured. For example, the displacement measuring device 3
The amount of displacement between the pattern of the isolation 14 as the first pattern and the pattern of the gate electrode 15 as the second pattern is measured.

The displacement measuring device 3 which measures the displacement as described above transmits the measured value to the host computer 5.
Via the network 4. In the second step L2 of the flow shown in FIG. 1A, the host computer 5 causes the data storage unit 6 to store the measurement value from the displacement measurement device 3 as the displacement of the second pattern.

As shown in FIG. 3, the wafer 10 whose positional deviation has been measured in the second pattern positional deviation measuring step 28 is sent to the second pattern etching step 29. In the etching step 29 of the second pattern, the gate electrode 15 is etched using the resist film in which the pattern of the gate electrode 15 has been exposed as a mask, and the gate electrode 15 is shown on the wafer 10 in FIGS. 4B and 4B ′. It is formed to be.

Next, the wafer 10 is sent to a step of forming a contact hole and the like, but the description of this embodiment is omitted as shown in FIG. Note that the loop shown in FIG. 1A is also performed in the step of forming the contact hole as the third pattern.

Thereafter, when the wafer 10 of the same lot as the previously processed wafer is put into the exposure step 26 of the second pattern, the host computer 5 executes the flow shown in FIG. . First, in the first step S1, "is there any past pattern exposure data of the present process?"
Is determined. If no (NO), the second step S
2 and the pilot exposure is performed, and the loop of FIG. 1A is executed in the third step S3. If there is (YES), the process proceeds to the fourth step S4. Although the case of the same lot is described, the lot may not be the same.
That is, when the lot is changed, the same processing is executed in the changed lot based on the information of the lot before the change.

In the fourth step S4, the host computer 5 reads out the information on the exposure apparatus, the information on the exposure condition, and the amount of displacement previously stored in the data storage section 6, and proceeds to the fifth step S5. In S5, an overlay correction value is calculated by the following method.

The misalignment Q _{1 in} the first pattern exposure step 21 is obtained by the following equation (1), and the misalignment Q ₂ in the second pattern exposure step 26 is obtained by the following equation (2). Q ₁ = a ₁ + b ₁ + f ₁ + g ₁ (1) Q ₂ = a ₂ + b ₂ + f ₂ + g ₂ (2) Here, a ₁ and a ₂ are displacement amounts, and data It is a measurement value of the displacement amount measurement device stored in the storage unit 6. b ₁ and b ₂ are information on exposure conditions, f ₁ and f ₂
The information of the exposure apparatus, g ₁ and g ₂ are the information of the mask.

The information of the first pattern exposure step 21 and the second pattern exposure step 26 of the wafer to be superimposed this time
Equations (1) and (2) are simplified by the following assumptions by using the combination data of the same condition stored in the past from the information of (1). 1) Delete mask information from variables limited to data using the same mask combination. However, only the accuracy of the mask remains. 2) Limit the data to data using only the same combination of exposure conditions, and delete the information of the exposure conditions from the variables. If there is no correlation between the alignment measurement result and the residual alignment error, it is deleted from the correction term. However, correction data between wafers remains. 3) In the information of the exposure apparatus, leave parameters correlated with the residual alignment error, and delete others.

Thus, the following equation (3) is obtained. Misalignment (first pattern exposure step, second pattern exposure step) = positional deviation amount (first pattern exposure step, second pattern exposure step) + b [wafer alignment correction amount (first pattern exposure step) , Second pattern exposure step), illumination alignment error (first pattern exposure step, second pattern exposure step)] + f [image distortion matching error (first pattern exposure step using apparatus, second pattern exposure apparatus) Exposure process use device)] + g [mask position accuracy (first mask, second mask)] (3) Note that the wafer alignment correction amount refers to the items and amounts that the exposure apparatus performs alignment measurement and automatically corrects. Is a correction amount input from outside.

Assuming that there is no variation in time, the following equation (4) can be simplified. The following constants can be evaluated and determined in advance using an absolute length measuring device or the like. If no precision is required, this constant can be omitted. b [illumination alignment error (first pattern exposure step, second pattern exposure step)]; constant 1 f [image distortion matching error (first pattern exposure step use apparatus, second pattern exposure step use apparatus) ]; Constant 2 g [mask position accuracy (first mask, second mask)]; constant 3 misalignment (first pattern exposure step, second pattern exposure step) = positional deviation amount (first pattern exposure step) , Second pattern exposure step) + b [wafer alignment correction amount (first pattern exposure step, second pattern exposure step)] + constant (1, 2, 3) (4)

The alignment correction items of equation (4) are obtained for each correction item of offset X and Y, wafer rotation, wafer orthogonality, wafer scale X and Y, shot rotation, and shot magnification. These correction items are described in detail in JP-A-3-96219.

The correction amount input to the second exposure apparatus 2 used in the exposure step 26 of the second pattern executes averaging using the following statistical method from the equation (4). In the following equation, N is the number of samples, and is a moving average of N latest data. Correction amount (second pattern exposure step) = − Σ [misalignment (first pattern exposure step, second pattern exposure step)] / N

After calculating the correction amount as described above, in the sixth step S6, the host computer 5 outputs the correction value to the second exposure device 2 which performs the exposure step 26 of the second pattern. Therefore, in the exposure step 26 of the second pattern, the pattern of the gate electrode 15 as the second pattern is exposed on the resist film deposited on the wafer 10 using this correction value.

That is, in the second pattern exposure step 26, a second mask (not shown) on which a mask pattern for transferring the gate electrode 15 is drawn is mounted on the second exposure apparatus 2, and the second mask Is exposed on the resist film deposited on the wafer 10. At this time, the correction value calculated in the fifth step S5 in the superposition method according to the present embodiment is the same as the sixth step S5.
6, is used in the alignment in the seventh step S7, and is exposed in the eighth step S8.

On the other hand, in the overlay method according to the present embodiment, the host computer 5 which has output the correction value proceeds to a ninth step S9, and executes the flow of FIG. . That is, the host computer 5 outputs information on the second mask as information on the mask used for performing the exposure step 26 of the second pattern,
Similarly, information on the second exposure apparatus 2 as information on the exposure apparatus,
The information on the exposure conditions at that time and the information on the wafer 10 are collected, and the information is stored in the data storage unit 6 together with the key information. Next, the host computer 5 stores the measurement value from the displacement amount measuring device 3 in the data storage unit 6 as the displacement amount of the second pattern.

Thereafter, the IC manufacturing method shown in FIG. 3 is performed on wafers in the same lot, and the superposition method shown in FIG. 1 is performed. Then, when the processing for all the wafers of the same lot is completed, the overlay method according to the present embodiment ends.

According to the above embodiment, the following effects can be obtained.

1) When an exposure process is performed on a wafer, an appropriate correction value is calculated for each exposure process based on past performance data in the same exposure process, so that the first pattern to be superimposed on each other can be obtained. Since the overlay accuracy with the second pattern can be increased, the overlay margin (margin) can be set small, and the variation in overlay accuracy between wafers can be reduced.

2) By setting the overlay margin small in the above 1), the circuit pattern formed on the wafer can be reduced, so that miniaturization and high integration of the IC can be promoted.

3) The quality and reliability of the IC can be improved by suppressing the variation in the overlay accuracy between wafers in the same lot.

4) When the past performance data is accumulated, the pilot work for ensuring the overlay accuracy can be omitted, so that the productivity can be improved.

Although the invention made by the inventor has been specifically described based on the embodiment, the invention is not limited to the embodiment, and various modifications can be made without departing from the gist of the invention. Needless to say, there is.

For example, the present invention is not limited to calculating the correction value for the superposition of the first pattern and the second pattern. Calculate the correction value for the superposition of the pattern and the second pattern, the correction value for the superposition of the second pattern and the third pattern, and the correction value for the superposition of the first pattern and the third pattern, respectively. can do. In the case where the correction value for the superposition of the first pattern and the third pattern is calculated, the exposure step of the third pattern corresponds to the exposure step of the second pattern according to the embodiment. .

In the above description, the case where the invention made by the present inventor is mainly applied to the process until the contact hole is formed in the field of application, which is the background of the application, has been described. Instead, the present invention can be applied to an electrode forming step, a multilayer wiring forming step, and the like in an IC manufacturing method, and further to a general method of manufacturing a semiconductor device such as a gate array.

[0055]

The effects obtained by typical aspects of the invention disclosed in the present application will be briefly described as follows.

When an exposure process is performed on a wafer, an appropriate correction value is calculated for each exposure process based on past actual data in the same exposure process, so that the first pattern and the second Since the overlay accuracy with the pattern can be improved, the overlay margin can be set small,
Further, variation in overlay accuracy between wafers can be reduced.

[Brief description of the drawings]

FIG. 1 is a flowchart showing an overlay method in an IC manufacturing method according to an embodiment of the present invention;
(A) shows a flow of data collection and storage, and (b) shows a flow of exposure correction.

FIG. 2 is a block diagram showing a system used for the superposition method.

FIG. 3 is a process chart showing a method of manufacturing an IC for explaining the method of superposition.

FIG. 4 shows patterns formed by the respective steps, wherein (a), (b) and (c) are plan views,
(A '), (b'), (c ') are cross-sectional views.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... 1st exposure apparatus, 2 ... 2nd exposure apparatus, 3 ... Position displacement amount measuring apparatus, 4 ... Network, 5 ... Host computer, 6 ... Data storage part, 10 ... Wafer, 11 ... Substrate, 12 ... Source, 13: drain, 14: isolation, 15: gate electrode, 16: SiO ₂ film, 1
7 contact hole, 21 first pattern exposure step, 22 first pattern development step, 23 first pattern displacement measurement step, 24 first pattern etching step, 25 gate electrode film formation Step 26: Exposure step of second pattern 27: Development step of second pattern 2
8: Step of measuring the amount of displacement of the second pattern, 29: Step of etching the second pattern.

 ────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor Takeshi Kato 5-20-1, Josuihonmachi, Kodaira-shi, Tokyo F-term in the Semiconductor Group, Hitachi, Ltd. 5F046 DB05 FC04

Claims (1)

[Claims] 1. A displacement amount storing step of measuring and storing a displacement amount between a first pattern and a second pattern which are respectively formed by being superimposed on the same wafer, and used for forming the first pattern. A first pattern exposure information storing step of collecting and storing information on the first pattern forming photomask, information on the exposure apparatus used for forming the first pattern, and information on the exposure conditions; and A second pattern exposure information storing step of collecting and storing information on the second pattern forming photomask used for forming, information on the exposure apparatus used for forming the second pattern, and information on exposure conditions, and The exposure is performed when the second pattern is formed on the wafer by using the second pattern forming photomask so as to overlap the first pattern. Calculating a correction value for superposition from information on the exposure apparatus and information on the exposure conditions used for the exposure and the amount of misalignment in the misalignment amount storing step. Production method.