JP2001356465A - Mask for exposure and method for correcting its pattern - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a mask for exposure capable of suppressing shortening corresponding to the environment without increasing the chip area and a method for correcting its pattern. SOLUTION: A mask pattern having a line width below a stipulated value is selected from mask patterns each projecting from an element region, the distance from the selected mask pattern to an adjacent pattern is calculated and the mask pattern is corrected corresponding to the distance. The desired mask pattern can be formed corresponding to the surrounding environment.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to an exposure mask used in a lithography step in the manufacture of a semiconductor device and a method of correcting a pattern thereof.

[0002]

2. Description of the Related Art In recent years, demands for dimensional control of device patterns have become more and more severe with the increase in integration and speed of semiconductor devices. For this reason, there has been a difference between a design dimension and a finished dimension due to a resolution limit or the like in a wafer manufacturing process. As means for correcting this difference, various optical proximity correction methods (OPC = Optical Prox
imity Correction) has been proposed. OPC is the shape and size of devices caused by the wafer manufacturing process, such as by partially increasing the thickness of a mask or arranging a dummy pattern in consideration of the total process of a wafer or by making full use of optical simulation. Is to correct the change of

For example, FIG. 16 shows a pattern in which gate wirings are arranged. As shown in FIG. 16, since the corner of the end of the gate wiring is already at the resolution limit, the end of the finished gate wiring 32 becomes shorter than the designed mask pattern 31. This phenomenon is called shortening. This shortening becomes more conspicuous as the line width of the gate wiring 32 becomes thinner.

Therefore, as shown in FIG. 17, a correction pattern 33 in which the length of the end portion of the mask pattern 31 is uniformly extended from the gate wiring 35 of the desired pattern by OPC.
Also, a correction pattern 34 in which a hammer head is attached to the end of the mask pattern 31 has been created. As a result, shortening of the gate wiring 35 was suppressed.

[0005]

However, in the case of the above method, considering the case where the gate wirings are densely arranged, there is a limit value in the extension amount of the end portion of the mask pattern and the size of the hammer head. There was a problem that shortening could not be suppressed.

Therefore, it is necessary to design the space between the end portions of the mask pattern and the space between the mask patterns with a sufficient amount of extension or a margin so that a hammer head can be provided. However, a design with a margin leads to an increase in chip area. Therefore, there has been a demand for an OPC method capable of suppressing shortening even when gate wirings are densely arranged.

In an actual device, the surrounding environment varies depending on whether the gate wirings are densely arranged or sparsely arranged, and the amount of shortening also varies depending on the environment. Therefore, a method of uniformly applying a necessary correction amount in consideration of an environment having the largest shortening amount is simple, but a method of changing the correction amount according to the environment in consideration of an increase in chip area has been required.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to provide an exposure mask and an exposure mask capable of suppressing shortening in accordance with the environment without increasing the chip area. An object of the present invention is to provide a pattern correction method.

[0009]

The present invention uses the following means to achieve the above object.

A method of correcting a mask pattern according to the present invention is a method of correcting a mask pattern for forming a gate wiring of a transistor intersecting an element region, wherein a plurality of mask patterns protruding from the element region are formed. 1
Extracting the protruding portion of, and calculating the line width of the plurality of first protruding portions, determining whether the line width of the plurality of first protruding portions is smaller than a specified value, Extracting a second protrusion having a line width smaller than the specified value from the plurality of first protrusions, and calculating a distance from the second protrusion to an adjacent mask pattern; Creating a correction rule for the distance between the adjacent mask patterns, and performing a necessary correction on the protrusion in accordance with the correction rule to create a correction pattern.

The method of determining the specified value includes a step of extracting each line width of the arranged test patterns and a distance between adjacent test patterns; a step of extracting a distance between the adjacent test patterns and an amount of shortening for each line width. Determining the minimum line width as a specified value by a step of deriving a relationship between the minimum line width, a step of determining an allowable value of the shortening, and a step of extracting a minimum line width at which a maximum amount of the shortening is equal to or less than the allowable value. are doing.

The correction rule includes a step of extracting a line width of the arranged test patterns and a distance between adjacent test patterns; a step of providing a hammer head having a size h in the test patterns; Fixing the line width of the pattern, variously changing the size h of the hammer head, calculating the amount of shortening with respect to the distance between the adjacent test patterns, and determining the allowable value of the shortening; Changing the size h of the hammer head so that the shortening amount is equal to or less than an allowable value at all distances between the adjacent test patterns with respect to a fixed line width; Deriving a relationship between the distance between the adjacent test patterns with respect to the height h and the amount of shortening; Toningu amount is made by a step of size h is determined of the hammer head of each distance between the adjacent test pattern becomes less than the allowable value.

A first exposure mask according to the present invention is an exposure mask for forming a gate wiring of a transistor that intersects with an element region, wherein a plurality of first masks of the mask pattern protruding from the element region are formed. Extracting the protruding portion of, and calculating the line width of the plurality of first protruding portions, determining whether the line width of the plurality of first protruding portions is smaller than a specified value, Extracting a second protrusion having a line width smaller than the specified value from the plurality of first protrusions, and calculating a distance from the second protrusion to an adjacent mask pattern; ,
It is formed by a step of creating a correction rule for the distance between the adjacent mask patterns, and a step of performing a necessary correction on the protruding portion according to the correction rule to create a correction pattern.

A second exposure mask according to the present invention comprises a first mask pattern provided with a hammer head at an end of the pattern, and a second mask pattern having a longer end of the pattern. The first mask pattern and the second mask pattern are alternately arranged in the left-right direction and the opposing direction.

A third exposure mask according to the present invention includes a first mask pattern in which a plurality of first hammer heads having a fixed size and a fixed interval are provided on a side surface of an end of the pattern. A plurality of second hammer heads having the same size and the same interval as the hammer heads of the first and second hammer heads, the first hammer head and the second hammer being provided on a side surface of a pattern end portion The first mask pattern and the second mask pattern are arranged alternately in the left-right direction and the opposing direction.

In the third exposure mask, the first and second hammer heads may be spaced apart from each other by a predetermined distance.
Desirably, it is approximately equal to a certain size of the second hammer head.

In the third exposure mask, the first and second hammer heads may be spaced apart from each other by a predetermined distance.
The second hammer head may be larger than a certain size.

[0018]

Embodiments of the present invention will be described below with reference to the drawings.

[First Embodiment] In a first embodiment of the present invention, for example, a method of correcting an exposure mask pattern for forming a gate wiring of a transistor crossing an element region will be described. This mask pattern correction method is
After selecting a mask pattern having a line width equal to or less than a specified value from the mask patterns protruding from the element region, a distance to a pattern adjacent to the mask pattern is calculated, and the mask pattern is corrected according to the distance. It is characterized by having been done.

FIG. 1 shows a flowchart of mask pattern correction according to the first embodiment. Hereinafter, a method of correcting a mask pattern according to the first embodiment will be described with reference to the flowchart shown in FIG.

FIG. 2 shows an example in which a plurality of mask patterns for forming a gate wiring are arranged crossing over an element region. As shown in FIG. 2, first, second, and third mask patterns 12a, 12b, 12
c are arranged in parallel, and a fourth mask pattern 12d is arranged perpendicular to the first, second, and third mask patterns 12a, 12b, and 12c.

First, as shown in FIG. 3, first, second and third mask patterns 12a and 12
b, 12c, for example, the fourth mask pattern 12
Portions protruding from the d-side element region 11 (hereinafter, referred to as protruding portions) 13a and 13b are extracted (ST1). Thereafter, as shown in FIG. 4, the line widths W1, W2 of the protruding portions 13a, 13b are calculated (ST2).

Next, it is determined whether or not the line widths W1 and W2 are smaller than a specified value a (a <W) (ST3). Here, for example, the first and second mask patterns 12a, 12a
b, the line width W1 of the protruding portion 13a is such that the line width W1 <the specified value a
In this case, the first and second mask patterns 12a and 12b need to be corrected. Further, for example, when the line width W2 of the protruding portion 13b of the third mask pattern 12c satisfies the relation of line width W2 ≧ specified value a, the third mask pattern 12c is used as a mask without performing correction processing (ST).
4). As described above, whether or not the mask pattern is corrected is determined based on the line widths W1 and W2. The method for obtaining the specified value a will be described later.

Next, as shown in FIG. 5, distances from each side of the protruding portion 13a of the first and second mask patterns 12a and 12b which need to be corrected to adjacent mask patterns (hereinafter, adjacent patterns). S is calculated (ST5).

Next, a correction rule for the distance S between the adjacent patterns is created (ST6). A detailed method of creating a correction rule will be described later.

Next, as shown in FIG. 6, necessary correction is performed on each side of the protruding portion 13a in accordance with the correction rule, and a correction pattern 14 is created (ST7).

Next, a method for obtaining the above-mentioned specified value a will be described. The specified value a defines a boundary of the line width for which the mask pattern correction process is required.

First, as shown in FIG. 7, the line width W of the arranged test patterns 15 and the adjacent test patterns 1
The distance S between the five is calculated. Next, a test pattern 1 for the distance S is obtained by an optical simulation or an experiment.
A shortening amount of 5 is required. FIG. 8 shows the result.

FIG. 8 shows the relationship between the distance S between adjacent test patterns 15 for various line widths W and the amount of shortening. In FIG. 8, line widths W = a, b, and c are a> a.
There is a relationship of b> c, and the shortening amount increases as the line width W decreases. When the distance S between the adjacent test patterns 15 is S ′, the amount of shortening becomes maximum. Hereinafter, the case where the amount of shortening is maximum is referred to as a worst case.

Next, the allowable value of the shortening is determined by design for the device to be applied. The allowable value of the shortening is determined by, for example, alignment accuracy at the time of exposure, dimensional variation, operation of a transistor, and the like.

Next, the minimum line width at which the worst case shortening amount becomes equal to or smaller than the allowable value is determined. As a result, as shown in FIG. 8, for example, the line width a is determined as the specified value a. Here, if the line width is larger than the specified value a, the shortening amount exceeds the allowable value, so that a mask pattern correction process is required. Therefore, the above ST
By the processes of 5 to ST7, a correction pattern is created according to the correction rule.

Next, a method of creating the above-described correction rule will be described. First, as shown in FIG. 9, the line width W of the arranged test patterns 15 and the distance S between the adjacent test patterns 15 are calculated. Next, a hammer head 16 having a size of, for example, h is provided on the test pattern 15. Here, the size h of the hammer head 16 indicates the length of a portion protruding from the test pattern 15.

Next, while the line width W of the test pattern 15 is fixed, the size h of the hammer head 16 is variously changed by optical simulation, experiment, or the like, and the amount of shortening with respect to the distance S between the adjacent test patterns 15 is determined. calculate. Here, the size of the hammer head 16 is changed, for example, by an integral multiple of the design grid, but is not limited to this. In the same manner as described above, the allowable value of the shortening is determined by design for the device to be applied, and the hammer head 16 is set so that the amount of shortening becomes equal to or less than the allowable value at all distances S with respect to the fixed line width W. The size h is changed. Note that the fixed line width W is set to a line width that is equal to or smaller than the specified value a.

FIG. 10 shows the distance S between adjacent test patterns 15 for various sizes h of the hammer head 16.
And the relationship between the amount and the amount of shortening. In FIG.
The size h = A, 2A, 3A of the hammer head 16 is 3
A>2A> A, and the hammer head 16
As the size h becomes smaller, the amount of shortening increases.

As a result, as shown in FIG. 11, the size h of the hammer head 16 at each distance S between the test patterns 15 at which the amount of shortening is equal to or less than the allowable value is obtained.
Thereby, as shown in FIG. 12, S <Sa or Sd ≦
In the case of S, h = A, Sa ≦ S <Sb or Sc ≦ S <Sd
In this case, a correction rule can be created such that h = 2A, and if Sb ≦ S <Sc, h = 3A. Here, the distance S between the divided test patterns 15 is, for example, an integral multiple of the minimum grid of the design, but is not limited thereto.

By acquiring data for various line widths W in the same manner as described above, a correction rule for a desired line width W can be created.

According to the first embodiment, after a mask pattern having a line width equal to or less than a specified value is selected from mask patterns protruding from an element region, a distance to a pattern adjacent to the mask pattern is calculated. The mask pattern is corrected according to the distance. Therefore, a desired mask pattern can be formed according to the surrounding environment. Therefore, the shortening phenomenon can be suppressed without increasing the chip area.

[Second Embodiment] In a second embodiment, a first mask pattern provided with a hammer head at a pattern end and a second mask pattern having a longer pattern end are formed in a horizontal direction. And an exposure mask alternately arranged in the facing direction. Hereinafter, the pattern of the exposure mask in the second embodiment will be described.

First, as shown in FIG. 13, consider a layout in which the gate wirings 21 are densely arranged in the left-right direction and the opposite direction. In a mask pattern for finishing such a layout, if a sufficient hammer head is attached to the mask pattern to avoid shortening, the hammer heads of adjacent mask patterns overlap. In addition, if the end portions of the mask pattern are extended to complete the layout according to the layout, the end portions of the mask pattern facing each other overlap.

In order to avoid the above problem, first, as shown in FIG. 14, in order to distinguish between adjacent mask patterns and opposite mask patterns, the first mask pattern 22a and the second mask pattern 22b are used. Divided into Next, the first mask pattern 22a is subjected to a process of providing a hammer head 23 at the end of the pattern,
Is subjected to a process of extending the pattern end.

According to the second embodiment, the first mask pattern 2 provided with the hammer head 23 at the pattern end is provided.
2a and a second mask pattern 22b having a longer pattern end are alternately arranged in the left-right direction and the opposing direction. Therefore, without increasing the chip area,
It is possible to prevent the hammer head of an adjacent mask pattern from overlapping with the end of the opposing mask pattern. Therefore, a mask pattern having a desired layout can be formed,
Shortening can be sufficiently suppressed.

Note that the second embodiment can be used in combination with the first embodiment. In this case, a mask pattern having a desired layout can be further formed, and shortening can be further suppressed.

Further, the first mask pattern 22a and the second
When the Levenson shifter arrangement conversion software is used as a method for dividing the pattern into the mask pattern 22b, the pattern can be easily distinguished.

[Third Embodiment] In a third embodiment, a first mask pattern provided with a plurality of hammer heads having a fixed size d and a fixed interval d, and the first mask pattern And a second mask pattern having a plurality of hammer heads provided at positions shifted by half a pitch from each other. Hereinafter, the pattern of the exposure mask in the third embodiment will be described.

First, as shown in FIG. 15, similar to the second embodiment, a layout in which the gate wirings 21 are densely arranged in the horizontal direction and the opposing direction as shown in FIG. In order to distinguish the mask patterns, the mask patterns are divided into a first mask pattern 24a and a second mask pattern 24b.

Next, a first hammer head 25 having a length d in the longitudinal direction of the first mask pattern 24a.
a is provided at an end of one side surface of the first mask pattern 24a. A second hammer head 25b having the same size as the first hammer head 25a is provided on one side surface of the first mask pattern 24a at a distance d from the first hammer head 25a. The third and fourth hammer heads 25 are provided at the same positions as the first and second hammer heads 25a and 25b.
c and 25d are provided on the other side surface of the first mask pattern 24a.

Similarly, the fifth hammer head 25e having the same size as the first hammer head 25a is
Is provided on one side surface inside by a distance d from the end of the mask pattern 24b. A sixth hammer head 25f having the same size as the fifth hammer head 25e is provided on one side of the second mask pattern 24b at a distance d from the fifth hammer head 25e. The seventh and eighth hammer heads 2 are provided at the same position as the fifth and sixth hammer heads 25e and 25f.
5g and 25h are provided on the other side surface of the second mask pattern 24b.

It is desirable that the distance between the hammer heads is substantially equal to the size of the hammer head, but it is sufficient if the distance is at least equal to the size of the hammer head.

According to the third embodiment, the first mask pattern 24a provided with a plurality of hammer heads having a fixed size d and a fixed interval d, and a hammer of the first mask pattern 24a A second mask pattern 24b having a plurality of hammer heads provided at a position shifted from the head by a half pitch is alternately arranged in the left-right direction and the opposing direction. Therefore, it is possible to prevent the hammer heads of the adjacent mask patterns from overlapping with the ends of the opposing mask patterns without increasing the chip area. Therefore, a mask pattern having a desired layout can be formed, and shortening can be sufficiently suppressed.

It is to be noted that the third embodiment can be used in combination with the first embodiment. In this case, a mask pattern having a desired layout can be further formed, and shortening can be further suppressed.

The first mask pattern 24a and the second
When the Levenson shifter arrangement conversion software is used as a method of dividing the pattern into the mask pattern 24b, the pattern can be easily distinguished.

The present invention can be variously modified and implemented without departing from the gist thereof.

[0053]

As described above, according to the present invention, it is possible to provide an exposure mask and a method of correcting the pattern thereof, which can suppress the shortening according to the environment without increasing the chip area.

[Brief description of the drawings]

FIG. 1 is a flowchart illustrating a method of correcting a mask pattern according to a first embodiment of the present invention.

FIG. 2 is a plan view showing an example in which a plurality of mask patterns are arranged on an element region.

FIG. 3 is an extraction of a protruding portion of a mask pattern (ST1).
FIG.

FIG. 4 is a plan view showing extraction (ST2, ST3) of a line width W of a protruding portion of a mask pattern.

FIG. 5 is a plan view showing calculation (ST5) of a distance S between a protruding portion of a mask pattern and an adjacent pattern.

FIG. 6 shows the creation of a mask pattern according to a correction rule (S
T6, ST7).

FIG. 7 is a plan view showing a method of calculating a prescribed value a.

FIG. 8 is a diagram showing the relationship between the distance S between adjacent test patterns and the amount of shortening for various line widths W.

FIG. 9 is a plan view in which a hammer head is provided on a test pattern.

FIG. 10 is a diagram showing the relationship between the distance S between adjacent test patterns and the amount of shortening for various sizes h of the hammer head.

FIG. 11 is a diagram showing a distance at which the amount of shortening is equal to or less than an allowable value.

FIG. 12 is a table showing a relationship between a distance S between adjacent patterns and a size of a hammer head.

FIG. 13 is a plan view showing a layout in which gate wirings are densely arranged.

FIG. 14 is a plan view showing a mask pattern according to a second embodiment of the present invention.

FIG. 15 is a plan view showing a mask pattern according to a third embodiment of the present invention.

FIG. 16 is a plan view showing a mask pattern according to the related art.

FIG. 17 is a plan view showing a mask pattern according to the related art.

[Explanation of symbols]

11: element region, 12a, 22a, 24a: first mask pattern, 12b, 22b, 24b: second mask pattern, 12c: third mask pattern, 12d: fourth mask pattern, 13a, 13b: protrusion Section 14: Correction pattern 15: Test pattern 16, 23, 25a, 25b, 25c, 25d, 25
e, 25f, 25g, 25h: hammer head; 21: gate wiring.

Continued on the front page (72) Inventor Koji Hashimoto 8th Shinsugita-cho, Isogo-ku, Yokohama-shi, Kanagawa Prefecture Inside the Toshiba Yokohama Office (72) Inventor Kei Keikawa 8th Shinsugita-cho, Isogo-ku, Yokohama-shi, Kanagawa Toshiba Yokohama Co., Ltd. Inside the business site (72) Inventor Ayako Nakano 8th Shinsugitacho, Isogo-ku, Yokohama-shi, Kanagawa Prefecture Inside the Toshiba Yokohama Office (72) Inventor Satoshi Usui 8th-8th Shinsugita-cho, Isogo-ku, Yokohama-shi, Kanagawa Prefecture Inside the Toshiba Yokohama Business Corporation F-term (reference) 2H095 BB01 BB02 BC09

Claims (8)

[Claims] 1. A method of correcting a mask pattern for forming a gate wiring of a transistor crossing an element region, comprising: extracting a plurality of first protrusions of the mask pattern projecting from the element region. Calculating the line width of the plurality of first protrusions; determining whether the line width of the plurality of first protrusions is smaller than a specified value; Extracting a second protruding portion having a line width smaller than the specified value from among the portions; calculating a distance from the second protruding portion to an adjacent mask pattern; Creating a correction rule for the distance of the object, and performing a necessary correction on the protrusion in accordance with the correction rule to create a correction pattern. How to correct the disk pattern. 2. The method according to claim 1, wherein each line width of the arranged test patterns is:
Extracting the distance between adjacent test patterns; deriving the relationship between the distance between adjacent test patterns and the amount of shortening for each of the line widths; determining the allowable value of the shortening; 2. The method according to claim 1, wherein the step of extracting the minimum line width at which the amount of shortening is equal to or less than the allowable value determines the minimum line width as a specified value. 3. A step of extracting a line width of the arranged test patterns and a distance between adjacent test patterns; a step of providing a hammer head having a size h in the test patterns; Fixing the width, varying the size h of the hammer head, calculating the amount of shortening with respect to the distance between the adjacent test patterns, and determining the allowable value of the shortening; Changing the size h of the hammer head so that the amount of shortening becomes equal to or less than an allowable value at all distances between the adjacent test patterns with respect to a line width; Deriving a relationship between the distance between the adjacent test patterns and the amount of shortening; and the amount of shortening. A step of calculating a size h of the hammer head for each distance between the adjacent test patterns that is smaller than or equal to the allowable value, thereby creating the correction rule. Method. 4. An exposure mask for forming a gate wiring of a transistor that intersects with an element region, the method comprising: extracting a plurality of first projecting portions of the mask pattern projecting from the element region; Calculating the line width of the plurality of first protrusions; determining whether the line width of the plurality of first protrusions is smaller than a specified value; Extracting a second protruding portion having a line width smaller than the specified value from within; calculating a distance from the second protruding portion to an adjacent mask pattern; and a distance between the adjacent mask patterns. And a step of creating a correction pattern by performing a necessary correction on the protruding portion according to the correction rule. For mask. 5. A semiconductor device comprising: a first mask pattern provided with a hammer head at an end of the pattern; and a second mask pattern having an elongated end of the pattern, wherein the first mask pattern and the second mask pattern are provided. Wherein the mask pattern is alternately arranged in the left-right direction and the opposing direction. 6. A first mask pattern in which a plurality of first hammer heads having a fixed size and a fixed interval are provided on a side surface of a pattern end, and an interval equal to a size equal to the first hammer head. A plurality of second hammer heads having a second mask pattern provided on a side surface of a pattern end, wherein the first hammer head and the second hammer head are shifted by a half pitch. An exposure mask that is provided, wherein the first mask pattern and the second mask pattern are alternately arranged in a left-right direction and a facing direction. 7. The exposure mask according to claim 6, wherein a fixed interval between the first and second hammer heads is substantially equal to a fixed size of the first and second hammer heads. 8. The exposure mask according to claim 6, wherein a certain distance between the first and second hammer heads is larger than a certain size of the first and second hammer heads.