JP2001356366A - Active matrix type display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To eliminate degradation in display quantity caused by difference in signal delay for each drain line due to difference in the locations of the cross points of data signal lines 7 and drain lines. SOLUTION: A capacitive line, which does not contribute to data transmission, is provided on a drain line to make the superimposed area with a data line to be made equal for each drain line. Thus, parasitic capacitance caused by the data line 7 and the drain line is made equal for each drain line, the difference in signal delay for each drain line is eliminated and the display quality is improved.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a structure of a drain line of an active matrix display device for selecting a drain line arranged for each column and supplying a signal.

[0002]

2. Description of the Related Art Display devices used at present are roughly classified into a passive matrix type and an active matrix type. Among them, the active matrix type display device is a type of display device in which a switching element is provided for each pixel, and a voltage corresponding to the image data of the pixel is applied to each pixel (or a current is applied) to perform display. It is.

A liquid crystal display (Liquid Crystal Display;
LCD) is a display device in which liquid crystal is sealed between opposing substrates, a voltage is applied to pixel electrodes formed for each pixel, and a display is performed by changing the transmittance of the liquid crystal. , Especially in monitor applications.

In addition, electroluminescence (Electr
o Luminescence (EL) display device is a display device that performs display by passing a current from a pixel electrode formed for each pixel to an EL element. Active matrix EL display devices have been actively studied for practical use. It is.

FIG. 4 is a circuit diagram showing an active matrix type LCD. In the display area 1, a plurality of drain lines 2 extending in the column direction and a plurality of gate lines 3 extending in the row direction are arranged, and a selection transistor 4 is arranged corresponding to each intersection of the drain line 2 and the gate line 3. Have been. The drain of the selection transistor 4 is connected to the drain line 2, the gate is connected to the gate line 3, and the source is connected to a pixel electrode formed for each pixel. Above the display area 1, a drain line selector 5 for selecting a predetermined drain line
And six data signal lines 7 connected to the drain line 2 via the drain line selection transistor 6. A gate line selector 8 for selecting a gate line is arranged beside the display area 1.

The gate line selector 8 sequentially selects a predetermined gate line 3 from the plurality of gate lines 3, applies a gate voltage, and turns on the selection transistor 4 connected to the gate line 3. The drain line selector 5 sequentially selects a predetermined drain line 2 from the plurality of drain lines 2 and sequentially turns on a predetermined drain line selection transistor 6. The drain line 2 in which the drain line selection transistor 6 is turned on is connected to the corresponding data signal line 7, and a data signal is input to the drain line 2. A data signal is applied to the pixel electrode of the pixel connected to the selected gate line 3 and the selected drain line 2 through the drain line 2 and the turned-on selection transistor 4, and the corresponding liquid crystal is driven to display. Is performed.

Conventionally, the drain line selector only selects one drain line 2 sequentially. However, as the number of pixels increases, the time during which one drain line becomes active is shortened, and there is a possibility that the response of the liquid crystal may not be in time. Therefore, in recent years, the number of data signal lines 7 has been increased, It is increasing that line 2 is active at the same time. FIG. 4 shows that the data signal line 7 is
A six-layer structure in which the number of B lines is six and the total of six drain lines 2 is active at the same time is illustrated. 6 shown in FIG.
Out of the six drain lines 2, the output of the drain line selector 5 common to the gate electrode of the drain line selection transistor 6 is applied to the six lines except for the one at the right end and turned on at the same time. Although omitted for simplification of the drawing, the rightmost drain line is also turned on simultaneously with five drain lines (not shown).

Although the description is omitted, there are also multilayer structures such as a 12-layer structure and a 24-layer structure in which the number of data signal lines 7 is further increased. In general, if a larger number of layers are used, a longer period of time during which one drain line 2 is active can be secured. Therefore, there is a demand for a larger number of layers when, for example, the number of pixels further increases.

FIG. 5 is an enlarged plan view of the vicinity of the data signal line 7 and the drain line selection transistor 6. Six data signal lines 7 extend in the horizontal direction, two for each of the RGB colors. The first drain line upper wiring 10 is connected to the data signal line 7R1 via the contact 11, and extends to the drain line selection transistor 6. The drain line selection transistor 6 has a gate electrode 6a and an active layer 6b. The gate electrode 6a is connected to the drain line selector 5 by a wiring (not shown). Active layer 6
The source b is connected to the first drain line upper wiring 10. The drain of the active layer 6b is connected to the first drain line lower wiring 12, and extends to the display region 1. The drain line upper wiring and the drain line lower wiring are collectively called a drain line.

The second upper drain line 13 is connected to the data signal line 7G1 via a contact 14 and extends to the drain line select transistor 6, to which the second lower drain line 15 is connected.

The third drain line upper wiring 16 is connected to the data signal line 7B1 via the contact 17, the fourth drain line upper wiring 19 is connected to the data signal line 7R2 via the contact 20, and the fifth drain line upper wiring. Reference numeral 22 denotes a data signal line 7G2 via a contact 23, and a sixth drain line upper wiring 25 denotes a data signal line 7G via a contact 26.
B2, respectively, and so on.

At this time, the drain line upper wirings 10, 13,.
16, 19, 22 and 25 have the same resistance,
They are formed of the same material, the same line width, and the same length. This is because if the resistance of the upper wiring is different, the attenuation rate of the data signal differs for each drain line, and a data signal having a different attenuation rate is applied to each drain line 2, thereby preventing the display quality from being deteriorated as a result. That's why.

[0013]

However, the above-described multilayer structure has the following problems.

The first drain line upper wiring 10 is connected to R 1 located at the uppermost stage of the data signal lines 7. On the other hand, the sixth drain line upper wiring 25 is connected to B2 of the data signal line 7 located at the lower stage again. Then, the first drain line upper wiring 10 crosses the five data signal lines 7 to which the first drain line upper wiring 10 is not connected.
The sixth drain line upper wiring 25 does not cross the data signal line 7 to which it is not connected.

At the intersection of the wirings, a parasitic capacitance is generated, and when the parasitic capacitance is generated, the following when changing the voltage applied to the wiring is delayed. In general, the larger the parasitic capacitance, the slower the response to a voltage change.

Therefore, the larger the number of data signal lines 7 intersected, the larger the parasitic capacitance is generated and the response speed becomes slower. Therefore, the first drain line upper wiring 10 and the sixth drain line upper wiring 25 In this case, since the response is different, there is a problem that the display quality is deteriorated.

This becomes more noticeable when the structure has 12 layers, 24 layers, and a multilayer structure.

An object of the present invention is to provide an active matrix type display device having a high display quality without a difference in signal delay between drain lines even when the data signal line 7 has a multilayer structure.

[0019]

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and has a display area in which a plurality of pixel electrodes are arranged, and a plurality of display areas arranged in a peripheral portion of the display area. A data signal line, a plurality of drain lines respectively connected to any one of the plurality of data signal lines, and extending to the display region; and a plurality of drain lines intersecting the plurality of drain lines and extending to the display region. The plurality of drain lines extend so as to intersect at least one of the data signal lines other than the data signal lines to which the drain lines are connected. It is a matrix type display device.

Further, each of the drain lines has a portion that intersects with every data signal line other than the data signal line to which the drain line is connected.

Further, the area of a portion where each of the drain lines intersects with the data signal line is substantially equal in all the drain lines.

Further, a drain line selection for selecting the plurality of drain lines is provided at a predetermined position of a portion extending from the position connected to the corresponding data signal line of the plurality of drain lines toward the display region. The distance from a position where the switching element is interposed and the drain line selection switching element is connected to the corresponding data signal line of the plurality of drain lines is substantially equal to each other between the plurality of drain lines.

Further, a display area in which a plurality of pixel electrodes are arranged, a plurality of data signal lines arranged in parallel with each other around the display area, and one of the data signal lines.
A plurality of drain lines respectively connected to the book and extending to the display region; a plurality of gate lines intersecting with the drain line and extending to the display region; corresponding to intersections of the drain line and the gate line, respectively. And a switching element connected to the drain line, the gate to the gate line, and the source to the corresponding pixel electrode, respectively. At least part of
A portion extending from the position connected to the corresponding data signal line toward the display region, and a portion extending away from the display region, and each portion other than the data signal line to which the drain line is connected. The sum of the areas where the data signal lines intersect and where the drain lines and the data signal lines overlap at each intersection is equal for each of the plurality of drain lines.

Further, a portion extending from the position where the plurality of drain lines are connected to the corresponding data signal line toward the display region and a portion extending away from the display region have substantially the same thickness. The number of intersections between the drain lines and the data signal lines is equal for each of the plurality of drain lines.

Further, a drain signal selection for selecting the plurality of drain lines is provided at a predetermined position of a portion extending from the position connected to the corresponding data signal line of the plurality of drain lines toward the display area. The distance from the position where the switching element is interposed and connected to the corresponding data signal line of the plurality of drain lines to the drain signal selection switching element is substantially equal between the plurality of drain lines.

Further, a portion extending toward the display region from a position where the plurality of drain lines are connected to the corresponding data signal line and a portion extending away from the display region extend in substantially the same direction. ing.

[0027]

DESCRIPTION OF THE PREFERRED EMBODIMENTS As a first embodiment of the present invention,
An example in which the present invention is applied to an LCD will be described below. The circuit diagram of the present embodiment is completely the same as the conventional one shown in FIG.
Description is omitted.

FIG. 1 is an enlarged plan view of the vicinity of the data signal line 7 and the drain line selection transistor 6 of the LCD according to the present embodiment.

The data signal lines 7 are two for each of the RGB colors 6
The book extends horizontally. The first drain line upper wiring 50 is connected to the data signal line 7R1 via the contact 51, and extends to the drain line selection transistor 6. The drain line selection transistor 6 has a gate electrode 6
a and the active layer 6b. The gate electrode 6a is connected to the drain line selector 5 by a wiring (not shown). The source of the active layer 6b is connected to the first drain line upper wiring 50. The drain of the active layer 6b is connected to the first drain line lower wiring 52, and the display region 1
Extending to

The second upper drain line 53 is connected to the data signal line 7G1 via the contact 54, extends to the drain line selection transistor 6, and the second lower drain line 55 is connected thereto.

The third drain line upper wiring 56 is connected to the data signal line 7B1 via the contact 57, the fourth drain line upper wiring 59 is connected to the data signal line 7R2 via the contact 60, and the fifth drain line upper wiring. 62 is connected to the data signal line 7G2 via the contact 63, and the sixth drain line upper wiring 65 is connected to the data signal line 7G via the contact 66.
B2, respectively, and so on.

At this time, the drain line upper wirings 50, 53,
56, 59, 62 and 65 are used to make the resistances equal to each other,
They are formed of the same material, the same line width, and the same length.

The present embodiment differs from the prior art in that the second to sixth drain line upper wirings 53, 56, 59, 62, 6
5 is that capacitor lines 68, 69, 70, 71, 72 are connected. Capacity lines 68, 69, 70, 71, 72
Are drain line upper wirings 53, 56, 59, 62, 65
Although there is no boundary line, the side farther from the display area than the contact with the data signal line is referred to as a capacitance line here for convenience of explanation. The first drain line upper wiring 50 is connected to the uppermost data signal line 7R1, and the data signal line 7 does not exist farther from the display area 1 than the uppermost data signal line 7R1, so that no capacitance line is formed.

The length of the capacitance line differs depending on which data signal line the drain line is connected to, and all the capacitance lines extend from the contact with the data signal line in a direction away from the display region, The drain line crosses the unconnected data signal line and extends to a side farther from the display area than the uppermost data signal line 7R1. In the present embodiment, the width of the capacitance line is the same as the drain line upper wiring.

As a result, the total number of times that the upper wiring of the drain line and the capacitance line intersect with the data signal line 7 is equal to five for all the drain lines. The parasitic capacitance formed by the wirings is determined by the area where the wirings overlap, but in the present embodiment, since the capacitance line and the drain line upper wiring have the same line width, the parasitic capacitance value is simply different from that of the data signal line. Determined by the number of intersections. Therefore, the sum of the capacitance formed by the data line 7 and the upper line of the drain line and the capacitance line is equal for all the drain lines, and the response is different for each drain line. Will be resolved.

Here, the arrangement of the capacitance lines will be described.
As described above, the resistance from the contact between the drain line and the data signal line to the drain line selection transistor 6 needs to be equal. Therefore, it is better to dispose the capacitance line so as to extend on the opposite side to the drain line upper wiring as in the present embodiment, rather than branching from somewhere in the drain line upper wiring. In addition, the parasitic capacitance can be adjusted by adjusting the line width of the drain line upper wiring only at the intersection of the drain line upper wiring and the data signal line. This is not optimal because the resistance of the internal wiring changes. In other words, the capacitance line does not contribute to the transmission of the data signal, but plays only the role of adjusting the capacitance.

The capacitance line is preferably extended in the same direction as the drain line upper wiring. This is because if the intersection angle between the drain line upper wiring and the capacitance line is different from the data signal line 7, the overlapping area of the intersection is different even if the line width is equal, and the parasitic capacitance cannot be made uniform.

In the present embodiment, the distance from the contact between the upper wiring of the drain line and the data signal line to the drain line selection transistor is the same for all drain lines. This is a measure for equalizing the electrical resistance of the drain line upper wiring for each drain line as described above. On the other hand, conventionally, as a method for equalizing the electrical resistance of the drain line upper wiring, changing the thickness of the drain line upper wiring has been proposed.

FIG. 2 is a plan view of an active matrix display device in which the thickness of the drain line upper wiring is changed. The drain line upper wiring 81 connected to the uppermost data signal line far from the display area is formed thickest, and the drain line upper wiring 86 connected to the lower lower data signal line is formed thinnest. Since the resistivity of the wiring decreases as the thickness of the wiring increases, optimizing the length and the thickness makes it possible to equalize the resistances of all the drain line upper wirings.

If the resistances are made uniform by this method, the length of the upper wiring of the drain line can be shortened, so that there is an advantage that the wiring area can be slightly reduced. The wiring is thick at the intersection with the data signal line to which it is not connected, and the area overlapping with the data signal line is large. Conversely, the drain line upper wiring 83 intersecting with one data signal line is thin and has only one intersection. Therefore, the difference in the parasitic capacitance between the drain line upper wiring and the data signal line is further increased.

In this case as well, the capacitance lines can be arranged and the capacitances can be made uniform according to the same idea, but the arrangement of the capacitance lines requires some contrivance. FIG. 3 is a plan view of an active matrix display device according to a second embodiment of the present invention. Drain line upper wiring 81, 82, 83, 84, 8
Lines 5 and 86 have different line widths according to their lengths as in FIG. Capacitance lines 91, 92, 93, and 9495 are formed on the side far from the display area 1. The widths of these capacitance lines are different from each other, and are set so that the sum of the areas where the capacitance lines and the corresponding drain line upper wiring overlap each other at the intersection with the data signal line 7 is equal to each other.

As is clear from the first embodiment and the second embodiment, what is intended by the present invention is that the area where the upper wiring of the drain line overlaps the data signal line and the capacity line is the data signal line It suffices that the sum of the line and the overlapping area be equal for each drain line. However, comparing the first embodiment and the second embodiment, the first embodiment has a smaller parasitic capacitance between the upper wiring of the drain line and the data signal line, and has better responsiveness of the entire drain line. , The first embodiment is considered more suitable.

Although the above embodiments have been described by exemplifying an LCD, the present invention is not limited to this, and can be applied to any active matrix display device such as an EL display device and an LED display device.

[0044]

As described in detail above, according to the present invention, the drain line has a portion which intersects at least once with the data signal line other than the data signal line to which the drain line is connected. The difference in capacitance between the drain lines is small, and the difference in response time between the drain lines is small. Therefore, even when the data signal line 7 has a multilayer structure, an active matrix display device with a small display signal difference between drain lines and high display quality can be provided.

Further, since all the drain lines have portions that cross all the data signal lines other than the data signal lines to which the drain lines are connected, the difference in capacitance between the drain lines is further reduced, and the display quality is further reduced. Active matrix display device having a high density.

Further, since the area of the portion where each of the drain lines intersects with the data signal line is substantially equal in all the drain lines, the difference in capacitance between the drain lines is further reduced, and the active matrix type display with higher display quality It can be a device.

Further, a drain line selection switching element for selecting a plurality of drain lines is provided at a predetermined position of a portion extending from the position connected to the corresponding data signal line of the plurality of drain lines toward the display area. Since the distance from the intervening and connected position of the plurality of drain lines to the corresponding data signal line to the drain line selection switching element is substantially equal between the plurality of drain lines, the parasitic capacitance between the drain line and the data signal line And the resistance between the drain lines can be made uniform.

At least a portion of the drain line has a portion extending from the position connected to the corresponding data signal line toward the display region, and a portion extending away from the display region. , And the overlapping area of the drain line and the data signal line at this intersection is equal for each drain line, so that the response time of each drain line is equal, and the data signal line 7 has a multilayer structure. However, there is no difference in signal delay for each drain line, and an active matrix display device with high display quality can be obtained.

In particular, a portion extending from the position where the plurality of drain lines are connected to the corresponding data signal line toward the display region and a portion extending away from the display region have substantially the same thickness. Since the number of intersections at these portions is equal for each of the plurality of drain lines, the parasitic capacitance of each of the drain lines can be made uniform, the increase in capacitance can be minimized, and the signal delay is small. An active matrix display device with high display quality can be provided.

Further, at a predetermined position of a portion extending from the position connected to the corresponding data signal line of the plurality of drain lines toward the display area, a drain signal selection for selecting the plurality of drain lines is provided. Since the switching element is interposed and the distance from the position where the plurality of drain lines are connected to the corresponding data signal line to the drain signal selection switching element is substantially equal to each other between the plurality of drain lines, the distance between the drain lines is An active matrix display device with equal resistance and high display quality can be obtained.

[Brief description of the drawings]

FIG. 1 is a plan view showing an active matrix display device according to a first embodiment of the present invention.

FIG. 2 is a plan view of a conventional active matrix display device.

FIG. 3 is a plan view showing an active matrix display device according to a second embodiment of the present invention.

FIG. 4 is a circuit diagram illustrating an active matrix display device.

FIG. 5 is a plan view of a conventional active matrix display device.

[Explanation of symbols]

2 Drain line 3 Gate line 6 Drain line selection transistor 7 Data signal line 50, 53, 56, 59, 62, 65 Drain line upper wiring 68, 69, 70, 71, 72 Capacity line 91, 92, 93, 94, 95 Capacity line

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) G09G 3/36 H04N 5/66 102A H04N 5/66 102 G02F 1/136 500 F term (Reference) 2H092 GA59 GA61 JA24 JA42 JA44 JB13 JB32. FB12 FB14 FB15

Claims (8)

[Claims] A display region in which a plurality of pixel electrodes are arranged, a plurality of data signal lines arranged in a peripheral portion of the display region, and one of the plurality of data signal lines, respectively; In an active matrix display device including a plurality of drain lines extending to the display region, and a plurality of gate lines intersecting with the plurality of drain lines and extending to the display region, the plurality of drain lines are ,
An active matrix display device, wherein the drain line extends so as to intersect at least one of the plurality of data signal lines other than the connected data signal line. 2. The active matrix display according to claim 1, wherein all of the drain lines have a portion that intersects with all of the data signal lines other than the data signal lines to which the drain lines are connected. apparatus. 3. The active matrix display device according to claim 2, wherein an area of a portion where each of the drain lines intersects with the data signal line is substantially equal in all the drain lines. 4. A drain line selection for selecting the plurality of drain lines at a predetermined position of a portion extending from a position connected to a corresponding data signal line of the plurality of drain lines toward the display area. The distance between a position where a switching element is interposed and a position where the plurality of drain lines are connected to a corresponding data signal line and the drain line selection switching element is substantially equal to each other between the plurality of drain lines. Item 7. An active matrix display device according to item 3. 5. A display area in which a plurality of pixel electrodes are arranged, a plurality of data signal lines arranged in parallel with each other in a peripheral portion of the display area, and each of the plurality of data signal lines is connected to one of the data signal lines. An active matrix display device having a plurality of drain lines extending to a display region, and a plurality of gate lines intersecting the drain lines and extending to the display region, at least a part of the plurality of drain lines Has a portion extending toward the display region from a position connected to a corresponding data signal line, and a portion extending away from the display region, and a data signal having a drain line connected at least in one portion. The sum of the areas that intersect with the data signal lines other than the lines and where the drain line and the data signal line overlap at each intersection is substantially equal for each of the plurality of drain lines. An active matrix display device characterized in that: 6. A portion extending toward the display region from a position where the plurality of drain lines are connected to a corresponding data signal line, and a portion extending away from the display region have substantially the same thickness. The active matrix display device according to claim 5, wherein the number of intersections of the drain lines and the data signal lines is equal for each of the plurality of drain lines. 7. A drain line selection for selecting the plurality of drain lines at a predetermined position of a portion extending from the position connected to the corresponding data signal line of the plurality of drain lines toward the display region. The distance between a position where a switching element is interposed and a position where the plurality of drain lines are connected to a corresponding data signal line and the drain line selection switching element is substantially equal to each other between the plurality of drain lines. Item 7. An active matrix display device according to item 6. 8. A portion extending toward the display region from a position of the plurality of drain lines connected to a corresponding data signal line, and a portion extending away from the display region extends in substantially the same direction. The active matrix display device according to claim 5, wherein: