JP2001352332A - Atm main signal phase adjustment circuit and memory capacity reduction system used for it - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an ATM main signal phase adjustment circuit which has a small circuit scale and low power consumption. SOLUTION: A memory section 11 of a buffer section 1 temporarily stores a received main signal by two cells, a retiming section 12 outputs only with retiming not through the memory section 11, and a select section 13 selects a path through which the received main signal passes through the memory section 11 or a path through which the received main signal passes through the retiming section 12. A write address generating section 2 generates a write address signal of the memory section 11, and a read address generating section 3 generates a read address signal for the memory section 11 and generates a selection instruction signal to the select section 13. A control signal generating section 4 generates a write frame pulse signal, a read frame pulse signal, an output frame pulse signal and an address switching signal on the basis of a received frame pulse signal and an externally-set phase setting value set externally.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an ATM main signal phase adjusting circuit and a memory capacity reduction method used for the same, and more particularly to an ATM (Asynchronous Transfer) circuit.
The present invention relates to a reduction in memory capacity used in a main signal phase adjustment circuit used in a digital transmission device of a mode (Asynchronous transfer mode).

[0002]

2. Description of the Related Art Conventionally, a main signal phase adjusting circuit used in an ATM digital transmission apparatus has a memory for three cells, stores a periodic cell located at the head of a frame in a memory dedicated to the periodic cell, Are stored in the effective cell memory area for two cells, and each cell is delayed.

[0003] JP-A-06-046102 discloses that A
RS (Request to Send) -C by TM method
When performing D (Carrier Detect) transmission,
There is disclosed a technique aimed at eliminating the error of the RS-CD delay time and matching the phases of the CD and the RS even when the cell reception interval is not constant.

In this technique, the state of a carrier is detected from a received cell and held in a carrier register, the time from a transmission request to a transmission permission is counted by a timer, and the received cell is stored in a cell reception memory. At the same time, the stored cell number is counted by a cell number counter.

[0005] Then, by referring to the state of the carrier output from the carrier register, the time from the timer, and the number of cells from the cell number counter, the state of the carrier and the phase of the received data are adjusted. The timing for parallel / serial conversion of the received data is created.

[0006]

The above-mentioned conventional main signal phase adjustment circuit requires a memory area of three cells as a memory area for delaying the main signal, so that the circuit scale and power consumption are large. is there.

Accordingly, an object of the present invention is to provide an ATM main signal phase adjustment circuit capable of solving the above-mentioned problems, reducing the circuit scale and reducing power consumption, and a memory capacity reduction method used therefor. Is to do.

[0008]

An ATM main signal phase adjusting circuit according to the present invention comprises an ATM (Asynchronous T).
an ATM main signal phase adjusting circuit for use in a digital transmission device of the transfer mode.
Control means for controlling the periodic cell located at the head of the M frame and other valid cells by controlling the address at the time of reading and writing of the memory so as to adjust the phase of the main signal only in the memory area of two cells. Have.

The method for reducing the memory capacity of the ATM main signal phase adjusting circuit according to the present invention is based on an ATM (Asynchronous).
s Transfer Mode) is a memory capacity reduction method of an ATM main signal phase adjustment circuit used in a digital transmission device, wherein a periodic cell located at the head of the ATM frame and other valid cells are read and written in a memory. And the phase of the main signal is adjusted only in the memory area of two cells.

That is, the ATM main signal phase adjusting circuit of the present invention does not divide the memory area into the periodic cells and the other valid cells as in the prior art. The main signal phase adjustment circuit is realized by controlling the address of the other valid cells at the time of reading and writing the memory, thereby realizing the phase adjustment of the main signal only in the memory area of two cells. Can be realized.

More specifically, the ATM main signal phase adjusting circuit according to the present invention, when the rising edge of the write frame pulse is in the odd cell of the memory read cell, changes the periodic cell to the first cell area of the memory or the two cells. When the rising edge of the write frame pulse is in the even cell of the memory read cell, the periodic cell is changed to the first cell area and the second cell area of the memory. The operation is performed so as to be alternately held. This makes it possible to adjust the phase of the main signal only in the memory area for two cells.

[0012]

Next, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing a configuration of an ATM main signal phase adjusting circuit according to one embodiment of the present invention. In FIG. 1, an ATM main signal phase adjusting circuit according to one embodiment of the present invention includes a buffer unit 1, a write address generation unit 2, a read address generation unit 3, and a control signal generation unit 4.

The buffer unit 1 comprises a memory unit 11, a retiming unit 12, and a select (SEL) unit 13. The memory unit 11 has an input main signal 101 for two cells.
The retiming unit 12 outputs the input main signal 101 only by retiming without passing through the memory unit 11, and the select unit 13 outputs the input main signal 101 to the memory unit. 11 and a path where the input main signal 101 outputs only at retiming.

The write address generation unit 2 generates a write address (W_ADR) signal 107 for the memory unit 11, and the read address generation unit 3 generates a read address (R_ADR) signal 108 for the memory unit 11 and an input main signal 101.
Generates a switching instruction signal 106 for switching between a path passing through the memory unit 11 and a path where the input main signal 101 outputs only at retiming.

The control signal generator 4 includes an input frame pulse (FP) 103 and an externally set phase set value 105.
A write frame pulse (W_FP) for controlling the write address generation unit 2 and the read address generation unit 3 based on
A signal 110, a lead frame pulse (R_FP) signal 111, an output frame pulse (FP) signal 104, and an address switching (ADR_SEL) signal 113 are generated.

FIG. 2 is a diagram showing a cell format for explaining the operation of one embodiment of the present invention. In FIG. 2, in one embodiment of the present invention, ATM (Asynchrono) is used.
usTransfer Mode: Asynchronous transfer mode)
Since the cell format of 54 bytes is classified into 6 bytes × 9 areas, the operation clock of the memory unit 11 becomes one cell with nine clocks.

That is, the first to sixth bytes of the cell format are 1 to 48 bits, and 7 to 12 bits.
Byte 49-96 bits, Bytes 13-18 are 9
7 to 144 bits, the 19th to 24th bytes are 145 to 19
2 bits, the 25th to 30th bytes are 193 to 240 bits, and the 31st to 36th bytes are 241 to 288 bits, 37
The 42nd byte is composed of 289 to 336 bits, the 43rd to 48th byte is composed of 337 to 384 bits, and the 49th to 54th byte is composed of 385 to 432 bits.

FIG. 3 is a diagram showing a memory area for explaining the operation of one embodiment of the present invention. FIG. 3 shows a breakdown of addresses in a memory area for two cells according to one embodiment of the present invention.

The dual-port RAM for two cells mounted on the buffer unit 1 can store one cell with nine addresses. As shown in FIG.
0 'to' 08 '(' 00 ',' 01 ',' 02 ',' 0
3 ',' 04 ',' 05 ',' 06 ',' 07 ',' 0
8 ') and the area of the first cell and' 09 'to' 11 '(' 0 ').
9 ',' 0A ',' 0B ',' 0C ',' 0D ',' 0
E ',' 0F ',' 10 ',' 11 ') and the two cells are divided into two and two cells are stored.

Memory addresses '00' and '09' have cell format bits 1 to 48, memory addresses '01' and '0A' have cell format bits 49 to 96, and memory address '02'. , '0
B 'has 97-144 cell format bits, memory addresses'03' and '0C' have 145-192 cell format bits, and memory addresses' 04 'and' 0D 'have cell format bits. 1
93 to 240 bits respectively correspond.

Memory addresses '05' and '0E' have cell format bits 241 to 288 bits, memory addresses '06' and '0F' have cell format bits 289 to 336 bits, and memory address '0'.
7 'and' 10 'are cell format bits 337 to
384 bits correspond to memory addresses '08' and '11', and 385 to 432 bits of cell format bits respectively.

FIG. 4 is a timing chart showing a phase comparison between the read frame pulse signal 111 and the write frame pulse signal 110 in one embodiment of the present invention. FIGS. 5 and 6 are memory access timings in one embodiment of the present invention. FIG. Here, FIG. 5 shows the timing when the rise of the write frame pulse signal 110 is at an odd cell of the memory read cells,
FIG. 6 shows timing when the rise of the write frame pulse signal 110 is at the even-numbered memory read cell. The operation of the ATM main signal phase adjusting circuit according to one embodiment of the present invention will be described with reference to FIGS.

The order in which the two areas of the memory area are read and written differs depending on the phase relationship between the read frame pulse signal 111 and the write frame pulse signal 110, so two types of address generation procedures are required.

Hereinafter, a method of selecting an address generation procedure based on the phase relationship between the read frame pulse signal 111 and the write frame pulse signal 110 will be described with reference to FIG. The control signal generation unit 4 differentiates the rising edge of the write frame pulse signal 110 and generates a write frame pulse differential pulse having a width of 1 clock by the operation clock of the memory unit 11. In addition, from the rising of the read frame pulse signal 111, “H”,
An odd / even cell determination pulse that repeats “L” is generated.

The above-mentioned write frame pulse differential pulse is applied to the odd-numbered cell (1, 3, 5,... Cell) or the even-numbered cell (2, 4, 6,... Cell) of the memory read cell. The position is determined by performing an AND operation with the odd / even cell determination pulse. The control signal generator 4 holds the result and outputs it to the read address generator 3 and the write address generator 2 as the address switching signal 113 to select two types of address generation procedures.

Next, an address generation procedure in the case where the write frame pulse differential pulse is in the odd cell of the memory read cell will be described with reference to FIG. The read address generation unit 3 sets the read address signal 108 from '00' to '1'
When the rising edge of the write frame pulse signal 110 is detected by repeatedly generating “1” (the address of the area of the first and second cells) and counting up to “11”, “09” is counted.
To '11' (address of the area of the second cell) are repeatedly generated.

The write address generator 2 starts writing the write address signal 1 from the rising edge of the write frame pulse signal 110.
After generating '00' to '11' (address of the area of the first cell and the area of the second cell) for one cycle as 07, '09' to '11' are generated.
'11' (the address of the area of the second cell) is repeatedly generated. However, when the rising edge of the lead frame pulse signal 111 is detected, after counting up to '11', '00'
~ '11 '(address of the first cell and second cell area)
Is repeatedly generated.

That is, when the write frame pulse differential pulse is present in the odd cell of the memory read cell, the address generation procedure is to set the periodic cell to either the first cell area or the second cell area of the memory unit 11. Operate to always hold.

Next, the address generation procedure when the write frame pulse differential pulse is in the even-numbered memory read cell will be described with reference to FIG. When the read cycle signal 112 is "H", the read address generator 3 generates "09" to "11" (address of the area of the second cell) as the read address signal 108 at the rise of the read frame pulse signal 111. , '00'-'1
1 '(the address of the area of the first and second cells) is repeatedly generated. However, the light frame pulse signal 110
When the rising edge is detected, after counting to '08',
'09' to '11' (address of the area of the second cell) are repeatedly generated.

When the read cycle signal 112 is "L", the read address generator 108 sets "00" to "11" (first cell and second cell) as the read address signal 108 at the rise of the read frame pulse signal 111. Are repeatedly generated. However, when the rising edge of the write frame pulse signal 110 is detected, after counting to '11', '00' to '08' (address of the area of the first cell) are repeatedly generated.

In the write address generator 2, when the write cycle signal 109 is "H", the write frame pulse signal 1
At the rise of 10, the write address signal 107 becomes '0'.
After generating 0 'to' 11 '(address of the first cell and the area of the second cell) for one cycle,' 09 'to' 11 '(address of the area of the second cell) are repeatedly generated. However, when the rising of the lead frame pulse signal 111 is detected,
After counting to '11', '00' to '11' (1
The address of the cell and the area of the second cell) are repeatedly generated.

When the write cycle signal 109 is "L", the write address generation unit 2 sets the write address signal 107 at the rising edge of the write frame pulse signal 110 as "09" to "11" (address of the second cell area). ), '00' to '08' (address of the area of the first cell) are repeatedly generated. However, when the rising of the lead frame pulse signal 111 is detected, after counting to '08', '09' to '11' (address of the area of the second cell) are generated, and thereafter, '00' to '11'. (The addresses of the areas of the first cell and the second cell) are repeatedly generated.

That is, in the case where the write frame pulse differential pulse is present in the even-numbered memory read cell, the address generation procedure is such that the periodic cell is alternately switched between the first cell area and the second cell area of the memory unit 11. Operate to hold.

By the above-described address control, the phase adjustment for one frame including the periodic cell and the effective cell can be performed with the memory capacity for two cells. When the read address signal 108 matches the write address signal 107 and when the rising edges of the read frame pulse signal 111 and the write frame pulse signal 110 match,
The switching instruction signal 106 from the read address generation unit 3 is input to the buffer unit 1, the output of the memory unit 11 is stopped, and the input main signal 101 passes through the buffer unit 1 only at retiming without passing through the memory unit 11. Retiming unit 1
8 is switched.

As described above, even when the phase adjustment near one frame is to be performed, the memory area for delaying the main signal data corresponding to the phase adjustment required in the circuit is limited to only two cells. A main signal phase adjustment circuit having a small circuit size and low power consumption can be provided.

[0036]

As described above, according to the present invention, A
In an ATM main signal phase adjusting circuit used in a digital transmission system of a TM, a periodic cell located at the beginning of an ATM frame and other valid cells are controlled by an address at the time of reading and writing of the memory, and a memory for two cells is controlled. By adjusting the phase of the main signal only in the region, the circuit scale can be reduced, and the power consumption can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an ATM main signal phase adjusting circuit according to one embodiment of the present invention.

FIG. 2 is a diagram showing a cell format for explaining the operation of one embodiment of the present invention.

FIG. 3 is a diagram showing a memory area for explaining the operation of one embodiment of the present invention.

FIG. 4 is a timing chart showing a phase comparison between a read frame pulse signal and a write frame pulse signal in one embodiment of the present invention.

FIG. 5 is a timing chart showing memory access timing according to one embodiment of the present invention.

FIG. 6 is a timing chart showing memory access timing according to one embodiment of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Buffer part 2 Write address generation part 3 Read address generation part 4 Control signal generation part 11 Memory part 12 Retiming part 13 Select part 101 Input main signal 102 Output main signal 103 Input FP signal 104 Output FP signal 105 Phase setting value input 106 Switching instruction signal 107 Write address signal 108 Read address signal 109 Write cycle signal 110 Write frame pulse signal 111 Read frame pulse signal 112 Read cycle signal 113 Address switching signal

Claims (8)

[Claims] 1. An ATM (Asynchronous Tr)
An ATM main signal phase adjusting circuit used in a digital transmission device of an ATM transfer mode.
Control means for controlling the address of the periodic cell located at the head of the frame and other valid cells at the time of reading and writing of the memory so as to adjust the phase of the main signal only in the memory area of two cells. AT characterized by the following
M main signal phase adjustment circuit. 2. The control unit according to claim 1, wherein a rising edge of a write frame pulse used for writing the periodic cell and the valid cell to the memory is in an odd cell or an even cell of a read cell from the memory. 2. The ATM main signal phase adjusting circuit according to claim 1, further comprising means for judging the address, and controlling the address at the time of reading and writing according to the judgment result. 3. The control unit always holds the periodic cell in one of the two memory areas when it is determined that the rising of the write frame pulse is at the odd cell of the read cell from the memory. 3. The ATM main signal phase adjusting circuit according to claim 2, wherein: 4. When the rising of the write frame pulse is determined to be the even-numbered read cell from the memory, the control means alternately holds the periodic cells in the memory area of the two cells. The ATM main signal phase adjusting circuit according to claim 2 or 3, wherein: 5. An ATM (Asynchronous Tr)
A method for reducing the memory capacity of an ATM main signal phase adjustment circuit used in a digital transmission device in an transfer mode, wherein a periodic cell located at the head of the ATM frame and other valid cells are read and written at the time of reading and writing of the memory. A memory capacity reduction method, wherein an address is controlled to adjust a phase of a main signal only in a memory area for two cells. 6. It is determined whether a rising edge of a write frame pulse used for writing the periodic cell and the valid cell to the memory is at an odd cell or an even cell of a read cell from the memory. 6. The memory capacity reduction method according to claim 5, wherein the address at the time of said read and write is controlled according to the determination result. 7. When the rise of the write frame pulse is determined to be at an odd cell of a read cell from the memory, the periodic cell is always held in one of the two memory areas. Claim 6
Memory capacity reduction method described. 8. When the rising edge of the write frame pulse is determined to be at the even cell of the read cells from the memory, the periodic cells are alternately held in the memory area of the two cells. The memory capacity reduction method according to claim 6 or 7, wherein: