JP2001352046A - Semiconductor device and its manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress GIDL of an information transfer transistor of a memory cell, while maintaining a current drive capability of a transistor of a peripheral circuit, as is. SOLUTION: A gate after oxide film of a MOS transistor in the memory cell is made thicker than a gate after oxide film of a MOS transistor in the peripheral circuit. The gate after oxide film of the MOS transistor, requiring a high withstand voltage in the peripheral circuit, is made thicker than that of the MOS transistor not needing the high breakdown voltage.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to post-gate oxidation of transistors used in semiconductor devices.

[0002]

2. Description of the Related Art A device structure of a conventional dynamic random access memory (hereinafter, referred to as DRAM) will be described with reference to the drawings. FIG. 1 shows a conventional DRAM.
1 shows a cross-sectional structure. In the memory cell section, a trench capacitor 1 and a MOS transistor 2 for information transfer are formed in a p-type silicon substrate 8. Trench capacitor 1
Comprises a storage electrode 3, a capacitor insulating film 4, and a plate electrode 5. Storage electrode 3 is electrically connected to one of source / drain regions 6 of MOS transistor 2. The other of the source / drain regions 6 is connected to a bit line 7. In the peripheral circuit section, the p-type silicon substrate 8
A MOS transistor (N-type) 9 is formed. Here, attention is focused on the MOS transistors 2 and 9 in the memory cell section and the peripheral circuit section. These MOS transistors 2,
Reference numeral 9 denotes a gate insulating film 10 formed on a p-type silicon substrate 8, and a polysilicon film 1 on an upper surface of the gate insulating film 10.
2 are formed. On the side surface of the polysilicon film 12, a post-gate oxide film 11 is formed. The post-gate oxide film 11 is formed by an oxidation process performed after processing the polysilicon film 12. On the upper surfaces of the polysilicon film 12 and the post-gate oxide film 11, a silicon nitride film 14 is formed. On the side surface of the post-gate oxide film 11, a silicon nitride film 13 as a side wall insulating film is formed. Thus, the MOS transistors 2 and 9 have the same structure.

FIG. 2 is a sectional view showing a case where a peripheral circuit portion has a CMOS structure. This CMOS includes an NMOS transistor 15 formed on a p-type silicon substrate 8,
PM formed in N well 17 in p-type silicon substrate 8
And an OS transistor 16. Both the NMOS transistor 15 and the PMOS transistor 16 have the same structure as the MOS transistor 9 in the peripheral circuit section in FIG. FIG. 3 shows a word line drive circuit system 18 for selecting a memory cell. The word line driving circuit system 18 includes a level conversion circuit 19 to which a row address signal RAx output from a row address decoder (not shown) is input, and a word line driving circuit controlled by receiving an output from the level conversion circuit 19. 20 is shown. The level conversion circuit 19 receives the row address signal RAx, and according to the level, increases the boosted potential Vpp of the power supply voltage as, for example, a high-level potential,
The ground potential Vss is output as the low-level potential. The word line drive circuit 20 has a drain connected to the word line WL, and a source to which the word line selection signal WDRV is input.
It has a MOS transistor 21 and an NMOS transistor 22 whose drain is connected to a word line and whose source is grounded. These PMOS transistor 21 and NMO
The gate of the S transistor 22 is commonly used as the level conversion circuit 1
9 driven by the output node N1. The NMOS transistor 23 is a reset transistor, and its gate has a signal / WD having a logic opposite to that of the word line selection signal WDRV.
RV is input. However, the word line selection signal WDRV is the boosted potential Vpp when the word line is selected, and is the ground potential Vss when the word line is not selected. The high level of the inverse logic signal / WDRV is the power supply potential Vcc.

In the word line drive circuit 20, when the word line drive signal WDRV is selected to have the boosted potential Vpp, if the decode signal of the node N1 output from the level conversion circuit 19 is Vss, the PMOS transistor 21 is turned on. The NMOS transistor 22 turns off. Thereby, boosted potential Vpp is applied to word line WL. When the decode signal of the node N1 is Vpp, the NMOS transistor 22 is turned on, the PMOS transistor 21 is turned off, and the word line WL is set to the ground potential Vss. When the word line drive circuit 20 is not selected, the signal / WDRV = Vc
The NMOS transistor 23 is turned on by c, and the word line WL is reset to the ground potential Vss.

[0005]

By the way, as the size of the memory cell becomes finer, the source / drain region of the MOS transistor for information transfer in the memory cell portion becomes higher in density. In addition, the thickness of the gate insulating film has been reduced. For this reason, leakage GIDL (Gate Induced Drain Leakage) between the gate electrode and the drain region is increased, which has an adverse effect on the pause characteristics of the DRAM.
On the other hand, as a method of suppressing GIDL, it is conceivable to increase the thickness of the post-gate oxide film. However, as described above, since the MOS transistor in the memory cell portion and the MOS transistor in the peripheral circuit portion have the same structure,
When the thickness of the post-gate oxide film of the MOS transistor in the memory cell portion is increased, the thickness of the post-gate oxide film of the MOS transistor in the peripheral circuit portion is also increased. This causes a problem that the current driving capability of the MOS transistor in the peripheral circuit section is deteriorated. Further, as the thickness of the gate insulating film is reduced, GIDL in a transistor in a peripheral circuit portion also becomes a problem. For example, focusing on the word line drive circuit 20 shown in FIG.
Between the gate and the drain of the S transistor 21, (Vpp
−Vss). On the other hand, when the word line is selected, N
Also between the gate and the drain of the MOS transistor 22 (V
ss-Vpp). However, normally, one word line is selected in the memory cell array, and the other word lines are not selected.
Increases the time that voltage stress is applied over time,
An increase in GIDL becomes a problem. In order to suppress the GIDL, it is not necessary to increase the thickness of the post-gate oxide film of all the MOS transistors constituting the word line drive circuit 20, and it is sufficient to increase the thickness of only the post-gate oxide film of the PMOS transistor 21.

The present invention has been made in view of the above problems, and has as its object to suppress the GIDL of the information transfer transistor in the memory cell portion while maintaining the current drive capability of the transistor in the peripheral circuit portion. .

[0007]

A semiconductor device according to the present invention comprises: a first MOS transistor for information transfer formed in a memory cell section on a semiconductor substrate;
An information storage capacitor electrically connected to a source / drain region of the transistor; and a second MOS transistor formed in a peripheral circuit portion on the semiconductor substrate, forming the first MOS transistor. The thickness of the post-oxide film formed on the side surface of the gate electrode forming the second MOS transistor is larger than the thickness of the post-oxide film formed on the side surface of the gate electrode forming the second MOS transistor. The gate electrode includes a conductive film containing silicon, a first insulating film formed on an upper surface of the conductive film, and a second insulating film formed on a side surface of the conductive film. The post-oxide film is formed on a side surface of the conductive film. Further, the second MOS transistor constitutes a word line drive circuit, and is turned off particularly when a word line corresponding to the word line drive circuit is not selected. A method of manufacturing a semiconductor device according to the present invention includes a step of forming a first MOS transistor for information transfer in a memory cell section, a step of post-oxidizing the first MOS transistor, and a step of forming a second MOS transistor in a peripheral circuit section. Forming a MOS transistor; post-oxidizing the first MOS transistor and the second MOS transistor; and storing information electrically connected to a source / drain region of the first MOS transistor. Forming a capacitor.

As a result, the present invention makes it possible to suppress the GIDL of the information transfer transistor in the memory cell portion while maintaining the current driving capability of the transistor in the peripheral circuit portion.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS <First Embodiment> A first embodiment of the present invention
The embodiment will be described with reference to the drawings (FIGS. 4 to 12). FIG. 4 is a diagram illustrating a D according to the first embodiment of the present invention.
FIG. 2 is a top view layout diagram of a RAM. Word lines WL and bit lines BL are arranged to intersect. One of the source / drain regions formed so as to sandwich the word line WL is connected to the stacked capacitor SC. The other of the source / drain regions is electrically connected to bit line BL. FIG. 5 is a cross-sectional view taken along line AA ′ of the top layout diagram of FIG. FIG. 5 also shows the NMOS and PMOS portions of the peripheral circuit not shown in FIG. In the memory cell section, a MOS transistor 22 for information transfer is formed on a semiconductor substrate 21. The MOS transistor 22 for information transfer is formed on a gate oxide film 26 formed on a semiconductor substrate 21, a gate electrode formed of a polysilicon film 27 and a tungsten silicide film 28 formed thereon, and a gate electrode formed on the gate electrode. Silicon nitride film 25, a post-oxide film 29 formed on the side surface of the gate electrode, a silicon nitride film 24 formed on the side surface of the post-oxide film 29, and a silicon nitride film 25 formed on the surface of the semiconductor substrate 21 so as to sandwich the gate electrode. And source / drain regions 30.

One of the source / drain regions 30 is connected to a stacked capacitor via a capacitor contact CC. The stacked capacitor has a storage electrode S
N, a capacitor dielectric film 23 formed on the storage electrode SN, and a plate electrode PL formed on the capacitor dielectric film 23. On the other hand, in a peripheral circuit portion, for example, a PMOS portion, similarly to the memory cell portion, a gate oxide film 31 formed on a semiconductor substrate 21 and a gate formed of a polysilicon film 32 and a tungsten silicide film 33 formed thereon. An electrode, a silicon nitride film 35 formed on the gate electrode, a post-oxide film 34 formed on the side surface of the gate electrode, a silicon nitride film 36 formed on the side surface of the post-oxide film 34, and sandwich the gate electrode. And a source / drain region 37 formed on the surface of the semiconductor substrate 21 as described above. The same applies to the NMOS section. here,
The MOS transistor in the memory cell section and the M in the peripheral circuit section
Compared to the OS transistor, the MOS in the memory cell section
The transistor is characterized in that the post-oxide film is formed thicker. For example, the thickness of the post-oxide film 29 of the MOS transistor in the memory cell portion is set to 16 nm, and the thickness of the post-oxide film 34 of the MOS transistor in the peripheral circuit portion is set to 10 n.
m. By doing so, the MOS of the peripheral circuit section
The GIDL of the MOS transistor for information transfer in the memory cell portion can be suppressed while maintaining the current driving capability of the transistor.

FIG. 6 is a cross-sectional view taken along the line BB 'of the top layout diagram shown in FIG. The other of the source / drain regions 30 in the memory cell section is connected to the bit line plug BP on the element isolation region 38, and is electrically connected to the bit line contact BC and the bit line BL. Hereinafter, FIG.
7 to FIG. 6 show a method of manufacturing the DRAM shown in FIG. First, FIG.
As shown in FIG. 3, the STI (Shallow T
An element isolation region 38 such as a trench isolation is formed. Further, a gate oxide film 26, a polysilicon film 27, a tungsten silicide film 28, and a silicon nitride film 25 are sequentially deposited on the semiconductor substrate 21. Further, a resist 39 is applied on the upper surface and is patterned into a predetermined shape. That is, in the memory cell portion, the resist 39 is left only in a portion to be a gate electrode later. next,
As shown in FIG. 8, the patterned resist 39
Is used as a mask to etch silicon nitride film 25 using an anisotropic etching method such as the RIE method. Further, using the resist 39 and the silicon nitride film 25 as a mask, the tungsten silicide film 28, the polysilicon film 27, and the gate oxide film 26 are etched using an anisotropic etching method such as an RIE method. Thereafter, the resist is removed by ashing or the like. Thereby, in the memory cell portion,
A gate electrode part 40 is formed.

Next, as shown in FIG. 9, the gate electrode portion 40 of the memory cell portion is post-oxidized. As a result, a post-oxide film 29 is formed on the exposed surfaces of the polysilicon film 27 and the tungsten silicide film 28 constituting the gate electrode portion 40. Thereafter, the thickness of oxide film 29 is about 6 nm for a test piece (a test semiconductor substrate put in a furnace other than a wafer). Next, as shown in FIG. 10, after a resist 41 is applied to the entire surface, this is patterned into a predetermined shape. That is, the resist 41 is left only in a portion that will be a gate electrode later in the peripheral circuit portion. next,
As shown in FIG. 11, the silicon nitride film 25 is etched by an anisotropic etching method such as RIE using the resist 41 patterned into a predetermined shape as a mask. Further, using the resist 41 and the silicon nitride film 25 as a mask, the tungsten silicide film 28, the polysilicon film 27, and the gate oxide film 26 are etched by an anisotropic etching method such as an RIE method. And resist 4
1 is removed by ashing or the like. Thus, the gate electrode section 42 is formed in the peripheral circuit section. Next, FIG.
As shown in FIG. 3, a gate electrode portion 40 formed in the memory cell portion and a gate electrode portion 42 formed in the peripheral circuit portion
Is post-oxidized. As a result, a post-oxide film 41 and a post-oxide film 34 are formed on the surfaces of the polysilicon film 27 and the tungsten silicide film 28 constituting the gate electrode portion 40 and the gate electrode portion 42, respectively. At this time, the thickness of the post-oxide film 34 formed on the gate electrode portion 42 of the peripheral circuit portion is
The thickness is about 10 nm for a test piece (a test semiconductor substrate placed in a furnace other than a wafer). Thereby, the post-oxide film 2 formed on the gate electrode portion 40 of the memory cell portion is formed.
9 has a thickness of 16 including the steps already shown in FIG.
nm. That is, a gate electrode having a thicker post-oxide film is formed in the memory cell portion than in the gate electrode portion formed in the peripheral circuit portion.

Thereafter, the DRAM shown in FIGS. 4 to 6 is completed by a normal manufacturing process. As described above, according to the first embodiment of the present invention, it is possible to suppress the GIDL of the information transfer transistor in the memory cell unit while maintaining the current driving capability of the transistor in the peripheral circuit unit. <Modification of First Embodiment> A first embodiment of the present invention will be described with reference to the drawings (FIG. 13). The semiconductor device shown in FIG. 13 shows an example in which the present invention is applied to a trench DRAM. The structure and manufacturing method of the information transfer transistor are the same as those in the first embodiment, and the capacitor structure is a trench type. The same components as those already shown in FIG. The trench capacitor TC for storing information is formed in the semiconductor substrate 21. Trench type capacitor TC
A capacitor dielectric film 51 formed on the lower surface of the trench formed in the semiconductor substrate 21, a storage electrode 52 made of a polysilicon film formed to fill the trench, and a capacitor dielectric film 51 interposed therebetween. It is composed of a plate electrode 53 formed opposite to the storage electrode. A collar oxide film 54 for suppressing generation of a parasitic transistor is formed on the upper surface of the trench. One of the source / drain regions 30 of the information transfer MOS transistor is electrically connected to the storage electrode 52.

In this case, the same effect as in the first embodiment can be obtained. <Second Embodiment> A second embodiment of the present invention will be described with reference to the drawings (FIG. 14). The second embodiment is characterized in that the gate post-oxide film of only the P-channel type MOS transistor 21 among the MOS transistors constituting the peripheral circuit portion, for example, the word line drive circuit already shown in FIG. 3, is thickened. And Specifically, this is as shown in FIG. The same components as those already shown in FIG. The difference from the configuration of FIG.
The point is that the thickness of the post oxide film 34 of the MOS transistor in the PMOS portion is the same as the thickness of the post oxide film 29 of the MOS transistor in the memory cell portion. As a result, the GIDL of the information transfer transistor in the memory cell portion is suppressed, and in the word line drive circuit, the P-channel MOS transistor to which a larger voltage stress is applied while maintaining the current drive capability of the N-channel MOS transistor 22 is maintained.
GIDL of the S transistor 21 can be suppressed. Although a P-channel transistor included in the word line driving circuit is illustrated here, this is a peripheral circuit including a plurality of transistors to which different voltage stresses are applied. That is, the voltage stress applied to a plurality of MOS transistors is large,
The purpose of this embodiment is to increase the thickness of the oxide film after the gate although it is desired to suppress L.

As described above, according to the second embodiment of the present invention, in the peripheral circuit portion, the decrease in the current driving capability of the MOS transistor is suppressed to a necessary minimum and the GIDL is also suppressed. GIDL of the transistor can be suppressed.

[0016]

According to the present invention, it is possible to suppress the GIDL of the information transfer transistor in the memory cell portion while maintaining the current driving capability of the transistor in the peripheral circuit portion.

[Brief description of the drawings]

FIG. 1 is a structural sectional view of a conventional DRAM.

FIG. 2 is a cross-sectional view of a CMOS structure of a conventional peripheral circuit.

FIG. 3 is a circuit diagram of a word line driving circuit system.

FIG. 4 is a diagram illustrating a DRA to which the first embodiment of the present invention is applied;
FIG.

FIG. 5 is a sectional view taken along line A-A ′ of FIG. 4;

FIG. 6 is a sectional view taken along line B-B ′ of FIG. 4;

FIG. 7 is a sectional view showing the manufacturing process of the semiconductor device according to the first embodiment of the present invention.

FIG. 8 is a sectional view showing the manufacturing process of the semiconductor device according to the first embodiment of the present invention.

FIG. 9 is a sectional view of the manufacturing process of the semiconductor device according to the first embodiment of the present invention.

FIG. 10 is a sectional view showing the manufacturing process of the semiconductor device according to the first embodiment of the present invention;

FIG. 11 is a sectional view showing the manufacturing process of the semiconductor device according to the first embodiment of the present invention.

FIG. 12 is a sectional view showing the manufacturing process of the semiconductor device according to the first embodiment of the present invention.

FIG. 13 is a cross-sectional view of a semiconductor device according to a modification of the first embodiment of the present invention.

FIG. 14 is a sectional view of a semiconductor device according to a second embodiment of the present invention.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Trench capacitor, 2 ... MOS transistor, 3
... storage electrode, 4 ... capacitor insulating film, 5 ... plate electrode, 6 ... source / drain region, 7 ... bit line, 8
... p-type silicon substrate, 9 ... MOS transistor, 10 ...
Gate insulating film, 11 gate oxide film, 12 polysilicon film, 13 silicon nitride film, 14 silicon nitride film, 15 NMOS transistor, 16 PMOS transistor, 17 N-well, WL word line, BL ... Bit line, SC: Stack type capacitor, AA: Active area, BP: Bit line plug, BC: Bit line contact, CC: Capacitor contact, SN: Storage electrode, PL: Plate electrode, 21: Semiconductor substrate, 23: Capacitor Dielectric film, 24 silicon nitride film, 25 silicon nitride film, 26 gate oxide film, 27 polysilicon film, 28 tungsten silicide film, 29 post-oxide film, 30 source / drain region, 31 gate oxide Film, 32: polysilicon film, 33: tungsten silicide film, 34: post-oxide film, 35 Silicon nitride film, 36
... Silicon nitride film, 37 ... Source / drain region, 38
... Element isolation region, 39 resist, 40 gate electrode portion, 41 resist, 42 gate electrode portion, 51 capacitor dielectric film, 52 storage electrode, 53 plate electrode, TC trench capacitor.

Claims (5)

[Claims] A first MOS transistor for information transfer formed in a memory cell portion on a semiconductor substrate; and a capacitor for information storage electrically connected to a source / drain region of the first MOS transistor. And a second MO formed in a peripheral circuit portion on the semiconductor substrate.
And a thickness of a second oxide film formed on a side surface of a gate electrode constituting the first MOS transistor, the thickness of the second MOS transistor being increased.
A semiconductor device characterized by being thicker than a post-oxide film formed on a side surface of a gate electrode constituting a transistor. 2. The gate electrode includes: a conductive film containing silicon; a first insulating film formed on an upper surface of the conductive film;
A second insulating film formed on a side surface of the conductive film,
2. The semiconductor device according to claim 1, wherein said post-oxide film is formed on a side surface of said conductive film. 3. The semiconductor device according to claim 1, wherein said second MOS transistor forms a word line driving circuit. 4. The semiconductor device according to claim 3, wherein the second MOS transistor is turned off when a word line corresponding to the word line drive circuit is not selected.
13. The semiconductor device according to claim 1. 5. A first MO for information transfer in a memory cell portion.
A step of forming an S transistor; a step of post-oxidizing the first MOS transistor; a step of forming a second MOS transistor in a peripheral circuit portion; and a step of forming the first MOS transistor and the second MOS transistor. A method of manufacturing a semiconductor device, comprising: a post-oxidation step; and a step of forming an information storage capacitor electrically connected to a source / drain region of the first MOS transistor.