JP2001351988A - Protection circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a protection circuit that can prevent a signal inputted from the outside, when a power supply is off form flowing into the power supply and does not cause resistance against electrostatic breakdown to decrease. SOLUTION: This protection circuit is provided with a first conductivity impurity diffusion region 155, a first conductivity impurity diffusion region 156 that is located while being separated by a first conductivity channel region to the impurity diffusion region 155, an electrode 113 that is located while being separated by an insulating film facing the first channel region, a second conductivity impurity diffusion region 152 with high concentration being adjacent to the impurity diffusion region 156, a first conductivity impurity diffusion region 157 adjacent to the impurity diffusion region 152, a first conductivity impurity diffusion region 158 that is located, being separated by the first conductivity second channel region to the impurity diffusion region 157, and an electrode 133 that is located, being separated by the insulating film facing the second region. In the protection circuit, the impurity diffusion region 155 and the impurity diffusion region 58 are connected, the impurity diffusion region 156 and the electrode 133 are connected, and the impurity diffusion region 152 and the impurity diffusion region 157 are connected to the electrode 113.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit for protecting a circuit from positive / negative excessive voltages due to static electricity or the like, and a power supply even when a signal is externally input when no voltage is applied to the power supply. The present invention relates to a protection circuit that can prevent a current from flowing through the protection circuit.

[0002]

2. Description of the Related Art Conventionally, a protection circuit for protecting a circuit device from electrostatic breakdown due to electrostatic discharge is mounted on a semiconductor integrated circuit or the like. However, an increase in the degree of integration of semiconductor devices in recent years has promoted miniaturization of elements and has caused a decrease in electrostatic breakdown resistance of circuits. For this reason, high performance of the protection circuit is regarded as important.

FIG. 4 shows an example of a conventional protection circuit using MOS transistors. As shown in FIG. 4, this protection circuit is provided between the input terminal 1 and the power supply (VCC) 3 in order to effectively release static electricity applied from the input terminal 1.
A protection circuit is arranged between the input terminal 1 and the ground (GND) 5. A P-channel MOS protection circuit 7 is used between the input terminal 1 and the power supply (VCC) 3, and an N-channel MOS protection circuit 9 is used between the input terminal 1 and the ground (GND) 5.

[0004]

However, the protection circuit shown in FIG. 4 has another LSI connected to the input terminal 1 when the power supply 3 is off.
When a signal is applied from the power supply (not shown) (when the power supply is off, the voltage of the power supply is assumed to be 0 V), a current may flow to the power supply 3 or the LSI (not shown) may be destroyed. is there.

In order to prevent this, a P-channel MOS
The protection circuit 7 may not be provided. That is, as shown in FIG. 5, the N-channel MOS protection circuit 9 is arranged only between the input terminal 1 and the ground 5.

However, in this case, although the current can be prevented from flowing into the power supply 3, there is a drawback that the resistance to electrostatic breakdown is reduced.

As shown in FIG. 6, in order to prevent a current from flowing into a power supply and a decrease in resistance to electrostatic breakdown, as shown in FIG.
There is a case where an N-channel MOS protection circuit 13 is arranged between the input terminal 1 and the power supply 3 and an N-channel MOS protection circuit 9 is arranged between the input terminal 1 and the ground 5. Thereby, it is possible to improve the resistance to the electrostatic breakdown while preventing the current from flowing into the power supply 3.

However, in this case, many N-channel MOS transistors are used, and the area of the protection circuit increases.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and it is an object of the present invention to provide a protection circuit capable of preventing all of a current from flowing into a power supply, a reduction in resistance to electrostatic breakdown, and an increase in the area of the protection circuit. The purpose is to provide.

[0010]

The feature of the present invention is that (1)
A floating well region of a second conductivity type located in a semiconductor substrate of a first conductivity type; (2) a first impurity diffusion region of a first conductivity type located on a surface of the floating well region; (4) a second impurity diffusion region of the first conductivity type located on the surface of the well region and separated by a first channel region of the first conductivity type with respect to the first impurity diffusion region; A first electrode located opposite to the first channel region with an insulating film interposed therebetween;
(5) a high-concentration third impurity diffusion region of the second conductivity type located on the surface of the floating well region and adjacent to the second impurity diffusion region; and (6) located on the surface of the floating well region. And a fourth impurity diffusion region of a first conductivity type adjacent to the third impurity diffusion region; and (7) a first impurity diffusion region located on the surface of the floating well region and having a first position with respect to the fourth impurity diffusion region. A fifth impurity diffusion region of the first conductivity type located across the second channel region of the conductivity type, and (8) a second electrode located opposite the second channel region with the insulation film therebetween. (9) the first impurity diffusion region is connected to the fifth impurity diffusion region, (10) the second impurity diffusion region is connected to the second electrode, and (11) the A third impurity diffusion region and the third impurity diffusion region; The impurity diffusion region of the first
Is connected to the electrodes.

Another feature of the present invention is that (1) the first impurity diffusion region and the fifth impurity diffusion region are connected to an input terminal and an input circuit, and (2) the second impurity diffusion region and The second electrode is connected to a power supply.

Another feature of the present invention is that (1) the first impurity diffusion region, the first channel region, the first electrode, and the second impurity diffusion region form a first MOS transistor. (2) the fourth impurity diffusion region,
The second channel region, the second electrode, and the fifth impurity diffusion region form a second MOS transistor, and (3) the first MOS transistor and the second MOS transistor The third impurity diffusion region is located apart from the third impurity diffusion region.

Another feature of the present invention is that the first conductivity type is P
And the second conductivity type is an N-type.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to the drawings.

1 to 3 show one embodiment of the present invention.
FIG. 1 is an overall view of a circuit including an N-channel MOS protection circuit 90 and a protection circuit 100 in which a P-channel MOS transistor is arranged in a floating N well. FIG. 2 is a sectional view of the protection circuit 100. FIG. It is a conceptual diagram of an application example.

In FIG. 1, a protection circuit 100 is arranged between an input terminal 1 and a power supply 3, and the input terminal 1 is connected to a ground 5.
An N channel MOS protection circuit 90 is arranged between the two.
The protection circuit 100 includes a floating N-well 150,
P channel MOS transistor 110 and P channel M
An OS transistor 130.

In FIG. 2, a floating N well 1
50, high-concentration N-type impurity diffusion regions 151, 15
2,153 and the high-concentration P-type impurity diffusion regions 155,1
56, 157 and 158 are formed.

Further, P-type impurity diffusion regions 155, 158
Are connected to the input terminal 1 and the input circuit 11. The P-type impurity diffusion region 156 and the electrode 133 are connected to the power supply 3. N-type impurity diffusion region 152 and P-type impurity diffusion region 157 are connected to electrode 113.

Then, the P-type impurity diffusion regions 155, 15
6 and the electrode 113 form a P-channel MOS 110 using the P-type impurity diffusion region 156 as a source, the electrode 113 as a gate, and the P-type impurity diffusion region 155 as a drain.

Further, P-type impurity diffusion regions 157 and 158
And the electrode 133 have a P-type impurity diffusion region 157 as a source,
A P-channel MOS 130 is formed using the electrode 133 as a gate and the P-type impurity diffusion region 158 as a drain.

(1) When static electricity is applied to the input terminal 1, the P-channel MOS 110 operates as a protection circuit for preventing electrostatic breakdown. That is, the static electricity applied to the input terminal 1 flows to the power supply 3 via the P-channel MOS 110.

(2) Next, a case where no voltage is applied to the power supply 3 but a signal is input to the input terminal 1 from another LSI (not shown) will be described.

(21) When the input terminal 1 is lower than the element threshold voltage of the P-channel MOS transistor 130, no current flows from the P-type impurity diffusion region 158 to the floating N well 150. That is, the signal input to the input terminal 1 flows to the input circuit 11.

(22) When the input terminal 1 is equal to or higher than the element threshold voltage of the P-channel MOS transistor 130, a current flows from the P-type impurity diffusion region 158 to the floating N well 150, and the floating N well 150 is input to the input terminal 1. Voltage rises. Further, the N-type impurity diffusion region 152
Current flows from type impurity diffusion region 152 to electrode 113. Thereby, the P-type impurity diffusion region 158, the floating N well 150, and the N-type impurity diffusion region 15
2 and the electrode 113 have the same potential.

Since the P-type impurity diffusion region 155 has the same potential as the P-type impurity diffusion region 158,
3, the P-type impurity diffusion region 155 and the floating N well 150 have the same potential. Since the power supply 3 is off, the voltage of the P-type impurity diffusion region 156 is 0 volt.

That is, the P-channel MOS transistor 1
Since the gate, drain, and N-well of 10 have the same potential, P-channel MOS transistor 110 is off. Therefore, since there is no current path from the input terminal 1 to the power supply 3, the signal input to the input terminal 1
Flow to 1.

Therefore, when the power supply 3 is off, the input terminal 1
Current can be prevented from flowing to the power supply 3 even if a signal is input from another LSI.

(3) Next, a case where a voltage is applied to the power supply 3 and a signal having a voltage higher than the voltage of the power supply 3 is input to the input terminal 1 from another LSI will be described.

(31) When the input terminal 1 is higher than the voltage of the power supply 3 but lower than the element threshold voltage of the P-channel MOS transistor 130, no current flows from the P-type impurity diffusion region 158 to the floating N well 150. That is, the signal input to the input terminal 1 flows to the input circuit 11.

(32) When the input terminal 1 is equal to or higher than the voltage of the power supply 3 and equal to or higher than the element threshold voltage of the P-channel MOS transistor 130, a current flows from the P-type impurity diffusion region 158 to the floating N well 150, N well 150 rises to the voltage input to input terminal 1. Further, the N-type impurity diffusion region 15 is transferred from the floating N-well 150 to the N-type impurity diffusion region 152.
A current flows from 2 to the electrode 113. Thereby, the P-type impurity diffusion region 158 and the floating N well 15
0, the N-type impurity diffusion region 152, and the electrode 113 have the same potential.

Since the P-type impurity diffusion region 155 has the same potential as the P-type impurity diffusion region 158,
3, the P-type impurity diffusion region 155 and the floating N well 150 have the same potential. Further, the P-type impurity diffusion region 1
56 has the same potential as the power supply 3.

That is, the P-channel MOS transistor 1
Since the gate, drain, and N-well of 10 have the same potential, P-channel MOS transistor 110 is off. Therefore, since there is no current path from the input terminal 1 to the power supply 3, the signal input to the input terminal 1
Flow to 1.

Therefore, even if a signal is input to the input terminal 1 from another LSI while a voltage is applied to the power supply 3,
Current can be prevented from flowing through the power supply 3.

That is, according to the protection circuit of this embodiment,
(1) Electrostatic breakdown can be prevented by the P-channel MOS transistor 110, and (2) Even when a signal is input when the power supply 3 is off, current flows into the power supply 3 and an LSI (FIG. (Not shown) can be prevented.

The protection circuit of this embodiment is, for example, shown in FIG.
The 3V power supply LSI (not shown) as shown in FIG.
It is effective as a protection circuit in a different potential interface between LSIs having the input circuit 200.

[0036] Application specific integrated circuits (ASICs)
In the gate array method, which is one of the configuration methods, only transistors are prepared in advance, and the wiring pattern between the transistors is changed according to the purpose. That is, the number of P-channel MOS transistors and N-channel MOS transistors that can be used as a protection circuit is often determined in advance.

When the prior art shown in FIG. 5 is applied to a gate array type ASIC, a P
No wiring is made to the channel MOS transistor. That is, all the P-channel MOSs made for the protection circuit
There is a waste that no transistor is used.

When the conventional technique shown in FIG. 6 is applied to a gate array type ASIC, N-channel MOS transistors are used for both the power supply side protection circuit and the ground side protection circuit. The number of N-channel MOS transistors that can be used is halved compared to the case where channel MOS transistors are used. Therefore, the durability is reduced to about half as compared with the case where all the N-channel MOS transistors are used for the ground-side protection circuit.

However, the protection circuit according to the present embodiment has (1)
P-channel MOS transistors can be used as a power-supply-side protection circuit without waste, and (2) all N-channel MOS transistors can be used as a ground-side protection circuit, so that resistance on the ground side does not decrease. .

[0040]

As described above, according to the present invention,
(1) While being able to prevent electrostatic breakdown,
(2) Even when no voltage is applied to the power supply of the input circuit, current can be prevented from flowing from the input terminal to the power supply.

Further, when the present invention is applied to a gate array type ASIC, a P-channel MOS transistor is used for the power supply side protection circuit and an N-channel MOS transistor is used for the ground side protection circuit.
The P-channel MOS transistor is not wasted and is not wasted, and (2) the number of N-channel MOS transistors used on the ground side is reduced by half and the durability is not reduced.

[Brief description of the drawings]

FIG. 1 shows an embodiment of the present invention, in which an N-channel MOS
FIG. 3 is an overall diagram of a circuit including a protection circuit (ground side) and a protection circuit (power supply side) in which a P-channel MOS transistor is arranged in a floating N well.

FIG. 2 is a sectional view of the protection circuit (power supply side) shown in FIG.

FIG. 3 is a conceptual diagram of an application example of the protection circuit shown in FIG.

FIG. 4 shows an example of a conventional protection circuit, in which a P-channel MOS protection circuit is used on the power supply side and an N-channel MOS protection circuit is used on the ground side.

FIG. 5 shows another example of a conventional protection circuit, in which an N-channel MOS protection circuit is used only on the ground side.

FIG. 6 shows another example of a conventional protection circuit, in which an N-channel MOS protection circuit is used on both the power supply side and the ground side.

[Explanation of symbols]

 Reference Signs List 1 input terminal 3 power supply 5 ground 11 input circuit 90 N-channel MOS protection circuit 110 P-channel MOS protection circuit 130 P-channel MOS protection circuit 150 floating N-well

 ────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor Yasunori Tanaka 25-1, Ekimae Honcho, Kawasaki-ku, Kawasaki, Kanagawa Prefecture Inside Toshiba Microelectronics Co., Ltd. Address F-term in Toshiba Microelectronics Center (reference) 5F038 BH07 BH13 BH14 CA02 CA04 EZ12 EZ20 5F048 AA02 AB02 AB06 AC03 BE10 CC09 CC12 CC15 CC19

Claims (4)

[Claims] A first conductive type floating well region located in a first conductive type semiconductor substrate; a first conductive type first impurity diffusion region located on the surface of the floating well region; and the floating well A second impurity diffusion region of a first conductivity type located on a surface of the region and separated by a first channel region of a first conductivity type with respect to the first impurity diffusion region; A first electrode positioned opposite to the region with an insulating film interposed therebetween; and a high-concentration second conductive type third impurity positioned on the surface of the floating well region and adjacent to the second impurity diffusion region. A diffusion region; a fourth impurity diffusion region of a first conductivity type located on the surface of the floating well region and adjacent to the third impurity diffusion region; A fifth impurity diffusion region of a first conductivity type, which is located on a surface and is separated by a second channel region of a first conductivity type from the fourth impurity diffusion region; and the second channel region. A second electrode that is located opposite to the semiconductor device with an insulating film interposed therebetween, wherein the first impurity diffusion region and the fifth impurity diffusion region are connected, and the second impurity diffusion region and the second impurity diffusion region are connected to each other. An electrode is connected, and the third impurity diffusion region and the fourth impurity diffusion region are connected to the first electrode. 2. The semiconductor device according to claim 1, wherein the first impurity diffusion region and the fifth
The protection circuit according to claim 1, wherein the impurity diffusion region is connected to an input terminal and an input circuit, and the second impurity diffusion region and the second electrode are connected to a power supply. 3. The first impurity diffusion region, the first channel region, the first electrode, and the second impurity diffusion region form a first MOS transistor, and the fourth impurity diffusion A region, the second channel region,
The second electrode and the fifth impurity diffusion region are formed by a second
3. The protection circuit according to claim 1, wherein the first MOS transistor and the second MOS transistor are located with the third impurity diffusion region being separated. 4. 4. The method according to claim 1, wherein the first conductivity type is P-type, and the second conductivity type is P-type.
4. The protection circuit according to claim 1, wherein the conductivity type is N-type.