JP2001351977A - Formation method of via stud, and semiconductor structure - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an interconnection part that has an improved electromigration life. SOLUTION: This formation method of a via stud includes a process that prepares a substrate 10 having first level adhesion metal 20 (a), a process that allows a layer 35 of an insulator to adhere (b), and a process that etches the insulator by a first etchant to form a related level. The related level has a line opening 33 and a via opening 34. Etching by the first etchant exposes the first level metal at the lower side of the via opening and includes a process that etches the exposed first level metal, so that the opening is formed (d) and a process that allows a linear 51 to adhere (e). The liner lines nearly the entire bottom part of the exposed first level metal and nearly the entire sidewall of the opening of the related level other than the nearly the entire sidewall of the first level metal.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

FIELD OF THE INVENTION The present invention relates generally to semiconductor devices and, more particularly, to submicron sized semiconductor devices having high conductivity conductors insulated by low dielectric constant dielectrics. It relates to the structure of high performance interconnects.

[0002]

2. Description of the Related Art Improved performance in semiconductor integrated circuits (ICs) is achieved by reducing loss rates. The loss rate is directly related to the inductance, capacitance, and resistance of the interconnect. Recently, conventional aluminum-based metals have been replaced by high conductivity copper metals to facilitate the reduction of interconnect resistance. Interconnect methods involving multi-level wiring have been successful in reducing inductance. However, interlayer insulators and increased wiring densities have caused sub-quarters (sub)
-Quarter) increase the interconnect capacitance in microns so that the interconnect capacitance is
It is a major factor in device performance. One way to reduce capacitance is to reduce the dielectric constant (k) of the insulator separating the conductive lines. Since "air" is known to have the lowest dielectric constant (k = 1), organic or inorganic materials containing large amounts of trapped air have been developed. One such material is a porous organic silicate glass. Accordingly, an interconnect made of copper-based metal and a porous insulator are desired.

[0003] One of the limitations of copper-based metals is that a barrier layer (usually one or more layers of refractory metal) is required to provide adhesion and corrosion protection to the copper conductor.
In multilevel interconnects, electrons must pass through this barrier layer as they flow from one level interconnect to another.

[0004] High current density causes mass transport to conductor lines (a phenomenon known as electromigration).
It is known to form voids in conductor lines to form electrical open circuits. Abrupt changes in mass transport rates (divergence of atomic flux) have been shown to be a major cause of electromigration. Thus, the presence of the barrier metal within the interconnect of the high conductivity metal causes a sudden divergence of the atomic flux and the formation of voids. This is shown in FIG. FIG. 1 is a cross-sectional view of a multi-level interconnect of the state of the art. The n-th level interconnect line M1 (1) is formed by the damascene method, and the (n + 1) -th level interconnect line M2 (3) and the bias stud V1 (2) are connected to a double (dual) damascene. Formed by the method. The interconnect lines and bias studs have barrier layers on the sides and bottom of the conductor lines and studs. As shown, the bias stud V1
, Must flow through the refractory metal barrier layer at the bottom of the bias stud V1. The low diffusivity of copper atoms in the barrier layer metal causes a sharp decrease in the atomic flux density just below the barrier layer at the bottom of the bias stud V1, as shown in FIG.
Eventually, voids 4 are formed.

The use of a porous insulator creates an electrical open circuit at the same interface between the bias stud layer V1 and the interconnect line M1. The electrical open circuit is interconnect line M1
Is a result of the mechanical separation of the bias stud V1 from the interconnect line M1 caused by the weak mechanical integrity of the surrounding insulator which allows the physical movement of the bias stud V1 to V1. Relative physical movement is the result of expansion and contraction during the heat stroke.

[0006] Thus, despite some inventions of methods and structures, the problem of electrically open circuits in ICs remains, and a method must be sought for its solution.

[0007]

SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide an interconnect having improved electrical performance of a semiconductor IC.

It is another object of the present invention to provide an interconnect having an improved electromigration lifetime.

It is yet another object of the present invention to provide an interconnect in which there is no barrier metal in the path of current flow between the various levels of interconnect.

It is yet another object of the present invention to provide a copper metal based interconnect having no barrier metal in the path of the current flow.

Yet another object of the present invention is to provide an interconnect having an increased surface area for contact between a copper conductor line and a copper bias stud.

It is yet another object of the present invention to provide an interconnect having reduced contact resistance.

[0013]

SUMMARY OF THE INVENTION These and other objects (as will be apparent to those skilled in the art) are achieved in the present invention involving a high conductivity copper interconnect having improved electromigration lifetime. . In one aspect, the present invention provides a semiconductor IC chip having a copper line and bias stud interconnect. The copper line has a barrier layer on its sides and bottom, and the bias stud is a coaxial barrier such that there is no barrier layer between the bias stud and the conductor line above or below the barrier layer. It has a layer partially. The interconnect is achieved by partially or completely etching the copper in the conductor line directly below the bias stud.

In a related aspect, the present invention is directed to a method of forming a copper interconnect having improved electromigration lifetime using a dual damascene method. The method comprises the steps of depositing one or more insulators on a semiconductor substrate, defining a bias stud pattern by photolithography, partially etching the insulator layer, and removing a resist process. Lithographically defining the interconnect pattern, and at most,
Etching the insulator layer and copper in the lower metal line until the barrier layer of the M1 metal line stops further etching. In the second etching process, the reactive gas used, for example CHF
A high sputter / reaction ratio is achieved by introducing argon with ₃ , or by increasing the argon / CHF ₃ ratio and negatively biasing the substrate. This condition promotes copper etching not only due to increased physical erosion, but also due to the formation of complex Cu-OHF molecules at low vapor pressure. In practice, the role of argon here is to provide a continuous fresh copper surface to continue the reaction by physical attack of the Cu-O-H-F compound. Subsequent to this cavity formation, a barrier metal is deposited in the trenches and via holes, followed by a copper seed layer, electrodeposited copper, and chemical mechanical polishing. The deep bias stud holes have copper undercuts in the lower conductor lines to prevent barrier layers from adhering to the sidewalls. As a result, a continuous copper interface is formed between the bias stud and the lower conductor line.

[0015] In still another aspect, the present invention provides, first,
A method for forming a hole for a bias stud by forming a via hole in an insulator by reactive ion etching and subsequently removing the copper under the via hole with a chemical etchant. Various organic and inorganic materials are known in the art for etching copper at a controlled rate.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A preferred embodiment will be described with reference to FIGS. In these figures, the same reference numbers indicate the same elements of the invention.

FIG. 3 shows a cross-sectional view of a conventional silicon semiconductor structure. In the figure, all the semiconductor devices and
Contact studs that contact these semiconductor devices and are included in the substrate 10 and contacts not formed on the relevant level are not shown. Also, as shown in FIG. 3, a portion of the first level high conductivity metal interconnect line pattern (M1) 20 is fabricated using prior art methods. The interconnect line 20 comprises a barrier layer 21
And copper interconnect line 22, the top surface of line 22 being substantially coplanar with surrounding dielectric 25. As shown in FIG. 4, the current technique for dual damascene is implemented to deposit a thin layer 31 of silicon nitride and a thin layer 35 of an interlevel dielectric layer. The material of the interlevel dielectric layer can be organic or inorganic, but preferably has a low dielectric constant. Next, a bias stud pattern is photolithographically defined on the dielectric 35, followed by partial removal of the dielectric 35 with a suitable etchant, preferably using reactive ion etching (RIE). An etching step is performed. Next, the pattern for the second level interconnect lines is photolithographically defined and the interlevel oxide 35 is etched to form trenches 3.
3 and a hole 34 are formed. This etching is performed until the nitride layer 31 is completely etched away and the metal line 22 is exposed. The final form of the current technology is shown in FIG. In FIG. 5, a hole 34 corresponding to the bias stud pattern (V1) and a trench 33 corresponding to the second level interconnect line pattern (M2) are formed in the interlevel dielectric layer 35. . By first defining a second metal interconnect pattern and partially etching the dielectric 35 and then defining a bias stud and etching the dielectrics 35 and 31, It should be noted that the sequence of pattern definition can be reversed. In either method, the partial etching step includes the trench 33 and the hole 3
The depth of 4 is adjusted to correspond to the desired interconnect metal line thickness and bias stud height, respectively.

The present invention is implemented at this point in the process. That is, at the point when the combined bias stud pattern and interconnect line pattern are etched into insulating layers 31 and 35 to expose copper on a portion of first level interconnect line 22. In the present invention, the exposed copper of the first level interconnect lines 22 under the bias stud opening 34 is at least partially etched to form a cavity, as shown in FIG. During the second etching step, the interlevel dielectric 3
With the etchant used to etch 5, argon was also observed to etch copper. Typical silicon - etchants against oxygen between the base of the level dielectrics used is typically a fluorinated hydrocarbon, for example, fluoroform (CHF _3). Second
In certain cases where a small amount of argon is used in the etching step, the ratio of argon to fluoroform must be increased. Preferably, the ratio should be greater than 1: 1. FIG. 6 shows a cavity 40 formed in the first level metal 22 as a result of metal etching.

In many of the ways described below, copper etching can be enhanced by adjusting the RIE parameters to increase the argon bombardment on the substrate. I) reducing the positive bias voltage provided on the substrate plate; ii) providing a negative bias voltage to the substrate electrode if a grounded substrate is used; iii) providing a positive bias voltage on the non-substrate electrode. Increase the bias voltage, iv) raise the substrate temperature to 200-400 ° C.,
v) Introduce oxygen together with fluoroform. In all of the above cases, the purpose is to etch the copper by continuously removing the organic polymer formed on the copper surface during the plasma etch. The organic polymer is removed by mechanical attack by argon bombardment, by oxidation with oxygen, or both. In addition to removing the polymer film, large complex copper molecules formed by the presence of oxygen and fluorine in the plasma, eg, Cu _x (OF)
By eroding _y , argon promotes the etching of copper. The amount of copper etching required is 50
It should be noted that it can be very small, from 0 ° to 4000 °. Etching can be increased if desired by the end user. Preferably, as shown in FIG.
It should be noted that the zero sidewalls 41 are drawn under the nitride layer 31.

Restarting the remaining steps of the double damascene process, sputter deposit the barrier layer 51 shown in FIG. The nitride layer overhang described above and the directional deposition characteristics of the sputter deposition method play a crucial role in preventing the deposition of barrier layer metal 51 on first level metal sidewalls 41. Next, an electroplated copper layer 52 is deposited to fill the cavities 33, 34, and 40, followed by chemical mechanical polishing to remove any excess metal from the unpatterned areas. 8 is obtained. This allows dual damascene
The process is completed and a second level interconnect line pattern 50 and a bias stud pattern 60 are formed. It should be noted that the copper at the bottom of the bias stud 60 filling the cavity 40 is in direct contact with the first level interconnect lines 22 and there is no barrier layer separating them. Thus, in the interconnect of the present invention, the second level metal 50 is converted to the first level metal 2 through the barrier stud 60 without passing through the barrier layer.
Electrons flow to zero. As a result, no flux divergence occurs, and thus a sufficiently improved electromigration life is obtained.

In another embodiment of the invention, the copper etch under the bias stud is performed externally. In the method described above where the nitride layer 31 is etched to expose the metal lines 22 as shown in FIG. 5, the wafer is removed from the RIE tool after the second etching step is completed. The copper 22 under the viaast opening 34 is chemically etched using one of several copper etchants known in the art, for example, an aqueous solution of iodine and potassium iodide, or dilute sulfuric acid. 6, cavity 40 of FIG.
To form a cavity similar to. It should be noted that the etching of copper in this process step by any other means, such as ion beam etching, is within the scope of the present invention.

It should be noted that the method of the present invention contemplates forming the second metal line and via separately. In this case, the steps of the method are the same as the steps of embedding the bias stud in the previous metal level.

Although the present invention has been described with respect to particular embodiments, given the teachings and explanations herein,
Many variations and modifications will be apparent to those skilled in the art. For example, it can be seen that the copper metal of the preferred embodiment can be replaced with any metal using a barrier layer. Also, the dielectric can be any solid or porous low dielectric constant material. Further, although the example given here is for a double damascene method, it is equally applicable to a single damascene method for forming interconnect lines and bias studs. Further, the teachings described herein are equally applicable to interconnects made in a subtractive etching process. Furthermore, the present invention is intended to cover all modifications and changes that fall within the scope of the appended claims.

In summary, the following matters are disclosed regarding the configuration of the present invention. (1) a method of forming a bias stud, comprising: a) providing a substrate having at least a first level of deposited metal; b) depositing a layer of insulator; c) forming an associated level. Etching said insulator with a first etchant, said associated level comprising at least one line opening and at least one line opening.
Etching with the first etchant exposes the first level of metal below the via opening; and d) forming an opening with the first etchant. Etching the exposed first level metal as formed, wherein the opening has sidewalls and a bottom; and e) depositing a liner, wherein the liner comprises the exposed liner. A method of lining substantially all of the bottom of the first level metal and substantially all of the sidewalls of the associated level opening, except for substantially all of the exposed first level metal sidewalls. (2) The method according to (1), wherein the insulator is an organic or inorganic material. (3) The method according to (1), wherein the insulator is selected from the group consisting of silicon oxide, silicon nitride, a composite of a silicon oxide layer and a silicon nitride layer, and organic silicate glass. (4) The method according to (3), wherein the insulator has a dielectric constant smaller than 4.0. (5) The above (2), wherein the insulator is chemically porous.
The method described in. (6) The method according to (2), wherein the insulator has a breaking strength close to zero. (7) The method according to (1), wherein the exposed copper is etched in-situ with an argon-containing etchant. (8) The method according to (1), wherein the exposed copper is etched in another place by using a method selected from the group consisting of exposure to wet chemicals, ion beam etching, and sputter etching. Method. (9) Substantially all of the exposed previous level metal is
The method according to the above (1), wherein the etching is performed. (10) The method of (1) above, wherein the exposed previous level metal is etched to draw sidewalls of the pre-etched level metal below the insulator. (11) The method of (1) above, wherein the exposed previous level of metal is etched to draw the etched copper sidewalls below the insulator. (12) The method according to (1), wherein the liner is selected from the group consisting of tantalum, tantalum nitride, chromium-chromium oxide, tungsten, tungsten-silicon, titanium, copper, or a combination thereof. (13) The method according to the above (1), further comprising depositing a metal in the liner opening. (14) The above (1), wherein the metal is a high conductivity metal.
The method according to 3). (15) The method according to (14), wherein the metal is electroplated copper. (16) a first metal layer provided in the insulator;
The first metal layer has a bottom liner layer and a top barrier layer, and includes a second metal layer provided in an insulator, the second metal layer having a bottom liner layer. A bottom liner of the second metal layer, wherein at least a portion of the second metal layer and the first metal layer are formed of an upper barrier layer of the first metal layer and a second metal layer; A semiconductor structure provided in the first metal layer so as not to be separated by a bottom liner layer. (17) The semiconductor structure according to (15), wherein the upper barrier layer is selected from the group consisting of silicon nitride and aluminum oxide. (18) The semiconductor structure according to (16), wherein the first and second metal layers include a copper-containing compound. (19) The material of the bottom liner of the first and second metal layers is tantalum, tantalum nitride, chromium-chromium oxide, tungsten, tungsten-silicon, titanium,
Selected from the group consisting of copper, or combinations thereof,
The semiconductor structure according to the above (17). (20) The semiconductor structure according to (17), wherein the bottom liner of the second metal is in contact with the bottom liner of the first metal.

[Brief description of the drawings]

FIG. 1 is a simplified cross-sectional view of a state-of-the-art interconnect showing portions of first and second level interconnect metals that connect to each other via a bias stud.

FIG. 2 is a cross-sectional view, similar to FIG. 1, of an interconnect failing an electromigration stress test.

FIG. 3 is a cross-sectional view of a semiconductor substrate formed to a first level metal interconnect by a process of the state of the art, illustrating a starting stage of the present invention.

FIG. 4 is a cross-sectional view of a semiconductor substrate formed to a first level metal interconnect by a process of the state of the art, showing a starting stage of the present invention.

FIG. 5 is a cross-sectional view of a semiconductor substrate formed to a first level metal interconnect by a process of the state of the art, illustrating a starting stage of the present invention.

FIG. 6 is a sectional view of a semiconductor substrate in an intermediate process according to the present invention.

FIG. 7 is a sectional view of a semiconductor substrate in an intermediate process of the present invention.

FIG. 8 is a cross-sectional view of the interconnect of the present invention.

FIG. 9 is a perspective view showing a final structure excluding a peripheral insulator layer.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 Substrate 20 First level interconnect line pattern 21 Barrier layer 22 Copper interconnect line 25 Dielectric 31 Thin layer of silicon nitride 33 Trench 34 Hole 35 Thin layer of dielectric layer 40 Cavity 41 Side wall 50 Second level interconnect Connection line pattern 51 Barrier layer 60 Biased pattern

Continued on the front page (72) Inventor Houma Dier M Dalal USA 12540 Lagrangeville Verry Road, New York 94 (72) Inventor Valendra Agharwala United States 12533 Hopewell Junction Saddle Ridge Drive 56, New York 56 (72) Inventor Terence Cane United States 12590 Wappingers Falls, New York Bowdoin Lane 26 (72) Inventor Paul S. McLaughlin United States 12601 Powkeepsie David Drive 103, New York 103 (72) Inventor Du Newyen United States 06810 Danbury Hickory Street, Connecticut 15 (72) Invention Richard Proctor United States 12533 Hopewell Junction Break Drive New York 9 (72) Inventor Hazara S. Lathoir United States 12582 Stormville Judith Drive, New York 27 (72) Inventor Yun-You Wong United States 12570 Pookeig Cipher Lane 34, New York 34 F-term (reference) 5F004 AA05 CA04 CA06 DA16 DA23 DA26 DB00 DB07 DB08 EB02 5F033 HH07 HH11 HH17 HH18 HH19 HH21 HH27 HH28 HH32. TT04 WW00 WW09 XX01 XX09 XX19 XX24 XX25

Claims (20)

[Claims] 1. A method of forming a bias stud, comprising: a) providing a substrate having at least a first level of deposited metal; b) depositing a layer of an insulator; Etching said insulator with a first etchant to form said at least one line opening and at least one line opening.
Etching with the first etchant exposes the first level of metal below the via opening; and d) forming an opening with the first etchant. Etching the exposed first level metal as formed, wherein the opening has sidewalls and a bottom; and e) depositing a liner, wherein the liner comprises the exposed liner. A method of lining substantially all of the bottom of the first level metal and substantially all of the sidewalls of the associated level opening, except for substantially all of the exposed first level metal sidewalls. 2. The method according to claim 1, wherein said insulator is an organic or inorganic material. 3. The insulator according to claim 1, wherein the insulator is selected from the group consisting of silicon oxide, silicon nitride, a composite of a silicon oxide layer and a silicon nitride layer, and an organic silicate glass.
The method described in. 4. The method of claim 3, wherein said insulator has a dielectric constant less than 4.0. 5. The method of claim 2, wherein said insulator is chemically porous. 6. The method of claim 2, wherein said insulator has a breakdown strength near zero. 7. The method of claim 1, wherein said exposed copper is etched in-situ with an argon-containing etchant. 8. The method of claim 1, wherein the exposed copper is etched in another location using a method selected from the group consisting of exposure to wet chemicals, ion beam etching, and sputter etching. the method of. 9. The method of claim 1, wherein substantially all of the exposed previous level metal is etched. 10. The method of claim 1, wherein said exposed previous level metal is etched to draw sidewalls of said etched previous level metal underneath said insulator. 11. The method of claim 1 wherein said exposed previous level of metal is etched to draw etched copper sidewalls underneath said insulator. 12. The method of claim 1, wherein said liner is selected from the group consisting of tantalum, tantalum nitride, chromium-chromium oxide, tungsten, tungsten-silicon, titanium, copper, or a combination thereof. 13. The method of claim 1, further comprising depositing a metal in said liner opening. 14. The method of claim 13, wherein said metal is a high conductivity metal. 15. The method according to claim 14, wherein said metal is electroplated copper. 16. A semiconductor device comprising: a first metal layer provided in an insulator, the first metal layer having a bottom liner layer and an upper barrier layer, and a first metal layer provided in the insulator. And a second metal layer.
Has a bottom liner layer, and the bottom liner of the second metal layer has at least a portion of the second metal layer and the first metal layer formed of the first metal layer. A semiconductor structure provided in said first metal layer so as not to be separated by an upper barrier layer and a bottom liner layer of said second metal layer. 17. The semiconductor device according to claim 1, wherein said upper barrier layer is selected from the group consisting of silicon nitride and aluminum oxide.
6. The semiconductor structure according to 5. 18. The semiconductor structure according to claim 16, wherein said first and second metal layers include a copper-containing compound. 19. The material of the bottom liner of the first and second metal layers is tantalum, tantalum nitride, chromium-chromium oxide, tungsten, tungsten-silicon, titanium, copper, or a combination thereof. 18. The semiconductor structure according to claim 17, wherein the semiconductor structure is selected from: 20. The semiconductor structure according to claim 17, wherein said second metal bottom liner is in contact with said first metal bottom liner.