JP2001350675A - Serial interface circuit and its testing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a serial/parallel interface capable of determining at what point of time an error occurred on output data. SOLUTION: The data set on an internal register are temporarily retained on a latch circuit after being read out, and the data retained on the latch circuit are read out. Serial data are read out interlockingly with the lack or excess readout clocks, readout is repeated according to the number of the data on the internal register, and the first readout data are compared with the second and subsequent readout data. If a difference is detected, it is judged that a noise is mixed in readout clocks.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a serial interface (S / P I / F).

[0002]

2. Description of the Related Art Generally, in an electronic device, a CP is used.
It is composed of a plurality of IC groups under the control of the U and the CPU, which are classified according to functions.

The CPU and the IC group are connected by a data bus and a data bus control line. The input / output method includes a parallel I / F, that is, a method of inputting / outputting with a bus width in bytes, and a serial I / F. The method is roughly divided into a method of inputting and outputting data in bit units called / F.

In recent years, there has been a trend in electronic device development to reduce the size of the device, reduce the area of the substrate inside the device, and reduce the number of wires on the substrate for data input / output. Has been widely adopted.

FIG. 4 shows the structure of a timing generator of a conventional S / P I / F. Data enable signal (/ EN)
Are active (= “L”) and the read / write signal (R / W) corresponds to an address given as a part of the serial data (SDIN) at the time of writing (= “L”). Data given as a part of SDIN is written to the internal register after S / P conversion.
Thereby, the internal state of the control IC is set. Thereafter, when reading the internal data of the IC (R / W = “H”), the internal data of the IC is output for each serial clock (SCLK) corresponding to the above address.

[0006]

As described above in connection with the prior art, a recent trend in electronic device development demands a reduction in device size. Along with this, the internal substrate has been multi-layered and the wiring width and the wiring interval have been narrowed,
So-called noise such as signal leakage and interference between adjacent wiring lines is generated, and the possibility of malfunction due to this noise is increasing. As an example, an I / O between the CPU, which is the control center of the internal board, and the ICs for each function,
If the malfunction occurs due to the noise in the F data, a serious problem is likely to occur in the stable operation of the device.

More specifically, when the SCLK is increased by one clock from the prescribed number due to noise, it is equivalent to adding one bit of meaningless data other than normal data as serial data.

In general, it is not possible to determine whether or not the data is normal in the serial I / F section of the IC for each function which has received the serial data to which the meaningless data is added.

In order to determine whether the received data is valid or not, it is general to perform a paired comparison between the transmitted data and the received data. In the above case, the transmission source CPU compares the transmitted data with the transmitted data. And a method of comparing received data read from the IC at the receiving end. However, there is a problem that it cannot be determined by the above-mentioned comparison whether the error of the output data has occurred at the stage of writing to the internal register or at the stage of reading from the internal register.

The present invention has been made in consideration of the above problems, and has been described in detail with reference to the accompanying drawings.
F is provided.

[0011]

The data set in the internal register is temporarily held in a latch circuit at the beginning of reading the internal data, and the data held in the latch circuit is read to link the shortage or excess of the read clock. By performing serial data reading and repeatedly reading according to the number of data in the internal register, 1
When the difference between the first read and the second or subsequent read data is detected and a difference is detected, it is determined that noise is mixed in the read clock.

For example, when the read clock is insufficient, in the first read and the second and subsequent read,
A data shift occurs before, and when the read clock is exceeded, a data shift occurs after.

Further, in the serial interface circuit of the present invention, a serial / parallel conversion circuit for converting input serial data into parallel data, an internal register in which the parallel converted data is written, and data written in the internal register are stored. A latch circuit for temporarily holding,
A parallel / serial conversion circuit that is connected to the latch circuit and repeatedly reads and outputs data held in the latch circuit.

According to the above configuration, since the register data is temporarily latched at the time of data reading, there is no difference between the first read data and the second and subsequent read data even if repeated reading is performed. Therefore, if there is no data error in the repeated reading, it is possible to detect that there is a data error at the time of writing.

[0015]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a circuit diagram of a serial interface circuit according to the present invention. The serial data input from the I / O port of the CPU is converted into parallel data by an S / P conversion circuit in a serial I / F unit of each functional IC.
For example, as shown in FIG. 1, the data is sent to a data bus having a bus width of 8 bytes. The upper 4 bits of the serial data are address data, and the following 8 bits are register setting data, each of which is transmitted from the MSB. The address converted into parallel data (4 bits) by the S / P conversion circuit is taken into an address latch circuit, decoded, and specifies a corresponding internal register. In the case of an internal register write operation, (R / W = “L”), and the specified S / P converted 8-bit data is input to the designated internal register. Will be retained.
The above series of operations is the write operation.

Next, a read operation will be described. The read operation indicates a mode in which R / W = "H" and / EN = "L". In a data read operation of the internal register, data read from the internal register is output to the latch circuit L based on a read permission signal generated from the timing generation circuit. The data held in the latch circuit L is subjected to P / S conversion and output as serial data.

Next, FIG. 2 shows a case where the number of serial clocks (SCLK) is insufficient or exceeds the number at the time of reading the internal register data. It should be noted that (d7, d6, d5, d4, d3, d2, d1,
It is assumed that normally written data d0) is stored.

FIG. 2A shows a case where the number of serial clocks (SCLK) is insufficient at the time of reading the internal register data. As shown in the figure, when the serial clock (SCLK) is not input at the timing corresponding to the d1 read at the time of reading the internal register data, the serial data output (Se
In (r-out), D0 is not output and data D1 continues for two clocks. That is, D1 is replaced and output at the original D0 output position, and the following serial output (Ser-out) is obtained.

(D7, d6, d5, d4, d3, d2
d1, d1) In order to repeatedly output this data string, an additional serial clock (SCLK) may be intentionally input. For example, if 8 clocks (= 8 data) are input as an additional clock, the following serial output (Ser-out) can be obtained.

(D0, d7, d6, d5, d4, d3
d2, d1) If this is compared with the previously read data in the CPU which is the data setting source, a difference in data can be detected.

Therefore, it can be seen that the data arrangement of the first data string is different from the data arrangement of the next data string, so that an abnormality of the serial clock has occurred at the time of reading. Further, in FIG. 2A, since the clock corresponding to the data D1 is lost as described above, the data is not read when D1 should be read, and the progress of the read data is stopped. It ends with D1. Therefore, in such a case, it can be determined that a missing (insufficient) serial clock has occurred during writing.

FIG. 2B shows a case where the number of serial clocks (SCLK) is exceeded at the time of reading the internal register data. As shown in the figure,
At the time of reading the internal register data, the serial clock (S
CLK) is input, D7 is output again at the serial data output (Ser-out) corresponding to this portion. That is, D7 is output again after the original output position of D0, and the following serial output (Ser-out) is obtained.

(D7, d6, d5, d4, d3, d2
d1, d0, d7) In order to repeatedly output this data string, a serial clock (SCLK) may be additionally input intentionally as in the case of SCLK shortage.

For example, as an additional clock, 8 clocks
(= 8 data), the following serial output (Ser-out) is obtained.

(D6, d5, d4, d3, d2, d1,
d0, d7) If this is compared with the previously read data in the CPU which is the data setting source, a difference in data can be detected.

As described above, since the CPU controlling each function-specific IC can determine whether data is correctly set in each function-specific IC, a reliable operation can be expected. Further, according to the above procedure, data can be continuously confirmed without step of reading data again, so that the redundant time required for resetting the EN and R / W control lines and address setting is reduced. Thus, the CPU can improve the efficiency of determining whether data is correctly set in each function-specific IC.

In addition to the above detection method, it is possible to detect the excess of SCLK at the time of reading the internal register by a simpler method. That is, one bit of F / F is prepared,
Serial output (Ser-ou) using SCLK as a clock
t) is updated as a data input, and this F / F output is
The serial output (Ser-
out), and if they do not match, it is possible to detect that SCLK due to noise has entered after d0 in the data string.

Next, the operation when a data error occurs due to an excess or deficiency of the clock at the time of writing will be described. FIG.
FIG. 4 is a timing chart showing how the data written to the internal register appears in Ser-out when the data written to the internal register is read when the clock is excessive or insufficient when writing data to the internal register in advance.

FIG. 3A shows the timing when data is read out when SCLK is insufficient when writing data in the internal register in advance, and FIG.
The timing when the data is read out when the SCLK exceeds the time when the LK writes the data to the internal register is shown.

In FIG. 3A, since SCLK was insufficient at the time of data writing (R / W = “L”), (a0, d7, d6, d5, d4, d) is stored in the internal register.
8, d2, d1) have already been written. This is the S / P-I / F data input terminal (S
DIN), the transfer order of the serial data to be received is in the order of the address and the data, and the MSB first. Since the clock is used as the clock for S / P conversion, the shortage of the clock causes the MSB of the internal register to shift. It is nothing but the least significant bit of the address.

As described above, (a0,
When the stored data d7, d6, d5, d4, d3, d2, d1) is read, (a0, d7, d6,
d5, d4, d3, d2, d1) are read out as they are and output to the Ser-out terminal. It looks as if the beginning of the read data is garbled and the end is missing.

In FIG. 3B, since the SCLK has previously exceeded the time of d0 writing at the time of data writing (R / W = “L”), (d6, d5, d
4, d3, d2, d1, d0, d0) have already been written. this is,
The transfer order of serial data to be received at the data input terminal (SDIN) of the S / P-I / F is in the order of address and data, and at the head of the MSB, and is used as a clock for S / P conversion. This is because the least significant bit of the address remains redundantly in the LSB of the internal register due to the clock excess.

Next, as described above, (d6,
When the stored data d5, d4, d3, d2, d1, d0, d0) is read, (d6, d5, d4,
d3, d2, d1, d0, d0) are read as they are and output to the Ser-out terminal. It looks as if the beginning of the read data is garbled and the end is duplicated. However, the above example shows only a small part of the phenomena that can actually occur. It is generally difficult to specify at what timing the shortage or excess of SCLK due to noise can occur in writing or reading.

Therefore, although it is possible in some cases to compare only the first or last data of the read data string and detect a data error during serial data transfer, the serial I / F circuit originally has 2 bits. Since the logic circuit is a value description logic circuit, it is almost impossible to detect when adjacent data is the same, such as "FFh" or "00h" in the originally set data string.

The above examples are "5Ah", "A
If a detection pattern such as 5h "is set, adjacent data in the first half of the data string and the second half of the data string are different, so that data error detection can be performed.

In addition to the above-described confirmation method in the serial I / F section, writing to an internal register (EN = “L”, W /
After R = “L”), W / R = “H” with EN = “L”, that is, it is also possible to immediately shift to data detection in the read mode. In this case, since the redundant time for shifting from the write mode to the read mode again can be further reduced, it is possible to check the setting data at higher speed. Here, the redundant time is as follows: write end processing (SCLK = “H”, EN = “H”) read start processing (SCLK = “H”, EN = “L”) read address setting (address 4 bits) Settings, SC
LK4 clock).

As described above, according to the embodiment of the present invention, Se
By examining the data sequence of r-out, it is possible to easily determine the cause of a data error that occurs in the process of setting / reading data from the CPU to each functional IC.

[0039]

According to the present invention, when an error occurs in S / P-converted data, it is possible to easily determine the cause of the data error by checking the arrangement of the serial data output data sequence. Become. Also, Ser-o
Since it is possible to reduce the redundant time required for the setting of the ut data reading, it contributes to the efficiency of data validity confirmation.

[Brief description of the drawings]

FIG. 1 shows a serial interface circuit according to a first embodiment of the present invention.

FIG. 2 is a timing chart showing how an abnormality of a serial clock at the time of data reading appears in Ser-out.

FIG. 3 is a timing chart showing how an abnormality of a serial clock at the time of writing data appears in Ser-out.

FIG. 4 shows a conventional serial interface circuit.

Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat II (reference) H03M 9/00 H03M 9/00 A F term (reference) 5B014 EA04 GC01 GE05 HA09 HB25 5B048 AA05 5B077 AA01 GG03 MM02 NN02 NN08 5B083 BB06 CC06 CC07 EE06

Claims (3)

[Claims] 1. A serial interface circuit having at least a serial / parallel conversion circuit and an internal register. As a result of reading and comparing data held in the internal register a plurality of times, the first data string read out and the data read out thereafter are read out. It is determined that a read data transfer error has occurred when the data sequence of the data sequence thus obtained is different, and when the occurrence of the data transfer error cannot be determined, the data is sent from outside the serial interface circuit to write to the serial interface circuit. Comparing the read data with the data read based on the data written to the internal register of the serial interface circuit, and determines that a data transfer error has occurred at the time of writing to the serial interface when at least a part of the data strings of the two are different. Is characterized by The method of testing Le interface circuit. 2. The method according to claim 1, wherein the data held in the internal register is temporarily held in a latch circuit, and the data is read from the latch circuit a plurality of times. 3. A serial / parallel conversion circuit that converts input serial data into parallel data, an internal register into which the parallel-converted data is written, a latch circuit that temporarily holds data written into the internal register, It is connected to a latch circuit and repeatedly reads the data held in the latch circuit, and checks the arrangement of one or more data strings to determine whether a data error has occurred at the time of writing or at the time of reading. A serial interface circuit, comprising: a determination unit capable of determining.