JP2001350673A - Flash memory access control method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To read/write-access an optional block on a flash memory in a state where the number of writing times and an alternate block address are managed. SOLUTION: Whether an access object block address is registered on a management data region 403 or not, is confirmed prior to read/write access. If it is not registered, access is gained to an access object block on a data region 401. If it is registered, a block address registered as the counterpart of the access object block address is used as the alternate block address, and the alternate block on the preliminary region 403 is made to be accessed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory in which the number of times of writing is limited, that is, a memory such as a flash memory or an EEPROM (hereinafter simply referred to as a flash memory) when reading / writing. The present invention relates to a flash memory access control method.

[0002]

2. Description of the Related Art The flash memory itself has an advantage that even if its operating power supply is cut off, the stored contents up to that point are maintained as it is. Therefore, the flash memory is a nonvolatile memory, The fact is that it has been widely used so far. However, when a read access is made to the flash memory, a memory area (hereinafter, referred to as a physical access unit) on the flash memory is used even if no problem occurs.
Each of these memory areas is simply referred to as a block.) Each of them has a limit on the number of times of writing. Therefore, in principle, a limit value on the number of times of writing is preset, and the number of times of writing to the same block is set in advance. A method in which the flash memory is accessed for writing within a range not exceeding the limit value is adopted. If the number of times of writing to a certain block exceeds the limit value, as shown in JP-A-6-36579, instead of the block used so far, for example, the same flash memory is used. An empty block separately prepared in advance is used as a substitute block thereafter.

Here, a specific example of a conventional memory access system will be described with reference to FIG.
201 includes a plurality of flash memories FM via a common bus.
In a state where 1 to FMn are accommodated and connected, an arbitrary block on an arbitrary flash memory can be read / written by the CPU 1201. In each of the flash memories FM1 to FMn, the memory area is divided for each predetermined address range, and the divided memory areas are arbitrarily and simultaneously read / write accessible. Each memory area is defined as the above-described block.

On the RAM 1202, which is always backed up by the battery 1203, the block correspondence management data is stored as updatable so that each block in the flash memories FM1 to FMn is file-managed. ing. Thus, for example, if the power of the entire system is intentionally turned off,
Prior to the disconnection, the contents stored in the RAM 1202 are saved and saved in a predetermined area on an arbitrary flash memory as the latest state. When the system is restarted by turning on the power thereafter, the saved contents are saved up to that time. The contents stored in the RAM 1202 can be transferred and stored. Even if the power of the entire system is unintentionally turned off due to a power failure or the like, the RAM 1202
It is always backed up by the battery 1203,
Since the management data as stored contents will not be lost,
In particular, no problem occurs.

Generally, an arbitrary block on the flash memories FM1 to FMn can be read / written by the CPU 1201. Here, for example, a block on the flash memory FM1 (shown by oblique lines)
A block 1204 is set as an access target of the block 1204.
When it is determined from the management data corresponding to the block 1204 that the accumulated value of the number of times of writing has reached the limit value, the free space separately secured on the same flash memory FM1 is substituted for the block 1204. Block 1205 is set as a substitute block thereafter. Depending on the block correspondence management data in the RAM 1202, the number of times of writing to the block, the presence / absence of a replacement block for the block, and the replacement block address when there is a replacement block are managed.

Here, a general operation at the time of read / write access to the flash memory will be described in detail. Generally, in a flash memory, a plurality of continuous memory addresses are collectively accessed as one block. Therefore, when it is necessary to read only data for a specific memory address from the flash memory, the specific memory address is temporarily converted into a block address, and then the flash memory is read and accessed. By this access, data on the block address, that is, data corresponding to a plurality of memory addresses is read out from the flash memory at a time. From among the data corresponding to the plurality of memory addresses, a specific memory address is read out. It is sufficient that only data corresponding to is selected. In addition, when it is necessary to write data only to a specific memory address on the flash memory or to update only data on the specific memory address, the specific memory address is once converted to a block address. Above, first, the flash memory is accessed for reading. With this access, data on the block address, that is, data corresponding to a plurality of memory addresses, is read out from the flash memory at a time and temporarily saved. Thereafter, the data on the block address is collectively erased, and the saved data is collectively written on the block address in a state where only the data corresponding to the specific memory address is updated with the write data. Is what it is.

[0007]

However, in the case of Japanese Patent Laid-Open No. 6-36579, the power supply to the entire system is unintentionally cut off, and it is assumed that the management data may be lost. The management RAM needs to be always supplied with power by a battery. In other words, a battery is specially required only for the block management RAM, which makes it difficult to reduce the size and cost of the entire system.

A first object of the present invention is to provide a block management R
An object of the present invention is to provide a flash memory access control method in which an arbitrary block in each of one or more flash memories can be write-accessed in a state where AM is not required and the number of times of writing to each block is managed.

A second object of the present invention is that, in addition to the first object, even when the cumulative value of the number of times of writing to a certain block reaches the limit value, an alternative block is secured for that block. In addition, the purpose of the present invention is to provide a flash memory access control method in which write access can be continuously performed to the substitute block.

A third object of the present invention is to provide a flash memory access control in which an arbitrary block can be read / written while a replacement block is secured in a flash memory and the number of writes and a replacement block address are managed. There is a way to provide.

[0011] A fourth object of the present invention is to provide a read / write access to a substitute block even if an abnormality occurs in any of the management data areas due to some factor. The purpose of the present invention is to provide a flash memory access control method in which read / write access can be continuously performed to each of the alternative blocks by using a simple management data area.

[0012]

The first object of the present invention is that, each time a block is accessed for writing, the number of times of writing, which is read from the block prior to the access and stored as a pair with data, is determined in advance. As long as the number does not exceed the set limit value, the number of times of writing is achieved by being written on the block together with the write data as an updated state.

[0013] The second object is that each time each block is accessed for writing, the number of writes stored as a pair with data, which is read from the block prior to the access, exceeds a preset limit value. Unless the number of times of writing is updated on the block together with the write data as the updated number of times, if the number exceeds the preset limit value, thereafter, from the spare area on the same flash memory, This is achieved by using the selected free block as a substitute block and writing the write data on the substitute block.

A third object of the present invention is that each time a block is accessed for writing / reading, an alternative block address for the block is registered in a management data area on the same flash memory prior to the access. If it is determined that the replacement block address is not registered, the block is read / write-accessed as it is, while if the replacement block address is registered, the block is replaced with the replacement block address. This is achieved by performing read / write access to a designated alternative block on the spare area.

Still further, the fourth object is that each time each block is accessed for writing / reading, at least any one of the management data areas whose registration contents are normal on the same flash memory prior to the access. It is determined whether or not an alternative block address is registered for the block. If the alternative block address is not registered, the block is read / write accessed as it is while the alternative block address is registered. If it has been read / read from / to the replacement block on the spare area specified by the replacement block address,
This is achieved by performing a write access.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to FIG.
11 will be described with reference to FIG. First, a processor system according to the present invention will be described. FIG. 1 shows a system configuration in one example. As shown, various input / output functions are accommodated and connected to a microprocessor (MPU) 101 via a processor bus 107. That is, the memory 105 via the memory controller 102 and the memory bus 108, the flash memory unit 106 via the flash memory controller 103 and the flash memory bus 109, and the like.
The input / output device group 110 is accommodated and connected via the I / O interface unit 104. In general, the flash memory unit 106 includes a plurality of flash memories FM1 to FMn, and functions as an external storage device that stores various programs and the like. When communication is performed between various input / output functions via the processor bus 107, the status of the communication result is displayed from the communication destination to the communication source after completion of the communication. It is.

In the MPU 101, when there is a processor bus use request from each of the various input / output functions, the processor bus use permission is selectively issued to those bus use request sources under the preset priority control. It has become something. In addition to the MPU 101, the memory 105 can be accessed from the flash memory controller 103 and the input / output device group 110 at any time.
In the MPU 101, when there is a memory access request to the memory 105, the highest priority access request source is determined under the prioritized priority control, and a memory access permission signal indicating the highest priority access request source is sent to the signal line. The memory use permission signal is transferred to only the highest priority access request source from the memory controller 102 via the memory controller 102. Indicates that the memory 105 has read / write access enabled. At the time of these accesses, data is read from the access address on the memory 105 under the control of the memory controller 102 based on the read / write mode signal from the processor bus 107, the access address, and the write data (only in the case of write access). Or write data is being written to the access address. Further, the flash memory unit 106 has the MPU1
01, read / write access is permitted. However, as described below, when those accesses are performed,
The read / write data is once written on the memory 105, and the read / write access is performed with the memory 105 interposed.

Now, among the above processor systems,
The flash memory controller 103 is directly related to the present invention, and FIG. 2 shows an internal configuration of one example. As shown in the figure, the flash memory controller control information from the processor bus 107 is held in the controller control unit 201. First, the controller control unit 201 will be described.
01, five types of control registers 0 to 4 are prepared.

That is, FIG. 3A shows the format of the control register 0. The control register 0 includes an ST field 301 and a CMD field 3
02 and EXE bit 303. Of these, the ST field 301 is for displaying the command execution result in the flash memory controller 103, and the command execution result is obtained by referring to this field after the command execution. The CMD field 302 is a field in which a command for giving an operation instruction to the flash memory controller 103 is written. If execution is instructed from the EXE bit 303, the flash memory controller 103 uses the command content written in this field to write the command. It works.

FIG. 3B shows the format of the control register 1, and the control register 1 is provided on any one of the flash memories FM 1 to FMn in the flash memory unit 106. The TNO field 304 indicates the access destination flash memory number, and the BAD field 3
In 05, an access destination block address is written.

FIG. 3C shows the format of the control register 2. As shown in FIG.
It consists only of the ADR field. The control register 2 is a flash memory unit 10
6, when read access is performed, to which memory address on the memory 105 the read data is to be written, and when write access is performed, the write data is stored in any memory address on the memory 105. MADR to indicate if it has been written to
These memory addresses are written on the field.

FIG. 3D shows a format of the control register 3, which is composed of only the LIMIT field as shown. In the LIMIT field, a limit value on the number of times of writing for each block (including the substitute block) is preset, and when each block is accessed for writing, the limit value for that block is set. The write access is controlled so that the accumulated value of the number of writings up to the above does not exceed the limit value.

The control register 4 shown in FIG.
In addition, a flash memory that requires a chip replacement is displayed due to occurrence of some failure (including a case where a substitute block cannot be secured from the spare area) in the flash memories FM1 to FMn. It has become something. Which flash memory needs to be replaced can be easily grasped by referring to this register.

Returning to FIG. 2 again and continuing the description of the other components in the flash memory controller 103, if the control register 0 (FIG.
(See (A)), the type and the like of the CMD field content (command content) are decoded by the command determination unit 202, and the flash memory control signal is sent from the flash memory control unit 203 according to the decoded content. While being output to the flash memory unit 106 via the bus 109, the flash memory unit 1
Status from the flash memory bus 1
The data is transferred to the controller control unit 201 after being captured by the flash memory control unit 203 via the controller 09. The processor bus / flash memory bus input / output data control unit 204 also temporarily stores read data on the processor bus 107 and stores the read data in the flash memory unit 10.
6, temporary storage of write data and control of output destination,
The output of the flash memory control data and the output of the contents of the internal control register to the processor bus 107 are controlled.

Now, referring to FIG.
To explain the memory map in each of the data area 401 to FMn, as shown in FIG.
Spare area 4 to be used as a substitute block when a defective block occurs in the number of write operations on 01
02 and a management data area 403 for managing the block addresses of the defective block and the substitute block in a corresponding relationship when the substitute block is actually used in accordance with the occurrence of the defective block. Has become. However, as the management data area 403,
It is desirable to be configured as two or more regions. This is because when the management data contents in each of the two or more management data areas are to be always the same,
Even if one of the management data areas becomes abnormal for some reason, the block address management for each of the defective block and the replacement block can be performed using the management data on the remaining normal management data area. is there.

As described above, the flash memories FM1 to FM1
In each FMn, a memory area is divided for each predetermined address range, and each of the divided memory areas is arbitrarily set.
At the same time, read / write access is permitted. Each memory area thus partitioned is defined as a block and managed by a block address. In the example of the memory map shown in FIG. 5, the block address space 501 as a whole is 1 to 2
144, the flash memories FM1 to FM1
It shows a specific example of a memory map for each FMn. In this case, 20 is stored in the data area 401.
48 blocks (block addresses 1 to 2048), 48 blocks (block addresses 2049 to 2096) in the spare area 402, and 48 blocks (block addresses 2097 to 2120, 2121) in each of the two management data areas 403. To 2144) are assigned. Since the block capacity of the spare area 402 is set to 48 blocks, the occurrence of defective blocks up to a total of 48 blocks in the data area 401 is allowed, and the defective blocks of a total of 49 blocks are allowed. If this occurs,
When it is determined that the flash memory is defective, the corresponding bit in the above-described control register 4 (see FIG. 3E) is set to, for example, “0”. It is indicated that it is necessary.

Here, the format on the data area 401 will be described. As shown in FIG. 6, the data area 401 is composed of a data field 601 and a write count field 602.
01, the original data itself is stored, and in the write count field 602, the write count so far is stored as a pair. For example, (3518) H (H indicates that the number is in hexadecimal) is stored as data in the data field on the block address 44, and (455) H is stored as the number of writes in the number-of-writes field. However, from the write count (455) H, the block address 4
4 on that, 1109 (= 16 ² × 4 + 16
It is known that data writing is performed ¹ × 5 + 16 ⁰ × 5) times. The format on the spare area 402 is the same as that on the data area 401.

FIG. 7 also shows block addresses 727 and 8
13, the blocks at the block addresses 2049 and 2050 are set as the replacement blocks, and the replacement blocks are set to (881) H and (865) H times, respectively. This shows the state in which data or landing has been performed. Therefore, on the two management data areas 403,
The block at block address 727 is replaced by that at block address 2049, and the block at block address 813 is replaced by block address 2050.
It is managed to be replaced by it. Therefore, prior to the read / write access, it is checked whether or not the access target block address is registered in the management data area 403. If the address is not registered, the access target block is accessed as it is, but it is registered. Then, the block at the block address registered as a pair with the access target block address is regarded as a substitute block, and the substitute block may be accessed.

Finally, the read / write access operation will be described. First, regarding read access, read access is performed according to the procedure shown in FIG. That is, first, a flash memory (chip) number and a (physical) block address to be read (read) are written (written) from the MPU 101 to the control register 1 (ST1). Thereafter, a memory address on the memory 105 as a transfer destination of the read data as a read result is written in the control register 2 (ST2). Further, a read command and an EXE bit (start instruction bit) "1" are written in the control register 0 (ST3). Then, after reading the control register 0, the state of the EXE bit is determined (ST4). If,
If the EXE bit is "1", the process returns to ST4.
If the XE bit is "0", the ST field on the control register 0 is to be referred to (ST5).

FIG. 9 also shows ST3 to ST
The operation flow in the flash memory controller 103 up to 5 is shown. In this case, first, based on the number of the flash memory (chip) to be read, a management data area in the flash memory is referred to (ST6), and it is determined whether or not a block address to be read is registered. (ST7). If registered, the substitute block address is obtained from the management data area (ST
8) If the data is not registered, the data is read by the read block address as it is (ST9). Thereafter, after accessing the memory controller 102 and acquiring the bus right of the processor bus 107 (ST10), the memory 10 designated in ST2 is accessed.
5, a write request for read data is made to the transfer destination memory address on ST5 (ST11).
Thereafter, the process waits for a status return from the memory controller 102 (ST12), the status is set in the ST field 301 of the control register 0, and the EXE bit is first cleared to "0". (ST13).

On the other hand, write access is performed according to the procedure shown in FIG. That is, first, MPU1
01 through the memory controller 102 to the memory 10
5, the write data to the flash memory is written (ST14), and then the flash memory (chip) number and the (physical) block address to be written are written (written) to the control register 1 (S).
T15). After that, S is stored in the control register 2.
The memory address on the memory 105 to which writing has been performed at T14 is set (ST16). Further, a write command and an EXE bit (start instruction bit) "1" are written on the control register 0 (ST17). After that, after reading the control register 0, the state of the EXE bit is determined (ST18). If E
If the XE bit is "1", the process returns to ST18.
If the XE bit is "0", the ST field on the control register 0 is referred to (ST19).

FIG. 11 also shows the flash memory controller 10 between ST17 and ST19.
3 shows the operation flow. In this case, first, after accessing the memory 105, ST14
Is obtained (ST2).
0). Thereafter, the number of times of writing is read from the block address specified in ST15, but the number of times of writing is updated by +1 and written back to the same block address (ST21). Further, the +1 updated write count a is compared with the limit value b on the write count in the control register 3 (ST22). If a = b, an empty block is found in the spare area. It is determined whether or not there is (ST23),
If there is a vacant block, the access target block address is determined to be a bad block, and replacement processing (writing of write data to a substitute block or writing of a block address to the management data area) is performed using the vacant block as a substitute block. (Writing process) (ST26). If there is no free block in the spare area, the flash memory to be accessed needs to be replaced, so that an indication is given on the control register 4 (ST24), and the write access processing ends. Is what is being done. On the other hand, if it is determined in step ST22 that a ≠ b and there is still room for the number of times of writing, the write data is written as it is to the write target block address (ST25). When the writing of the write data to the write target block or the substitute block is completed, the ST field on the control register 0 is set and the EXE bit is first cleared to "0" (ST27).

In the above description, it is not assumed that a substitute block has not yet been set for the access target block address. However, in general, it is determined whether or not a substitute block has been set. It is sufficient that data or write processing is performed on the access target block or the replacement block after confirmation at the initial stage.Although it seems that it is rare, the number of times of writing on the replacement block is less than the limit value b. If it has reached, it is conceivable to set a new alternative block for the alternative block. In any case, when the flash memory access control method according to the present invention is adopted, a flash memory such as a digital camera is used in addition to a computer system because a system can be constructed with a minimum configuration. It is applicable to the system.

[0034]

As described above, according to the first embodiment, the block management RAM is not required, and the number of times of writing to each block is controlled, and the number of blocks is reduced to one.
Any block in each of the above-mentioned flash memories can be accessed for writing. In addition, in the case of claim 2, in addition to such an effect, even when the cumulative value of the number of times of writing to a certain block reaches the limit value, After the replacement block is secured for the block, the write access can be subsequently performed to the replacement block. Further, according to the third aspect, the replacement block is secured on the flash memory and the write access is performed. In a state where the number of times and the substitute block address are managed, an arbitrary block can be read / write-accessed. Further, in the case of the fourth aspect, when the read / write access is performed to the substitute block, the read / write access may be performed for some reason. Even if an error occurs in any management data area, the remaining normal management It has become one read / write access can be made for continued replacement block each by chromatography data area.

[Brief description of the drawings]

FIG. 1 is a diagram showing a system configuration of an example of a processor system according to the present invention;

FIG. 2 is a diagram showing a configuration of an example of a flash memory controller according to the present invention;

FIGS. 3A to 3E are diagrams for explaining formats and functions of various control registers prepared in a flash memory controller; FIGS.

FIG. 4 is a diagram showing a memory map in each flash memory;

FIG. 5 is a diagram showing a specific example of a memory map;

FIG. 6 is a diagram showing a format on a data area;

FIG. 7 is a diagram for explaining what management data is set in a management data area when a replacement block is set in a spare area due to occurrence of a bad block in a data area; Illustration

FIG. 8 is a diagram showing a flow at the time of read access (part 1);

FIG. 9 is a diagram showing an operation flow in the flash memory controller (part 2);

FIG. 10 is a diagram showing a flow at the time of write access (part 1);

FIG. 11 is a diagram showing an operation flow in the flash memory controller (part 2);

FIG. 12 is a diagram showing a specific example of a memory access system according to the related art;

[Explanation of symbols]

101: microprocessor, 102: memory controller, 103: flash memory controller, 105
.., Memory, 106, flash memory unit, 107, processor bus, 401, data area, 402, spare area,
403: management data area, FM1 to FMn: flash memory

 ────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor Yuichi Higuchi 216 Totsukacho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture F-term in Hitachi, Ltd. Communications Division 5B018 GA04 KA18 MA23 NA06 5B025 AD01 AD04 AD05 AE01 AE08 5B082 DE00 JA06

Claims (4)

[Claims] 1. A flash memory access control method when an arbitrary block in each of one or more flash memories is write-accessed, wherein each time a block is write-accessed, the block is read from the block prior to the access. As long as the number of write operations to be read and stored as a pair with data does not exceed the preset limit value, the flash memory is configured to be written on the block together with the write data in an updated state of the number of write operations. Access control method. 2. A flash memory access control method when an arbitrary block in a data area in each of one or more flash memories is write-accessed in a state where a data area and a spare area are secured on the flash memory. Each time a block is written and accessed, as long as the number of writes stored as a pair with data that is read from the block prior to the access does not exceed a preset limit value, Is written on the block together with the write data as an updated state, while if the preset limit value is exceeded, a vacant block selected from the spare area on the same flash memory is used as a substitute block thereafter. So that write data is written on the replacement block. Flash memory access control method. 3. In a state where a data area, a spare area, and a management data area are secured on each flash memory,
If the number of times of writing to the same block in the data area exceeds the preset limit value, a vacant block selected from the spare area on the same flash memory is set as a substitute block, and thereafter, the read to the substitute block is performed. This is a flash memory access control method in which an arbitrary block on a data area in each of one or more flash memories is read / written assuming that the write / write access is performed. Before each access, it is determined whether or not an alternative block address for the block is registered in the management data area on the same flash memory, and if the alternative block address is not registered, Block is read / write accessed as is That one, if the surrogate replacement block address is registered is specified in the surrogate replacement block address, reading to alternate blocks on the spare area /
A flash memory access control method in which write access is performed. 4. In a state where a data area, a spare area, and two or more management data areas having the same registered contents are secured on each flash memory, the number of times of writing to the same block in the data area is determined in advance. If the set limit value is exceeded, a free block selected from the spare area on the same flash memory
A flash memory access control method when an arbitrary block in a data area in each of one or more flash memories is read / written assuming that read / write access is performed to the substitute block, wherein each block is Each time a write / read access is made, it is determined whether or not an alternative block address for the block is registered in at least one of the management data areas on the same flash memory where the registered contents are normal prior to the access. In addition, if the replacement block address is not registered, the block is read / write accessed as it is, while if the replacement block address is registered, the block is designated by the replacement block address. Read the replacement block on the spare area Flash memory access control method so that the teeth / write access is performed.