JP2001350620A - Display control device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the data transmission quantity between a display control device and a host computer. SOLUTION: The area of a display RAM 11 is partitioned into a display area 11a and a component area 11b. A bit map data having a high display frequency is preliminarily written in the component area 11b, and the data of the component area 11b is transferred to and displayed on the display area 11a.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display control device for sending display data in a bitmap format to a display.

[0002]

2. Description of the Related Art FIG. 2 shows a schematic configuration of a conventional bit map type display control device 50. As shown in FIG. In FIG. 2, the display RA
When displaying the bit map format display data written in M51 on the liquid crystal display 30, the display read control circuit 52 controls the line address decoder 54 in synchronization with the display clock generated by the timing generation circuit 53. Then, data of a specific line (data equal to the column size) is read out, latched by the display latch circuit 55, sent to the display drive circuit 56, and displayed on the liquid crystal display 30. The addresses of the lines read out from the display RAM 51 are sequentially updated from the head line to the tail line.

When writing bitmap data into the display RAM 51, the row write control circuit 57 controls the row address decoder 58 and the column write control circuit 5
9 controls the column address decoder 60 to write the display data sent from the host computer (not shown) via the host interface 40.

At the time of writing, when a row address is designated by the row write control circuit 57 and the row address decoder 58, the address is designated by a page concept in which a plurality of bits (for example, 8 bits) are treated as one page. There is also.

At the time of writing, a start address specified by the row write control circuit 57 and the column write control circuit 59 is initialized by the host computer, and the address register is incremented by +1 in a bus cycle, and the non-existing address is set. Is counted and not incremented.

Access (write) from the host computer to the display RAM 51 and output (read) from the display RAM 51 to the display latch circuit 55 are controlled to operate independently. The instruction decoder 61 decodes instructions from a host computer and controls the internal state of the display control device 50. 62 is an internal bus.

As described above, when the address of the display RAM 51 is designated by the host computer, the conventional display control device 50 writes the bitmap data while incrementing automatically from the designated position. The contents of the display RAM 51 are sent to the liquid crystal display 30 and displayed. When only a specific area of the liquid crystal display 30 is to be displayed and inverted as in a menu screen, an operation such as newly rewriting data in the area of the display RAM 51 or inverting data by the display latch circuit 55 is performed. ing.

[0008]

However, display RAMs
In the change of the screen display accompanied by the change of the data written in 51, even if the display content of a certain data area is frequently used, if the display content does not exist in the current display RAM 51, the display position is inappropriate. In some cases, or when inversion or non-inversion is inappropriate, it must always be rewritten by the host computer via the host interface 40.

For this reason, the amount of data transfer between the host computer and the display control device 50 during normal operation increases,
There is a problem in that the time required for data transfer increases in proportion thereto, and the current consumption by the interface increases.

An object of the present invention is to provide a display control device which can reduce the amount of data transfer to and from a host computer and solves the above-mentioned problem.

[0011]

According to a first aspect of the present invention, there is provided a display RAM in which bitmap data is written, and a first RAM in which data written in the display RAM is read and latched by a display latch circuit. And a write control circuit for writing data sent from the host computer to the display RAM, wherein a second read control circuit for reading data from the display RAM and a copy control circuit are provided. The copy control circuit writes data in a specific area of the display RAM read by the second read control circuit to another specific area of the display RAM specified by the write control circuit. did.

In a second aspect based on the first aspect, the copy control circuit performs the writing after processing the read data.

In a third aspect based on the first or second aspect, the first read control circuit includes a register for designating a read end position of the display RAM.

In a fourth aspect based on the first, second or third aspect, the write control circuit includes a register for designating a write start position and a register for designating a write end position of the display RAM. Wherein the second read control circuit comprises:
The display RAM includes a register for designating a read start position and a register for designating a read end position.

According to a fifth aspect of the present invention, the first, second, third or fourth aspect is provided.
In the invention, the display RAM area is divided into a display area in which writing by the write control circuit and reading by the first or second read control circuit are possible, and a writing area by the write control circuit and the second area. The read control circuit is divided into component areas that can be read, and data read and write by the copy control circuit are performed between the display area and the component area or in the display area.

[0016]

FIG. 1 is a block diagram of a display control device 10 according to an embodiment of the present invention. A display RAM 11 is provided with a line address decoder 12 for display reading and a row address decoder 13 and a column address decoder 14 for writing / reading.

The line address decoder 12 is controlled by a display read control circuit (first read control circuit) 15 including a display line control circuit (register and counter) 151 and a display line end address register 152.

The row address decoder 13 comprises a row address control circuit (register and counter) 161, a row start address register 162, a row end address register 163, a row write control circuit 16, and a row address control circuit (register and counter). 171, a row start address register 172, and a row read control circuit (second read control circuit) 17 comprising a row end address register 173.

The column address decoder 14 includes a column write control circuit 18 including a column address control circuit (register and counter) 181, a column start address register 182, and a column end address register 183.
Column address control circuit (register and counter) 19
1, a column read control circuit (second read control circuit) 19 comprising a column start address register 192 and a column end address register 193.

Reference numeral 20 denotes a display latch circuit, which temporarily latches data on the line designated by the line address decoder 12 and sends the data to the display drive control circuit 21.

Reference numeral 22 denotes a copy control circuit, which supplies a bus cycle to the write / read control circuits 16 to 19 in response to commands such as copy and move transmitted from the host computer via the host interface 40 to perform read and write operations. Writing (copying and the like) is performed simultaneously, and the execution is stopped by receiving a flag notifying that a predetermined address has been reached. An instruction decoder 23 decodes instructions transmitted from the host computer, and sets and controls the state of each register and each control circuit. Reference numeral 24 denotes a timing generation circuit for supplying a timing signal to the inside, and reference numeral 25 denotes an internal bus.

In this embodiment, the area of the display RAM 11 is divided into two partitions of a display area 11a and a component area 11b by a display line end address register 152 for use. That is, the liquid crystal display 30
The bitmap data displayed with is the first line (row)
From the display area 11a partitioned by a predetermined line (row) designated by the display line end address register 152
And the remaining area, ie, the component area 1
In 1b, frequently used bitmap data is written.

Display operation: The display of the bitmap data written in the display area 11a is performed as follows. The display line control circuit 151 controls the timing generation circuit 24 from the top line to the end line of the display area 11a.
Are sequentially specified in synchronization with the display clock generated in step (1), the contents are decoded by the line address decoder 12, and the actual lines are sequentially specified, and the display data of each of the specified lines is sequentially read out and read one line. Each time it is latched by the display latch circuit 20 and displayed on the liquid crystal display 30 by the display drive control circuit 21. This display operation is performed independently of the write / read operation by the address control circuits 16 to 19 described later.

Write operation: A normal write operation is performed as follows. The data on the data bus is displayed on the display R designated by the row address decoder 13 and the column address decoder 14.
Writing is performed at a predetermined position (display area 11a or component area 11b) of AM 11 in a write cycle. The start address to the start address registers 162 and 182 and the end address to the end address registers 163 and 183 can be rewritten by instructions from the host computer.

At the start of writing, a predetermined start address is set or initialized in the start address registers 162 and 182, and the column address is incremented by +1 in a bus cycle. When the column address reaches the column end address, the column address returns to the column start address at the next increment timing, and the row address is incremented by +1. When the row address reaches the row end address, it returns to the row start address at the next increment timing. However, if the end addresses of the row and column are equal to or larger than the row and column sizes, respectively, the address is returned to 0 instead of the start address.

In this writing, if only a predetermined start address is set in the write start address registers 162 and 182, the register 162
Since the start address 182 is used as a starting point to continuously update the address in a write cycle, the bitmap data sent from the host computer is stored in the display RAM 11 in order from the start address (row, column).
Are written to a continuous area (referred to as a linear area).

On the other hand, the start address register 16
When the end address within the size of the row and column is set in the write end address registers 163 and 183 together with the start address set in the write address 2 and 182, the bitmap data is stored in the start address (row and row).
The data is written in a rectangular area (called a rectangular area) that can be formed by a column) and an end address (row, column).

Read operation: A normal read operation is performed as follows. The data at a predetermined position (display area 11a or component area 11b) of the display RAM 11 designated by the row address decoder 13 and the column address decoder 14 is read in a read cycle. The start address to the start address registers 172 and 192 and the end address to the end address registers 173 and 193 can be rewritten by instructions from the host computer.

At the start of reading, a predetermined start address is set or initialized in the start address registers 172 and 192, and the column address is incremented by +1 in a bus cycle. When the column address reaches the column end address, the column address returns to the column start address at the next increment timing, and the row address is incremented by +1. When the row address reaches the row end address, it returns to the row start address at the next increment timing. However, if the end addresses of the row and column are equal to or larger than the row and column sizes, respectively, the address is returned to 0 instead of the start address.

In this read operation, when only a predetermined start address is set in the read start address registers 172 and 192, the register 17 is used.
2 and 192 continuously update the address in a read cycle starting from the start address. Therefore, in response to a read request from the host computer, data in a continuous area of the display RAM 11 is sequentially arranged from the start address (row, column). Is read.

On the other hand, the start address register 17
2 and 192, the end addresses within the row and column sizes are set in the read end address registers 173 and 193, respectively, when the start address (row and column) and the end address (row and column) are set. Column) Reads out data in a square area that can be made.

Copy operation: The copy operation is performed as follows. The copy control circuit 22 sets the start address for writing indicating the copy destination in the start address register 1.
62, 182, the end address is set in the end address registers 163, 183, the start address for reading indicating the copy source is set in the start address registers 172, 192, and the end address is set in the end address registers 173, 183. Set to 193. As a result, the bitmap data of the copy source area (the linear area or the square area of the display area 11a or the component area 11b) is copied to the copy destination as the linear area or the square area. This copy operation stops when both the row address and the column address reach the end address, and the copy control circuit 22 receives the end flag.

In this data transfer by copying, in addition to transferring the data as it is, it performs inversion, or processing such as logical sum, logical multiplication, and exclusive logical sum with other data previously written in a predetermined register. In other words, data can be processed and transferred.

As described above, when the write area and the read area are designated by the instruction and the start of the address movement is instructed, the display area 11a and the component area 11b in the display RAM 11 are connected between the display RAM 11 and the host computer. During or during the display area 11a, the bitmap data can be copied. At this time, the data read as described above can be processed and copied.

Therefore, if frequently used bitmap data is written in the component area 11b of the display RAM 11 in advance, it is possible to copy the bitmap data to the display area 11a of the display RAM 11 only by performing address management by the host computer. At this time, if the copy data is processed, highlighting, imposition of another screen, and the like can be realized.

Since the component area 11b can access a linear area having continuous addresses, the bitmap data can be stored in the display RAM 11 without generating a useless area. Shape can be different).

Further, the display area 11 of the display RAM 11 has already been set.
a to the same display area 11a
You can copy it to another location in the
It can also be temporarily evacuated to b.

In the current situation where the miniaturization / lower voltage of CMOS semiconductors is progressing, the circuit speed is higher / higher integration, and the power consumption per gate unit is decreasing, data is generally generated by an interface between devices having large power consumption. As compared with the transfer, the data transfer in the device has low power consumption and is fast.

Therefore, by performing display control using the above functions, the amount of data transfer between the host computer and the display control device is reduced, and the time and power consumption required for it can be reduced.

When a row address is designated by the write control circuit 16 or the read control circuit 17, a plurality of bits (for example, 8 bits) may be designated as one page, and the address may be designated in a page concept. Good.

[0041]

As described above, according to the display control device of the present invention, there is an advantage that the amount of data transferred to and from the host computer can be reduced, and the time and power consumption required for the transfer can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram of a display control device of the present invention.

FIG. 2 is a block diagram of a conventional display control device.

[Explanation of symbols]

10: display control device 11: display RAM, 11a: display area, 11b: component area, 12: line address decoder 13, row address decoder 14, column address decoder 15, display read control circuit (first read control circuit), Fifteen
1: display line control circuit, 152: display line end address register 16: row write control circuit, 161: row address control circuit, 162: row start address register, 163:
Row end address register 17: row read control circuit (second read control circuit), 17
1: Row address control circuit, 172: Row start address register, 173: Row end address register 18: Column write control circuit, 181: Column address control circuit, 182: Column start address register, 1
83: column end address register 19: column read control circuit (second read control circuit), 1
91: Row address control circuit, 192: Row start address register, 193: Row end address register 20: Display latch circuit 21: Display drive circuit 22: Copy control circuit 23: Instruction decoder 24: Timing generation circuit 30: Liquid crystal display 40 : Host interface

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) G09G 5/00 550 G09G 5/00 550M 5/39 5/36 530D F-term (Reference) 2H093 NC16 NC26 NC28 NC50 ND39 5B069 AA01 BA04 BB16 BC02 CA13 LA13 5C006 AA11 AC21 AF02 AF03 AF04 AF05 AF12 AF44 BB11 BC16 BF02 FA12 5C080 AA10 BB05 DD08 EE17 EE26 FF09 GG02 GG12 JJ02 5C082 AA01 BA02 DA12 BB15 DA22 DA15

Claims (5)

[Claims] 1. A display R on which bitmap data is written.
AM, a first read control circuit for reading data written in the display RAM, and causing a display latch circuit to latch the read data,
A display control device comprising: a write control circuit that writes data sent from a host computer to the display RAM; and a second read control circuit that reads data from the display RAM; and a copy control circuit. A circuit writes data in a specific area of the display RAM read by the second read control circuit to another specific area of the display RAM specified by the write control circuit. Display control circuit. 2. The display control circuit according to claim 1, wherein the copy control circuit performs the writing after processing the read data. 3. The display control circuit according to claim 1, wherein the first read control circuit includes a register for designating a read end position of the display RAM. 4. The write control circuit according to claim 1, wherein the write control circuit includes a register for specifying a write start position and a register for specifying a write end position of the display RAM. A display control circuit comprising: a register for designating a read start position and a register for designating a read end position of the display RAM. 5. The display RAM according to claim 1, wherein the display RAM area is a display area in which writing by the write control circuit and reading by the first or second read control circuit are possible. Partitioning into a component area where writing by the write control circuit and reading by the second read control circuit is possible, and reading and writing of data by the copy control circuit between the display area and the component area, or A display control circuit, wherein the display control is performed in a display area.