JP2001350440A - Display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize a display device capable of enhancing luminance and also capable of increasing the number of gradation by enhancing the setting speed of gradation data. SOLUTION: This display device is provided with frame memories 1, 2 storing gradation data of display pixels, a data rearranging circuit 4 which reads out the gradation data stored in the frame memories 1, 2 and disassembles the gradation data for every bit and rearranges the data, frame memories for ON/ OFF data 5, 6 storing the gradation data which are disassembled for every bit in the data rearranging circuit 4 as bit data for every bit and a display device control circuit 7 controlling lighting time lengths of the display pixels in accordance with the combination of bit data to be read out from the memories for ON/OFF data 5, 6.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display device,
In particular, the present invention relates to an improvement in a display device that converts grayscale data into an ON / OFF signal and displays the converted data.

[0002]

2. Description of the Related Art In a video output device or a display device of a computer terminal, gradation display is one of important display elements. As a gradation display method, in a display device such as a cathode ray tube display device which can perform analog control, an electron signal current can be controlled by applying an input signal voltage to a grid. , The luminance can be controlled almost continuously. on the other hand,
In an essentially binary display device that performs display using a memory effect, such as a PDP (plasma display panel) or a thermal sublimation type printer, the display time length is changed by utilizing the afterimage effect of human vision. Thus, a method of displaying a gradation is adopted.

As an example, FIG. 3 shows a lighting pattern of one pixel when displaying eight gradations. In FIG. 3, the vertical axis indicates the gradation to be displayed, the horizontal axis indicates time, and the symbol “○” indicates light-on and the symbol “●” indicates light-off. By controlling the number of times of lighting in this way, a gray scale can be displayed. However, if the gradation control is performed only by lighting seven times, a bias occurs in the time direction, which causes a problem such as generation of a false contour in an image.

[0004] In order to solve this problem, the number of times of lighting can be increased and the lighting patterns can be averaged to improve. FIG. 4 shows an example of the lighting pattern averaging. In order to increase the number of times of lighting and average the lighting pattern, it is necessary to increase the data transfer speed and increase the repetition frequency of lighting and extinguishing. However, in a conventional display device, in order to generate an ON / OFF signal representing a gray level of a pixel, data is read from a frame memory or a line memory, converted into ON / OFF data, and set. It was taking time.
When the set time is long, there is a problem that the display time is shortened, the screen brightness is reduced, the number of gradations cannot be obtained, and it is not possible to express subtle gradations.

[0005]

As described above, in a conventional display device which converts grayscale data into ON / OFF data and displays the grayscale data, the grayscale data read from the frame memory is sequentially converted into ON / OFF data. Therefore, it takes time to convert all the pixels, the screen luminance is reduced, the number of gradations cannot be obtained, and there are many problems in creating a moving image with subtle gradations. An object of the present invention is to solve this problem with a relatively simple configuration, improve the speed of setting gradation data, increase the luminance, and increase the number of gradations.

[0006]

In order to achieve the above object, the present invention provides a display device in which the gradation of the brightness of each display pixel constituting a display screen is represented by the lighting time length of the pixel per unit time. A gradation data storage unit for storing gradation data of the display pixel; a data rearrangement unit for reading out the gradation data stored in the gradation data storage unit and decomposing and rearranging the data for each bit; A bit-by-bit storage unit for storing the gradation data decomposed for each bit by the data rearranging unit as bit data for each bit; and displaying the gradation data in accordance with a combination of the bit data read from the bit-by-bit storage unit. Lighting time length control means for controlling the lighting time length of the pixel. Thereby, the gradation data can be read out in parallel as bit data directly connected to the lighting time length,
It is possible to realize a display device capable of increasing the setting speed of gradation data, increasing luminance, and increasing the number of gradations.

[0007]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a display device according to the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of the display device of the present invention. In FIG.
And 2 is a frame memory for storing video data to be displayed, 3 is a memory address control circuit, 4 is a data rearrangement circuit, 5 and 6 are ON / OF.
A frame memory for F data, reference numeral 7 denotes a display device control circuit, and reference numeral 8 denotes a display device.

The frame memories 1 and 2 use one of the memories for generating ON / OFF data, store the video data to be displayed next in the other memory, and use them alternately. The memory address control circuit 3 reads the video data from the frame memories 1 and 2 for performing the rearrangement, and stores the ON / OFF data frame memory 5
6 is created. ON / OFF
The data frame memories 5 and 6 are frame memories that store data so that the data output is directly turned ON / OFF data by the memory address control circuit 3 controlling the address. The display device 8 is controlled by the display device control circuit 7, whereby an image whose gradation is controlled is displayed on the display device 8.

Next, the data rearrangement operation according to the present embodiment will be described with reference to FIG. As shown in FIG. 2A, one frame of image data to be displayed is stored in the frame memory 1 or 2. FIG.
Each cell in (a) indicates an address, and each cell has one word (here, one word is 8 bits) from bit 0 (MSB) to bit 7 (LSB) as shown in FIG. Bit gradation data is stored. Assuming that the ON / OFF data of the display device 8 is for all the pixels in the horizontal direction, first, pixel data from the frame memory 1 or 2 is obtained from the beginning in the first row in the first row in the eight rows of gradation data, that is, The gradation data corresponding to the addresses A00 to A07 is read.

The read data is stored in the ON / OFF frame memory 5 or 6, and as shown in FIG. 2B, the address B00 stores the eight data stored in the addresses A01 to A07 in the frame memory 1 or 2. B of the gradation data of
It7 (LSB) as one word, address B1
Bit 0 of eight pieces of grayscale data is set as one word for bit6 of eight pieces of grayscale data, and bit0 of eight pieces of grayscale data is
(MSB) is rearranged into data for each bit as one word and stored. FIG. 2D shows address 8 of address B00.
Indicates bit data. Similarly, the next addresses B01 to B7
1 stores bit7 (LSB) to bit0 (MSB) of the gradation data of addresses A10 to A17 in the second row in the horizontal direction.

Thus, if there are eight rows in the horizontal direction and the number of vertical lines is 256, the number of addresses is 256 × 8 = 204
An 8-word memory is formed on the ON / OFF frame memory 5 or 6. The upper 8 bits of this memory address indicate the order of the vertical line, and the lower 3 bits are weighting for each pixel. The data stored in the ON / OFF frame memory 5 or 6 is sequentially read in bit units,
The display element is controlled so that this readout is directly proportional to the ON time. That is, O is determined by bit 7 (LSB).
Assuming that the time to become N is 1, 2 for bit6, 4 for bit5, 8 for bit4, 16 for bit3, 32 for bit2,
Control is performed so that 64 is set for bit 1 and 128 for bit 0 (MSB). In this time control, the lighting time may be changed, or the number of lightings may be changed at a fixed lighting time as shown in FIG. For example, if the bit 1 is ON and the MSB and bit 5 are 1 and the remainder is 0, the pixel of the corresponding display device is 128 + 4 = 13
It turns on twice, which means that the image data is converted into an analog light amount.

When data is read from the ON / OFF frame memory 5 or 6, for example, if data can be read in bit units from each bit in parallel, one read of ON / OFF data is significantly more compared with the conventional method. Can be faster. Generally, assuming that the number of ON / OFF data read out from the ON / OFF frame memory 5 or 6 is n, the data of the total number of pixels can be set to about 1 / n.

In a PDP or the like, a shorter data setting time leads to a longer lighting time, and the maximum luminance is determined by the ratio of the data setting time to the lighting time. The brightness can be increased by shortening the time. Further, since the number of times of lighting can be increased even if the blinking frequency is the same, it is possible to express a delicate gradation by increasing the number of gradations.

[0015]

As described above, according to the first aspect of the present invention, there is provided a display device in which the gradation of luminance of each display pixel constituting a display screen is represented by the lighting time length of the pixel per unit time. Gradation data storage means for storing gradation data of display pixels, data rearrangement means for reading out gradation data stored in the gradation data storage means, and decomposing and rearranging each bit, and data rearrangement means The bit-by-bit storage means that stores the gradation data decomposed for each bit as bit data for each bit, and controls the lighting time length of the display pixel according to the combination of each bit data read from the bit-by-bit storage means Lighting time length control means. Thus, with a relatively simple configuration, it is possible to control the display by converting the grayscale data into bit data directly related to the lighting time of the display pixel, improve the setting speed of the grayscale data, increase the brightness, A display device capable of increasing the number of gradations can be realized.

According to a second aspect of the present invention, the bit data output from the bit-by-bit storage means is performed in parallel. As a result, the setting of the pixel data can be speeded up at a speed substantially proportional to the parallel number, and the luminance can be further increased and the number of gradations can be increased.

According to a third aspect of the present invention, the gradation data storage means includes storage means for two fields for alternately storing and reading gradation data. This makes it possible to continuously store and read out the gradation data, and it is possible to eliminate delays in the storage and reading operations in this portion.

The invention according to a fourth aspect of the present invention is characterized in that the storage means for each bit has a storage means for two fields for alternately storing and reading out bit data. As a result, bit data can be stored and read continuously, and delay in storage and read operations in this portion can be eliminated.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a display device of the present invention.

FIG. 2 is an explanatory diagram of a data rearranging operation according to the present invention.

FIG. 3 is an explanatory diagram showing a lighting pattern of one pixel when displaying eight gradations.

FIG. 4 is an explanatory diagram showing an example of lighting pattern averaging.

[Explanation of symbols]

1, 2 ... frame memory, 3 ... memory address control circuit, 4 ... data rearrangement circuit, 5, 6 ... frame memory for ON / OFF data, 7 ... display device control circuit, 8
... display device.

Claims (4)

[Claims] 1. A display device in which a luminance gradation of each display pixel constituting a display screen is represented by a lighting time length of a corresponding pixel per unit time, wherein gradation data storage means for storing gradation data of the display pixel. A data rearranging unit that reads out the grayscale data stored in the grayscale data storage unit, decomposes and rearranges each bit, and the grayscale decomposed for each bit by the data rearrangement unit. A bit-by-bit storage unit that stores data as bit data for each bit; and a lighting time length control unit that controls a lighting time length of the display pixel according to a combination of each bit data read from the bit-by-bit storage device. A display device, comprising: 2. The display device according to claim 1, wherein the bit data output from the bit-by-bit storage unit is performed in parallel. 3. The display device according to claim 1, wherein said gradation data storage means has two fields of storage means for alternately storing and reading out said gradation data. 4. The display device according to claim 1, wherein said bit-by-bit storage means includes storage means for two fields for alternately storing and reading said bit data.