JP2001349933A - Delay time detecting circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a delay time detecting circuit capable of indicating degree of delay without preparing a plurality of patterns. SOLUTION: This delay time detecting circuit detects the delay time of a circuit 11 sandwiched by a plurality of flip-flops 12 and 13, and has a binary up counter 15 that is reset just after data for the circuit 11 are transmitted to the flip-flop 12 in a previous stage and a trigger signal is provided and counts input times of a clock signal until finishing of the propagation of the circuit 11.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a delay time detection circuit, and more particularly to a delay time detection circuit provided in a semiconductor integrated circuit having a plurality of sequential circuits.

[0002]

2. Description of the Related Art FIG. 3 is a circuit diagram of a conventional delay determination circuit. As shown in FIG. 3, the delay determination circuit 1 has a combinational circuit 2 sandwiched between flip-flops (FF) of a rising edge trigger, which are delay determination targets.

The FF3 at the front stage of the circuit 2 connects the data input terminal Din and the control clock terminal C5.
The data output terminal Dout and the control clock terminal C6
Each has it.

A specific operation of the delay determination circuit 1 will be described. The outputs of the circuit 2 and the FF 3 are both low.
In the input to Din, the output value of the circuit 2 is high (Hi).
Is set in advance to a value that changes to By sending a signal to C5, the value of Din is sent to circuit 2.

Then, the clock of C6 is input and the circuit 2
If the output value of FF3 changes from low to high, it is determined that there is no delay fault, and if the output value of the circuit 2 remains low without change, it is determined that a delay fault has occurred. As described above, the presence or absence of the delay fault is determined based on the output value.

[0006]

However, in the delay determination circuit 1 for determining whether or not there is a delay fault, it is not possible to know how much the signal is out of the delay standard in one pattern. When investigating, it was necessary to prepare scan patterns in which the timings of C5 and C6 were varied.

An object of the present invention is to provide a delay time detecting circuit capable of knowing how much delay has occurred without preparing a plurality of patterns.

[0008]

To achieve the above object, a delay time detection circuit according to the present invention is a delay time detection circuit for detecting a delay time of a circuit sandwiched between a plurality of sequential circuits, It is reset at the same time as sending out data to the circuit to the preceding sequential circuit and giving a trigger signal,
There is provided a counting circuit for counting how many times the clock signal is inputted until the propagation of the circuit is completed.

With the above structure, the delay time detecting circuit for detecting the delay time of a circuit sandwiched between a plurality of sequential circuits sends data to the preceding sequential circuit to supply a trigger signal, The counter is reset, and the number of times the clock signal is input until the propagation of the circuit ends is counted by the counting circuit. As a result, it is possible to know how much delay has occurred without preparing a plurality of patterns.

[0010]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a circuit diagram of a delay time detecting circuit according to an embodiment of the present invention. As shown in FIG. 1, the delay time detection circuit 10 includes a circuit 11, a flip-flop (FF) 12, a flip-flop (FF) 13, an OR circuit 14, and a binary up counter (BUC) 15 for which a delay time is to be detected. have.

A front-stage FF 12 is provided at an input terminal of the circuit 11.
The output terminal of the circuit 11 is connected to the FF 13 at the subsequent stage, and the FF 12 is connected to the data input terminal Din. The output value from the FF 13 can be read from the output terminal Dout. Both FFs 12 and 13 operate according to the rising edge.

A clock terminal C16 is connected to the clock signal input section of the FF12, and a clock terminal C17 is connected to the clock signal input section of the FF13.
The clock terminal C16 is connected to the reset unit of the BUC 15, and the clock terminal C17 is connected to one input terminal of the OR circuit 14, respectively. A stationary pulse wave is given to the clock terminal C17.

The FF1 is connected to the other input terminal of the OR circuit 14.
3 is connected to the output terminal of the OR circuit 14 by the BUC 15
Are connected to each other. BUC15
From the output terminal B connected to the output section Qn of the
Can read the count value.

The BUC 15 counts rising edges input from the counting section C and resets when the reset section R is high.

That is, the delay time detecting circuit 10, which is a semiconductor integrated circuit having a plurality of sequential circuits for holding or writing data in synchronization with a clock signal, has a data input terminal Din (test pattern) for checking internal operation. An input unit), a clock terminal C16 (first clock input unit) for receiving a delay signal input from the outside, a clock terminal C17 (second clock input unit) for receiving a clock signal composed of a constant pulse wave, Clock terminal C1
7, an OR circuit 14 (logic circuit) that receives an input signal from the FF 13 and an output signal of the FF 13 (sequential circuit at the subsequent stage),
BUC 15 having a counting unit to which the output of circuit 14 is connected
(Counting circuit).

Next, the operation of the delay time detecting circuit 10 will be described. A pulse wave having a constant period is given to the clock terminal C17, and the outputs of the circuit 11 and the FF 13 and the clock terminal C1 are output.
6 is set to low, and the data input terminal Din is set to high. At this time, the value of the data input terminal Din is not shifted to the circuit 11 because the clock terminal C16 is fixed to low.

When a trigger clock signal serving as a trigger of a delay test is applied to the clock terminal C16, a high value set at the data input terminal Din propagates to the circuit 11 and the BUC 15 is reset.

While the signal propagates through the circuit 11, the clock signal input to the clock terminal C17 is
C15 counts. When the output of the circuit 11 switches from low to high and a clock is input to the clock terminal C17, the output value of the FF 13 changes from low to high. As a result, the input value of the counting unit C of the BUC 15 is fixed to high, and the counting stops.

Therefore, by reading the count number from the output terminal B of the BUC 15 and multiplying the count by a cycle,
The approximate value of the delay time of the circuit 11 can be obtained with one test pattern.

This means that the data is sent to the front-stage FF 12 to the circuit 11 and a trigger signal is given and at the same time BUC1
This is because the delay time can be roughly estimated by resetting 5 and counting the number of times the clock signal is input until the propagation of the circuit 11 ends.

As a result, it is not necessary to prepare several sets of test patterns when 01 is determined by one test pattern, and the pattern becomes enormous in the case of a scan control circuit. Time does not increase.

In the above embodiment, an example has been described in which a binary counter is built in a semiconductor integrated circuit. However, a binary counter is not built in, and a reset signal or a count signal is directly output to use an external counter. May be. Thus, the number of binary counter circuits can be reduced.

Further, a frequency dividing circuit may be inserted at the count signal output terminal. FIG. 2 is a circuit configuration diagram of a delay time detection circuit according to another embodiment of the present invention. As shown in FIG. 2, the delay time detecting circuit 20 has a frequency dividing circuit 21 inserted at the count signal output terminal of the OR circuit 14. Thus, the interval between the clock signals Co output from the frequency dividing circuit 21 can be made longer, so that even a tester supporting low frequencies can observe the movement of the clock signal Co.

As described above, according to the present invention, the circuit 11
By counting the number of times the clock signal is input until the propagation of the data is completed, the time during which data passes through the circuit 11 interposed between the rising edge trigger flip-flops (the FF12 at the front stage and the FF13 at the rear stage) is counted. That is, the approximate value of the delay time of the circuit 11 can be obtained by one test pattern.

In particular, in the present invention, the counter (BUC1
At the same time as resetting 5), the flip-flop (the preceding FF 12) is shifted.

[0027]

As described above, according to the present invention, a delay time detecting circuit for detecting a delay time of a circuit sandwiched between a plurality of sequential circuits sends data to the preceding sequential circuit. The counter is reset at the same time as the trigger signal is given, and the counting circuit counts how many times the clock signal is input until the propagation of the circuit ends.
Without preparing a plurality of patterns, it is possible to know how much delay there is.

[Brief description of the drawings]

FIG. 1 is a circuit configuration diagram of a delay time detection circuit according to an embodiment of the present invention.

FIG. 2 is a circuit configuration diagram of a delay time detection circuit according to another embodiment of the present invention.

FIG. 3 is a circuit configuration diagram of a conventional delay determination circuit.

[Explanation of symbols]

 10, 20 delay time detection circuit 11 circuit 12, 13 flip-flop 14 OR circuit 15 binary up counter 21 frequency divider B, Dout output terminal C16, C17 clock terminal Din data input terminal Qn output section

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H03K 5/13

Claims (6)

[Claims] 1. A delay time detecting circuit for detecting a delay time of a circuit sandwiched between a plurality of sequential circuits, the data being sent to a preceding sequential circuit and being supplied with a trigger signal and being reset at the same time. And a counting circuit for counting how many times the clock signal is inputted until the propagation of the circuit is completed. 2. The delay circuit according to claim 1, wherein the count value of the counting circuit is read, and an approximate value of the delay time of the circuit is obtained by one test pattern by multiplying the count by a period. Time detection circuit. 3. The delay time detecting circuit according to claim 1, wherein the sequential circuit operates by a rising edge trigger and holds or writes data in synchronization with a clock signal. 4. The delay time detecting circuit according to claim 1, wherein an external counting circuit is used without incorporating the counting circuit. 5. The logic circuit according to claim 1, wherein a frequency divider is inserted into a count signal output terminal of the logic circuit, and a movement of a clock signal output from the frequency divider is observed. Delay time detection circuit. 6. A delay time detecting circuit having a plurality of sequential circuits for holding or writing data in synchronization with a clock signal, comprising: a test pattern input section for checking internal operation; A first clock input unit for receiving a delay signal, a second clock input unit for receiving a clock signal composed of a constant pulse wave, an input signal from the second clock input unit, and an output signal of a sequential circuit in a subsequent stage 1. A delay time detection circuit comprising: a logic circuit having an input of: a first clock input unit connected to a reset signal unit, and a count circuit connected to an output of the logic circuit by a counter unit.