JP2001345694A - Logic function circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a logic function circuit for facilitating a timing design of an input signal when a circuit of a semiconductor integrated circuit is designed by using a logic function circuit called a macro cell. SOLUTION: The logic function circuit comprises latch circuits (14, 16) for inputting a data signal or an address signal in synchronism with a clock signal, a clock buffer (17) for repeating the clock signal (8) to be transmitted to the latch circuit, and a delay circuit (41, 42) provided at an input signal line for transmitting an input signal (3, 4) to the latch circuit (14, 16) in such a manner that a time difference between a signal delay time of a clock signal line and a signal delay time of the input signal line is set to substantially '0', or the difference is set to substantially integer times as large as half the period of the clock signal. The function circuit also comprises a diagnostic logic for conducting an operation test of an internal circuit mounted in the delay circuit (41, 42) to externally input a diagnostic signal.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an ASIC (applicant) such as a register file or on-chip RAM.
The present invention relates to a technique which is useful when applied to a logic function circuit such as a macro cell used in ion specific integrated circuits.

[0002]

2. Description of the Related Art In recent years, a technology called an ASIC for providing a user with a custom function unique to a semiconductor integrated circuit has been actively used for customers who produce various electronic devices using the semiconductor integrated circuit.

[0003] In the ASIC, various macro cells having a specific function designed in advance and provided with specific functions are provided to the user as past resources, and the user combines these macro cells with a user's own logic circuit to design the entire circuit of the semiconductor integrated circuit. Designing can greatly reduce the development period. The macro cell includes, for example, various logic operation units, registers, on-chip RAM,
There are cores and so on.

[0004]

SUMMARY OF THE INVENTION Some macro cells include:
An input unit to which a signal is input from another peripheral circuit such as a register file or an on-chip RAM is provided with a latch circuit for latching an input signal in synchronization with a clock signal, and the input timing of the signal is aligned by the latch circuit. Some are supplied to internal circuits.

Further, such a clock synchronous latch circuit has an input characteristic that an input signal must be determined from a setup time to a hold time. The setup time is the time during which the level of the signal to be latched must be determined before the input of the clock signal, and the hold time is the time during which the determined level of the signal to be latched must be maintained after the input of the clock signal. is there.

However, in a conventional macro cell having a latch circuit at an input portion, a transmission system of a clock signal input from outside the macro cell to the latch circuit and a data signal and an address signal input from a peripheral circuit to the latch circuit are provided. The signal transmission time was not adjusted in the macro cell with the signal transmission system.

Therefore, when a circuit is designed to input a clock signal and a data signal to a conventional macro cell, the input timing of the clock signal is changed so that the input signal does not change from the setup time to the hold time of the latch circuit. It is necessary for the user to design the input signal and the input signal decision timing outside the macro cell, and then to design the input signal into the macro cell, which is very troublesome. Furthermore, in recent years, the operation speed of semiconductor integrated circuits has been increasing, and the timing design of clock signals and input signals as described above has become more difficult and troublesome.

Further, as shown in FIG. 6, in a register file 10 having a large number of flip-flops (latch circuits) 14 and 16 in an input section, a large number of flip-flops 14 and
A clock buffer 1 for relaying a clock signal in a macro cell for distributing the clock signal 8 to the macro cell 16
In general, as shown in the time chart of FIG. 7, the clock signal delay τ4 caused by the clock buffer 17 corresponds to the apparent setup time TS0 and the hold time as viewed from the outside of the register file 10. Since the timing of TH0 is shifted, if the write data 4 is normally output from the flip-flop 21e in the preceding stage, the data signal changes between the setup time and the hold time, causing data racing. This causes the timing design of the input signal to the macrocell to be more difficult.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a logic function circuit for an input latch which can easily design a timing of an input signal when designing a circuit of a semiconductor integrated circuit using a logic function circuit called a macro cell. is there.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0011]

The outline of a typical invention among the inventions disclosed in the present application is as follows.

That is, a logic function circuit having a desired function is selected from a plurality of logic function circuits registered in a database and used, and the logic function circuit is used in a semiconductor integrated circuit design method for designing a semiconductor integrated circuit. A latch circuit for receiving an input signal such as a data signal or an address signal in synchronization with a clock signal; a buffer circuit for relaying a clock signal transmitted to the latch circuit; and a clock circuit for the latch circuit. A delay circuit provided on at least one of a clock signal line for transmitting a signal or an input signal line for transmitting an input signal to the latch circuit, the signal delay time of the clock signal line and the input signal The time difference from the signal delay time of the line is set to substantially “0”, or the time difference is set to the clock signal. Configured to set to be substantially an integral multiple of the half period.

According to such means, when designing a circuit of a semiconductor integrated circuit using an existing logic function circuit in a database, the delay of the signal transmission time of a clock signal or an input signal in the logic function circuit is reduced. The timing of the clock signal and the input signal to be input to the latch circuit can be designed without substantially considering the above, and therefore, the timing of the entire system can be easily designed.

In particular, in the case of an ASIC in which the user designs a circuit by combining a logic function circuit that has been designed in advance and a unique logic circuit, a circuit that adjusts the input timing of a signal input to the logic function circuit is a logic circuit. There is no need to design outside the functional circuit, and the user's labor can be reduced.

More preferably, a diagnostic logic is provided in the delay circuit, and when a diagnostic signal is input from the outside,
It is preferable that the delay circuit outputs a diagnostic signal to an internal circuit.

As described above, by adding the diagnostic logic to the delay circuit, the peripheral circuit of the logic function circuit can be compared with a case where the diagnostic logic circuit is provided in the preceding stage of the logic function circuit separately from the delay circuit. And its wiring can be simplified.

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A preferred embodiment of the present invention will be described below with reference to FIGS.

FIG. 1 is a circuit diagram showing an input part of a register file as a logic function circuit according to an embodiment of the present invention and a circuit at a preceding stage thereof, and FIG. 2 is a timing chart of signals input / output in this circuit. FIG. FIG. 3 is a block diagram showing a configuration example of an ASIC using the register file of FIG.

Although the register file 10 of this embodiment is not particularly limited, as shown in FIG. 3, it has one read port and one write port, and has a memory capacity of N words × M bits. It has a port memory mat 11. Edge trigger flip-flops 14 and 16 as a synchronous latch circuit which takes in the write address 3 and the write data 4 in synchronization with a clock are input to the input section.
Is provided, and the fetched write address is
And the write address 3 of the memory mat 11
The write data 4 is written in the area corresponding to. The read address 2 is input via the buffer 12, decoded by the decoder 13, and data is read from the area corresponding to the read address 2 of the memory mat 11.
It is configured to be output to.

The semiconductor integrated circuit 100 shown in FIG. 3 is an ASIC such as a hard disk controller, for example.
Is provided to the user as a pre-designed macro cell.

In the preceding stage of the register file 10, there are provided logic circuits 20 to 22 designed by the user.
Write address 3 and write data 4 are output to register file 10, respectively. The logic circuits 20 to 22 include logic units 20a, 20b, 21a, 21b, 22a,
22b, edge-triggered flip-flops 20c to 20e, 21c to 21 for aligning signal timings.
Synchronous circuits such as e and 22c to 22e are provided in the middle of the signal path.

The semiconductor integrated circuit 100 has a clock generation circuit 24 for generating the clock signal 8. The clock generation circuit 24 outputs the register file 10 and the flip-flops 20 c to 20 e and 21 of the logic circuits 20 to 22.
The clock signal 8 is supplied to c to 21e and 22c to 22e via signal transmission buffers 24a and 24b in a plurality of stages. The semiconductor integrated circuit 100 is also provided with a system test circuit 25 for performing an operation test of the system. The system test circuit 25 can output a diagnostic signal for performing an operation test to the register file 10.

As shown in FIG. 1, in the register file 10 of this embodiment, a clock buffer 17 for relaying the clock signal 8 is provided in a stage preceding the flip-flops 14 and 16. The clock buffer 17 distributes and supplies a clock signal 8 for giving a latch timing to flip-flops 14 and 16 for taking in the write address 3 and the write data 4. Although only one flip-flop 14 or 16 is shown in FIG. 1, these circuits are provided by the same number as the number of bits of the write address 3 and the write data 4. Further, in this embodiment,
Buffer circuits 41 and 42 as delay circuits corresponding to the clock buffer 17 are provided on signal lines for the write address 3 and the write data 4.

Next, the operation of the input section of the register file 10 and restrictions imposed on input signals will be described with reference to the time chart of FIG.

In the register file 10, the clock signal 8 is input to the flip-flops 14 and 16 with a delay time τ1 due to the gate delay of the clock buffer 17.

The write address 3 and the write data 4 are also output to the flip-flop 16 with a delay of the delay time τ2 due to the delay of the buffer circuits 41 and 42, respectively.

In FIG. 2, TS0 and TH0 are a setup time and a hold time in the register file 10 with reference to the clock signal of the node n2 input to the flip-flop 16, and these setup times TS
0 and the hold time TH0 are determined by the characteristics of the flip-flop 16.

On the other hand, TS1 and TH1 are the apparent setup time and hold time as seen from outside the register file 10 with reference to the clock signal 8 inputted from outside the register file 10. The apparent setup time TS1 is different from the delay time τ1 of the clock buffer 17 and the delay time τ of the buffer circuit 42 because the reference point is shifted by the delay time τ1 and the data signal is also shifted by the delay time τ2.
2 and the difference Δτ (= τ1−τ2) from the flip-flop 1
Time TS1 subtracted from setup time TS0 of No. 6 =
TS0−Δτ. Also, the apparent hold time T
Since the time H1 is a time that goes back to the past from the rising edge of the clock signal, the time is obtained by adding the above time difference Δτ to the hold time TH0 of the flip-flop 16 (TH1 = TH1).
0 + Δτ.

In this embodiment, the buffer circuit 42
Is the delay time τ1 of the clock buffer 17.
Are substantially the same, the difference Δτ becomes a small value, and the hold time TH0 and the setup time TS0 of the flip-flop 16 and the apparent hold time TH1 and the setup time TS1 as seen from the outside of the register file 10 do not change much. It will be.

On the other hand, when the buffer circuit 42 is not provided, that is, when the delay time τ2 of the buffer circuit 42 is regarded as 0, the value of Δτ becomes large, so that the apparent hold time TH1 also becomes large. Thus, the apparent setup time TS1 becomes shorter.

In FIG. 2, Tdmin is the time from the rise of the clock signal 8 to the timing at which the write data 4 changes, and Tdmax is the time from the rise of the clock signal 8 to the timing at which the next write data 4 is settled. However, since the write data 4 input from the outside needs to be determined from the apparent setup time TS1 to the lapse of the apparent hold time TH1,
In the register file 10 of the above embodiment, the constraint imposed on the input timing of the write data 4 input from the outside is Tdmin> TH1. In the circuit of FIG. 1, since there is no margin in the timing on the hold time side, it is assumed that the setup time side has a margin.

Therefore, when the buffer circuit 42 is provided, the apparent hold time TH1 is shorter than when the buffer circuit 42 is not provided. Therefore, the restrictions imposed on the input timing of the write data 4 are relaxed, and For example, it is not necessary to make the delay time of the flip-flop 22e that outputs 4 longer than usual, so that the timing design is facilitated and the operation with the faster frequency clock is also possible.

Since the timing design of the write address 3 is the same as that of the write data 4, the description is omitted.

As an additional configuration, in the register file 10 of this embodiment, the buffer circuits 41 and 42 for facilitating the timing design of the input signal are provided.
Is provided with a diagnostic logic function. That is, the buffer circuits 41 and 42 are connected to the system test circuit 25 (FIG. 3).
Is connected to a signal path 9 for supplying a diagnostic signal output from the buffer circuit 41. The diagnostic signal is supplied from the signal path 9 to the buffer circuit 41 in place of the write address 3 and the write data 4. The memory mat 11 is latched and written, and then a diagnostic signal is sent from the signal path 9 to the buffer circuit 1 in place of the read address.
2 to determine the read data 5 output from the memory mat 11, it is possible to test whether or not the register file 10 operates normally.

As described above, the buffer circuits 41, 4
2 is provided with a diagnostic logic function, so that an operation test of the register file 10 can be performed.
2 in comparison with the case where a diagnostic circuit for providing a diagnostic signal to the register file 10 from the side of the register file 10 is provided.
Peripheral circuit and its wiring can be simplified.

Preferably, the register file 10 may be provided with a control signal terminal and a switch for bypassing the buffer circuits 41 and 42 based on a control signal input to the terminal. If there is any logic gate after the flip-flops 21e and 22e, and the timing of the setup / hold time of the write address 3 and the write data 4 is guaranteed without the buffer circuits 41 and 42, the buffer circuit 41 , 42 can be bypassed, and the input timing of the input signal to the flip-flops 14 and 16 can be adapted to the setup and hold time of the flip-flops 14 and 16.

Further, by providing a plurality of delay circuits and selectors each having a different delay time, the register file 1
0 and the input signal (write address 3
And write data 4) can be switched so that the clock signal or the input signal in the register file 10 can be changed regardless of the output timing of the signal from the circuit preceding the register file 10. The signal delay time is switched to an optimum value, and the input timing of the input signal is set up in the register file 10.
The effect of being able to adapt to the hold time is also obtained.

FIG. 4 is a circuit diagram of a register file input section and a circuit preceding the register section according to a second embodiment of the present invention.
FIG. 5 shows a time chart of each signal input / output in the circuit.

As shown in FIG. 4, in the register file 10 of this embodiment, the write address 3 and the write data 4
In order to facilitate the timing design of the above, instead of providing delay circuits on the signal lines for the write address 3 and the write data 4, buffer circuits 44, 44 as delay circuits are provided on the clock signal lines to delay the clock signal lines. The time is substantially delayed by a half cycle of the clock signal 8 as compared with the delay time of the signal line for the write address 3 and the write data 4.

According to such a register file 10, since the clock signal of the node n4 input to the flip-flop 16 is delayed by half a cycle from the clock signal 8 input from the outside, the delayed clock signal is used as a reference. Setup time TS0 of the flip-flop 16
The hold time TH0 is as shown in FIG.

Further, only the clock signal serving as a reference point for the setup time and the hold time is delayed and the write data 4
Is transmitted without delay, the apparent hold time TH1 as seen from the outside of the register file 10 is the time TH1 = TH0 + τ3 obtained by adding the delay time τ3 of the clock signal to the hold time TH0 of the flip-flop 16. Also, since the apparent setup time TS1 is positive when going backward in the past from the rising edge of the clock,
Time TS1 = TS obtained by subtracting clock signal delay time τ3 from setup time TS0 of flip-flop 16
0−τ3.

In this embodiment, since the delay time τ3 of the clock signal is set to substantially half the length of the clock cycle, the apparent setup time TS1 is a negative value, that is, after the rise of the clock signal. Time.

Therefore, in order to design the timing of the write data 4 in the circuit of this embodiment, the clock signal 8
Is designed so that the write data “D0” input at the time of the rise is not input to the flip-flop 16, but the next write data “D1” is input to the flip-flop 16. The timing design of the write data 4 can be facilitated. However, when inputting data continuously, only the latch of the first data is delayed, and the total required time hardly increases.

In the above case, after the rising of the clock signal 8, the next write data 4 (for example, "D1") is inputted.
Must be determined between the apparent setup time TS1 and the hold time TH1. Therefore, the constraint imposed on the input timing of the write data 4 is Tdmax <
| TS1 |. In the setup time, the elapsed time is treated as a negative value, so that the absolute value is compared. Further, in this case, since there is no margin in the timing on the setup time side, it is assumed that there is a margin on the hold time side.

The above restriction does not require, for example, that the delay of the flip-flop 22e outputting the write data 4 be longer than usual, so that the timing design of the write data 4 becomes easy, and Operation is also possible.

Since the timing design of the write address 3 is the same as that of the write data 4 described above, the description is omitted.

As described above, according to the register file 10 of the above embodiment, the buffer circuit for appropriately adjusting the delay time between the clock signal 8 and the input signals such as the write address 3 and the write data 4 in the register file 10. 41,
42, the register file 10
When the circuit design of a semiconductor integrated circuit is performed using a macro cell as a macro cell, it is possible to design the timing of the input signal without substantially considering the difference in signal transmission time between the clock signal and the input signal in the register file 10. Therefore, the timing design of the whole system becomes easy.

In particular, when the user designs the ASIC using the register file 10 as an existing macro cell, the timing of the input signal to the register file 10 can be easily designed, and the user's labor can be reduced.

Although the invention made by the inventor has been specifically described based on the embodiments, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the gist of the invention. Needless to say.

For example, the edge trigger type flip-flop has been described as the latch circuit. However, the present invention is not limited to this. Any type of circuit may be used as long as it takes in a signal in synchronization with a clock. Further, the delay circuit is not limited to the buffer circuit. The buffer circuit 41 of FIG.
Although a configuration in which a diagnostic logic function is added is shown in FIG. 42, an effect that timing design can be easily performed can be obtained even if a configuration having only a signal delay function without adding a diagnostic logic function is provided. Further, the signal input to the macro cell is not limited to the write data and the write address to be written in the register file, and can be applied to various input signals.

In the above description, the invention made by the inventor has been mainly described with respect to the register file which is the field of application as the background, but the invention is not limited to this, and the input signal is latched at the input section. It can be widely used for a logic function circuit of a type to be supplied to an internal circuit later. Further, the semiconductor integrated circuit using the logic function circuit is not limited to the hard disk controller but can be widely used for various semiconductor integrated circuits such as a CPU and a network controller.

[0052]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

That is, according to the present invention, when a circuit design of a semiconductor integrated circuit is performed using a logic function circuit called a macro cell, the delay of the signal transmission time in the logic function circuit is hardly taken into consideration, and the latch circuit is transferred to the latch circuit. The timing of the input clock signal and the input signal can be designed.
Therefore, there is an effect that the timing design of the whole system becomes easy.

In particular, in the case of an ASIC in which a user designs a circuit by combining a logic function circuit provided in a designed state and a unique logic circuit, it is necessary to adjust the input timing of a signal input to a macro cell. Disappears,
There is an effect that the user's labor can be reduced.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing an input part of a register file as a logic function circuit according to an embodiment of the present invention and a circuit at a preceding stage thereof.

FIG. 2 is a time chart illustrating timings of signals input and output in the circuit of FIG. 1;

FIG. 3 is a block diagram illustrating a configuration example of an ASIC using a register file according to an embodiment of the present invention.

FIG. 4 is a circuit diagram showing an input part of a register file and a preceding circuit thereof according to another embodiment of the present invention.

FIG. 5 is a time chart showing timings of signals input and output by the circuit of FIG. 4;

FIG. 6 is a circuit diagram showing an example of a conventional macro cell (register file) input section and a circuit preceding the input section.

FIG. 7 is a time chart showing timings of signals input and output by the circuit of FIG. 6;

[Explanation of symbols]

3 Write address 4 Write data 8 Clock signal 9 Diagnostic signal 10 Register file 11 Memory mat 14, 16 Edge trigger flip-flop (latch circuit) 17 Clock buffer 24 Clock generation circuit 25 System test circuit 41, 42 Buffer circuit (Delay circuit) 44, 44 Buffer circuit (delay circuit) 100 Semiconductor integrated circuit (ASIC) TS0 Flip-flop setup time TH0 Flip-flop hold time TS1 Apparent setup time TH1 Apparent hold time

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H03K 19/0175 H01L 27/04 T H03K 19/00 101K 101N F-term (Reference) 5B048 AA20 DD10 5F038 CD06 CD08 CD09 DF05 DF11 DF16 DT02 DT15 EZ20 5F064 AA02 BB12 BB19 BB26 EE47 EE54 FF09 FF14 FF52 HH10 HH12 5J042 AA10 BA01 BA03 CA12 CA13 CA14 CA15 CA20 CA27 DA04 DA05 5J056 AA01 AA39 00

Claims (1)

[Claims] A logic function circuit having a desired function selected from a plurality of logic function circuits registered in a database, and the logic function circuit having the desired function is selected and used to design the semiconductor integrated circuit; In the functional circuit, a latch circuit for receiving an input signal such as a data signal or an address signal in synchronization with a clock signal, a signal relay buffer circuit for relaying a clock signal transmitted to the latch circuit, and a clock for the latch circuit A delay circuit provided on at least one of a clock signal line for transmitting a signal and an input signal line for transmitting the input signal to the latch circuit, for delaying a transmission signal; and a signal delay time of the clock signal line and the input The time difference from the signal delay time of the signal line is set to substantially “0”, or the time difference is Logic function circuit, characterized in that it is set to approximately an integer multiple of the half period of the.