JP2001345386A - Method for automatically wiring semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method for automatically wiring a semiconductor integrated circuit which contrives to restrict generation of an upper and lower restriction in a wiring design of the semiconductor integrated circuit, and shortens the time required for layout design, and enables to decrease the size of the semiconductor integrated circuit and increase the speed thereof. SOLUTION: This method comprises the steps of: congestion of a schematic wiring lattice set in S105 is made uniform (S103); determining a vertical direction detailed wiring route based on the schematic wiring route in S103 (S110); determining a horizontal direction detailed wiring route based on the vertical direction detailed wiring route in S110 (S111); further extracting a vertical direction segment belonging to a vertical direction schematic wiring region in the vertical direction detailed wiring step in S110 (S112); bisecting the vertical direction schematic wiring region up to a wiring track level (S113, S114); updating a wiring congestion every division (S115); allocating a vertical direction segment to a new division region at every division (S116); and forming a horizontal direction segment when the division of the vertical direction segment in S116 is generated (S117).

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wiring process in a layout design of a semiconductor integrated circuit, and more particularly to a method of determining a net wiring route using a computer.

[0002]

2. Description of the Related Art A semiconductor integrated circuit is constructed by arranging cells or blocks having a logical function or a memory function in a chip and wiring the input / output terminals.

[0003] In the wiring, different layers are allocated to a horizontal wiring called a trunk and a vertical wiring called a branch, and through holes are used to connect the branch and the trunk allocated to different layers. It is common to use

As shown in FIG. 2, in the wiring processing in the layout design of a semiconductor integrated circuit, rough wiring grids 7 are set on a chip 1 and the congestion degree of each rough wiring grid 7 is estimated.
A schematic wiring design that performs wiring path assignment at a schematic wiring grid level in consideration of the congestion degree, and a detailed wiring that determines the arrangement of detailed wiring 8 on the schematic wiring grid 7 in the schematic wiring path as shown in FIG. It consists of two processes of design. In FIG. 3, 9 indicates a trunk line, and 10 indicates a branch line.

As shown in FIGS. 4A and 4B, a generally known method includes a vertical detailed wiring step based on a schematic wiring path determined by a schematic wiring design.
This is performed in the order of the horizontal detailed wiring process. This is, for example, "IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN O
F INTEGRATED CIRCUITS AND SYSTEMS ”(Vol. 14 (No.
3), March 1995).

In the conventional vertical detailed wiring process, a passing point 11 of a branch line is determined (vertical detailed wiring) on the boundary of the general wiring grid 7 so that the vertical wiring is as straight as possible.

In the horizontal detailed wiring step, the Y coordinate of the horizontal segment 12 in which the X coordinates of the start point and the end point are determined is determined so that the wiring does not overlap.

[0008]

The above prior art is disclosed in FIG.
Focusing on the connection between the branch line passing point t1 and the terminal a2 and the connection between the branch line passing points t2 and t3 shown in (a), (b), and (c), the branch line passing point is located immediately below the branch line passing point t1. Since t3 exists,
There is a vertical constraint on the trunk line assignment that the trunk line between t1 and a2 must be assigned above the trunk line between t2 and t3. On the other hand, also for the branch line passing point t2 and the terminal a2, there is similarly an upper / lower constraint that the trunk line between t1 and a2 must be allocated below the trunk line between t2 and t3.

Therefore, a contradiction arises between these two upper and lower constraints. In such a case, FIG.
As shown in (b) and (c), one main line is divided and wired. When wiring is performed by dividing the trunk line in this way, a large number of wiring tracks are required, and the number of through holes increases.

Also, as shown in FIG. 6, nets a, b,
Paying attention to the connection between the branch line passing points ta1-ta2,..., td1-td2 of c and d, upper and lower constraints as shown in FIG. 5 occur for the trunk line allocation of the nets a, b, c and d. ing. As a result, if the number of vertical constraints exceeds the number of available horizontal wiring tracks in the wiring channel area, the net d
In such a case, it is necessary to secure a usable horizontal wiring track by generating the non-wiring 13 or increasing the height of the wiring channel region, thereby increasing the chip area.

As described above, when allocating the trunk line, the occurrence of upper / lower restrictions causes the division of the trunk line, the occurrence of non-wiring, and the increase in the wiring channel height. These problems lead to an increase in chip area due to the need for a large number of wiring tracks and an increase in through-hole resistance due to an increase in through-holes, which hinders miniaturization and high-speed operation of the semiconductor integrated circuit.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor integrated circuit that suppresses vertical constraints in the wiring design of a semiconductor integrated circuit, shortens the time required for layout design, and enables the semiconductor integrated circuit to be reduced in size and speed. An object of the present invention is to provide a method for automatically wiring a circuit.

[0013]

According to the present invention, in order to solve the above-mentioned problems, according to the present invention, a schematic wiring grid divided into meshes is set on the entire surface of a semiconductor integrated circuit chip, and a general wiring path is defined. An automatic wiring method for a semiconductor integrated circuit, comprising: a general wiring design step of allocating; and a detailed wiring design step of wiring a detailed wiring path based on the general wiring path, wherein the general wiring design step is performed for each of the general wiring grids. Estimating the number of wires that can pass through the general wiring grid as a first wiring congestion degree, and wiring at a general wiring grid level such that the wiring congestion degree of the general wiring grid is uniform based on the first wiring congestion degree. Determining a route, and obtaining the second wiring congestion degree by adding the determined wiring path to the first wiring congestion degree, and setting the second wiring congestion degree as the wiring congestion degree at the time of the subsequent general wiring path allocation. Characterized by being configured to be used.

Further, according to the present invention, the first wiring congestion degree of the general wiring grid is determined from the number of wiring tracks prepared on one side of the general wiring grid or a boundary of another side intersecting with the one side. The number of passable wiring tracks obtained by subtracting the number of obstacles of the wiring passing on the left side or lower side of the general wiring grid is defined as the wiring capacity, and the number of general wiring passing on the left side or lower side is determined as the wiring usage. It is characterized by being.

According to the present invention, the detailed wiring design step includes a vertical detailed wiring step of allocating a vertical segment and a horizontal detailed wiring step of allocating a horizontal segment. The vertical detailed wiring step includes a step of extracting the vertical segments belonging to each of the vertical general wiring areas, and dividing the vertical general wiring area into two for the extracted vertical segments N times to the level of the wiring track. Repeatedly obtaining a third wiring congestion degree of an Nth Nth general wiring grid newly generated every two divisions; and dividing the vertical segments in the Nth Nth vertical general wiring area. Determining a vertical detailed wiring route by attaching the vertical segment, and dividing the vertical segment when the vertical segment occurs. Characterized by a step of generating a segment.

Further, the automatic wiring method for a semiconductor integrated circuit according to the present invention comprises a general wiring step of wiring a schematic wiring path over the entire surface of the semiconductor integrated circuit, a vertical detailed wiring step and a horizontal detailed wiring step based on the schematic wiring path. In the automatic wiring method for a semiconductor integrated circuit having the vertical detailed wiring step, the vertical detailed wiring step includes: Extracting the belonging vertical segment, and repeating the extracted vertical segment twice in the vertical general wiring area N times up to the level of the wiring track, and is newly generated for each of the two divisions. A wiring congestion degree calculating step of calculating the wiring congestion degree of the Nth general wiring grid, and a vertical segment allocated to the left and right divided areas The vertical congestion degree is determined by the length of the N-th vertical segment so that the vertical congestion degree obtained from the length of the vertical segment is uniform, and the two vertical segments having different end points and starting point Y coordinates that are as different as possible do not coincide with each other. Determining a vertical detailed wiring route by allocating to a vertical general wiring area; and generating a horizontal segment when the vertical segment is divided at the time of the two divisions. Features.

[0017]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a diagram showing an example of a semiconductor integrated circuit chip to be subjected to the method of automatically wiring a semiconductor integrated circuit according to the present invention. In the figure, 1 is a semiconductor chip, 2 is a terminal, 3 is a cell, 4 is a cell column, 5 is a net, and 6 is a wiring prohibited area (for example, RAM or the like). FIG. 7 is a flowchart showing processing steps of the automatic wiring method for a semiconductor integrated circuit according to the present invention. FIG. 8 is a layout diagram showing vertical and horizontal segments of the automatic wiring method for a semiconductor integrated circuit according to the present invention.
9 to 11 are layout diagrams showing vertical detailed wiring processing of the automatic wiring method for a semiconductor integrated circuit according to the present invention.

As shown in FIG. 7, the wiring processing of the semiconductor integrated circuit (S102) according to the present invention is performed by the general wiring design (S102).
103) and detailed wiring design (S104).

In the schematic wiring design (S103), first, as shown in FIG. 8, the inside of the semiconductor integrated circuit chip 1 is divided into meshes, and the general wiring grids 7 are set (S105). The number of wiring tracks that can be passed is obtained by subtracting the number of wiring obstacles passing on the left or lower side of the schematic wiring grid 7 from the number of wiring tracks that can pass on the boundary of the left side or the lower side (one side or another side intersecting the one side). Is used as the wiring capacity, and the first wiring congestion degree is calculated using the approximate number of wirings passing on the left side or the lower side as the wiring usage (S106).

Next, wiring routes at the approximate wiring grid level are determined so that the wiring congestion degree becomes uniform, and these are divided into vertical and horizontal components, which are referred to as a vertical segment 14 and a horizontal segment 15, respectively ( S10
7). Further, the second route congestion degree is obtained by adding the determined route to the wiring congestion degree in S106 (S10).
8), which is used as the degree of wiring congestion at the time of subsequent rough wiring path assignment. Further, the above-described processing of S106 to S108 is performed until there is no net having an undetermined general wiring route (S109).

The detailed wiring design includes a vertical detailed wiring step (S110) for allocating the vertical segments 14 as shown in FIG. 8 and a horizontal detailed wiring step (S111) for allocating the horizontal segments 15 to the wiring channel region. ).

In the vertical detailed wiring step of S110, the same vertical general wiring direction area P as shown in FIG. 9B is used for the vertical segments in which the upper and lower wiring channels shown in FIG. Are extracted as shown in FIG. 9A (S112). Next, a vertical general wiring area P as shown in FIG.
9 while avoiding the wiring failure such as the wiring prohibition existing in FIG.
The vertical segment shown in FIG. 10A is applied to the vertical general wiring region P shown in FIG.
As shown in (b) and (c), the allocation of the vertical segment by the two-division process (S113) is repeated N times to the wiring track level (S114).

In the two-division process, the third wiring congestion degree of the N-th N-th general wiring grid newly generated at each division is calculated (S115), and the (N-1) -th vertical general wiring area is calculated. The vertical segment belonging to the Nth vertical wiring area is so arranged that the degree of wiring congestion is uniform and the end points and start point Y coordinates of two different vertical segments that are as different as possible do not coincide with each other. (S
116).

If the vertical segment is divided in step S116 as shown by the vertical segment b in FIG. 11, a horizontal segment generated by the division is generated (S117).

In the horizontal detailed wiring process of S111, S
At 110, a wiring path is determined on the Y-coordinate of the horizontal segment in which the X-coordinate of the start point and the end point is determined so that no wiring short-circuit occurs, and the wiring process of the semiconductor integrated circuit is completed.

According to the present invention, by applying the above means, in the vertical detailed wiring processing, each time the division of the general vertical wiring area and the allocation of the vertical segments progress,
Since the location of the main line due to the bend and the degree of horizontal wiring congestion at the location of the bend can be known, it is possible to allocate a detailed vertical wiring route while avoiding the occurrence of vertical restrictions and the wiring congestion in detail. This makes it possible to reduce the size and speed of the semiconductor integrated circuit.

Further, it is possible to quickly obtain an accurate detailed wiring route based on the detailed wiring congestion degree, and it is possible to reduce the processing time required for the detailed wiring design and the processing time for the entire layout design.

[0029]

As described above, according to the method for automatically wiring a semiconductor integrated circuit of the present invention, by performing the above-mentioned means, in the vertical detailed wiring processing, the division of the vertical general wiring area and the vertical Each time segment allocation progresses, the location of the main line due to the bend and the degree of horizontal wiring congestion at the location of the bend can be known, so the detailed vertical wiring route is divided while avoiding the occurrence of vertical restrictions and wiring congestion in detail. Can be attached.

Thus, the size and speed of the semiconductor integrated circuit can be reduced. Further, it is possible to quickly obtain an accurate detailed wiring route based on the detailed wiring congestion degree, and it is possible to reduce the processing time required for the detailed wiring design and the processing time for the entire layout design.

[Brief description of the drawings]

FIG. 1 is a diagram showing an example of a semiconductor integrated circuit chip to which a method for automatically wiring a semiconductor integrated circuit according to the present invention is applied.

FIG. 2 is a layout diagram showing a schematic wiring design process of a conventional automatic wiring method for a semiconductor integrated circuit.

FIG. 3 is a layout diagram showing a schematic wiring design step of a conventional automatic wiring method for a semiconductor integrated circuit.

FIG. 4 is a layout diagram showing a detailed wiring design step of a conventional automatic wiring method for a semiconductor integrated circuit.

FIG. 5 is a layout diagram for explaining a problem associated with the occurrence of vertical constraints due to a conventional automatic wiring method for a semiconductor integrated circuit.

FIG. 6 is a layout diagram for explaining a problem associated with the occurrence of vertical constraints due to a conventional automatic wiring method for a semiconductor integrated circuit.

FIG. 7 is a flowchart showing the entire process of the automatic wiring method for a semiconductor integrated circuit according to the present invention.

FIG. 8 is a layout diagram showing vertical and horizontal segments in an automatic wiring method for a semiconductor integrated circuit according to the present invention.

FIG. 9 is a layout diagram showing vertical detailed wiring processing of the automatic wiring method of the semiconductor integrated circuit according to the present invention.

FIG. 10 is a layout diagram showing vertical detailed wiring processing of the automatic wiring method for a semiconductor integrated circuit according to the present invention.

FIG. 11 is a layout diagram showing a vertical detailed wiring process of the automatic wiring method of the semiconductor integrated circuit according to the present invention.

[Explanation of symbols]

1 ... Semiconductor chip, 2 ... Terminal, 3 ... Cell, 4 ... Cell row,
5: Net, 6: RAM, 7: Schematic wiring grid, 8: Detailed wiring, 9: Main line, 10: Branch line, 11: Branch line passing point, 12
... horizontal segments, 13 ... unwired, 14 ... vertical segments, 15 ... horizontal segments.

Claims (4)

[Claims] 1. A general wiring design step of setting a general wiring grid partitioned in a mesh shape on the entire surface of a semiconductor integrated circuit chip and allocating a general wiring path, and a detailed wiring for wiring a detailed wiring path based on the general wiring path. In the automatic wiring method of a semiconductor integrated circuit having a design step, the schematic wiring design step,
Estimating the number of wires that can pass through the general wiring grid as the first wiring congestion degree for each of the general wiring grids, and making the wiring congestion degree of the general wiring grid uniform based on the first wiring congestion degree. Determining a wiring path at a schematic wiring grid level; and determining the determined wiring path as the first wiring path.
A schematic wiring method for a semiconductor integrated circuit, wherein a second wiring congestion degree is obtained by adding to the wiring congestion degree, and is used as a wiring congestion degree at the time of subsequent allocation of a schematic wiring path. 2. The first wiring congestion degree of the general wiring grid passes on the left side or lower side of the general wiring grid based on the number of wiring tracks prepared on the left side or lower side boundary of the general wiring grid. 2. The semiconductor integrated circuit according to claim 1, wherein the number of traversable wiring tracks obtained by subtracting the number of wiring obstacles is a wiring capacity, and the approximate number of wirings passing on the left side or the lower side is a value obtained as a wiring usage amount. Automatic circuit wiring method. 3. The detailed wiring design step includes a vertical detailed wiring step of allocating vertical segments and a horizontal detailed wiring step of allocating horizontal segments.
And the vertical detailed wiring step includes a step of extracting the vertical segments belonging to each of the vertical schematic wiring areas, and dividing the vertical vertical wiring area into two with respect to the extracted vertical segments to a wiring track level. N
Repetition times, obtaining a third wiring congestion degree of the Nth general wiring grid newly generated every two divisions, and allocating the vertical segments in the Nth vertical general wiring area 2. The semiconductor integrated circuit according to claim 1, further comprising: a step of determining a vertical detailed wiring route; and a step of, when division of the vertical segment occurs, generating a horizontal segment generated by the division. Automatic wiring method. 4. A rough wiring step of setting a rough wiring grid partitioned in a mesh on the entire surface of the semiconductor integrated circuit chip and allocating a rough wiring path, and a fine wiring step of wiring a fine wiring path based on the rough wiring path. Determining an approximate wiring path so that the degree of wiring congestion of the general wiring grid obtained in the general wiring step is uniform, wherein the vertical wiring is determined based on the general wiring path. Determining a detailed direction wiring path; determining a detailed horizontal wiring path based on the detailed vertical wiring path; and determining the detailed vertical wiring path, comprises: A step of extracting vertical segments belonging to the area, a step of dividing the vertical schematic wiring area into two to a wiring track level, and updating the degree of wiring congestion for each division And a step of assigning a new segment every time the vertical segment is divided, and a step of generating a horizontal segment when the vertical segment is divided. Automatic wiring method.