JP2001344904A - Data reproducing device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a data reproducing device accelerating access after data is outputted normally from an ACIRC decoding circuit after track access. SOLUTION: The device is provided with a memory means 6 for temporarily holding data read from a recording medium, a memory control means 72 for controlling writing and reading of data by generating the address of the means 6, a data quality detecting means 71 for detecting the quality of the read data, an address holding means 74 for holding a written address when a data coming to have a quality equal to or higher than a prescribed one is held in the means 6, a comparing means 75 which compares the read address of data outputted from the means 6 with the address held by the means 74 and outputs a data starting signal in coincidence, and a signal processing means 18 for signal- processing the output of the means 6 to reset prescribed processing by the data starting signal.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data reproducing apparatus, and more particularly to a data reproducing apparatus used for a mini disk (hereinafter, referred to as MD).

[0002]

2. Description of the Related Art In recent years, compact disks (hereinafter referred to as C
MD) which is smaller and capable of repeated recording
Has been commercialized. The MD can record a music signal at the same time as a CD despite its small diameter of about 1/2 that of a conventional CD (“Nikkei Electronics [Nikkei B]
Company P] No. 528 (1991.5.27), pp. 106 to 107 ”) and“ Radio Technology [Radio Engineering Co., Ltd.] (June 1991) pp. 9 to 12 ”).

Hereinafter, a general MD reproducing apparatus will be described with reference to the drawings.

FIG. 5 is a block diagram showing the configuration of a general MD playback apparatus. FIG. 5A shows the entire configuration.
(B) shows the internal configuration of the ACIRC decoding circuit. 6 is an explanatory diagram of output data of the ACIRC decoding circuit shown in FIG. 5, FIG. 7 is a transition diagram of a detection mode in the ACIRC decoding circuit shown in FIG. 5, and FIG. 8 is an MD shown in FIG.
FIG. 14 is an explanatory diagram of a sync detection operation in the playback device.

As shown in FIG. 1A, this MD reproducing apparatus includes a magneto-optical disk 1 having a magnetic film (hereinafter abbreviated as a disk), a spindle motor 2 for driving the disk 1 to rotate, and a rotating disk. The disk 1 is irradiated with a laser beam, the laser beam is reflected by the magnetic film of the disk 1, a magneto-optical signal is read from the returned beam, and an RF signal (RF: Radio Frequency) is read.
y), an RF amplifier 4 for amplifying an RF signal to an appropriate level, and an amplified RF
EFM signal extracted from the signal (EFM: Eight
to Fourteen Modulation)
An EFM demodulation circuit 5 for performing FM demodulation, a correction memory 6 for temporarily storing EFM demodulated data, and appropriately reading the data stored in the correction memory to detect and correct errors and to perform deinterleaving. An ACIRC decoding circuit 7, a sync detection circuit 8 for detecting a synchronization signal from a data string output from the ACIRC decoding circuit 7,
A shock-proof memory 9 (hereinafter referred to as SP memory) of about 16 Mbits for temporarily holding output data of the sync detection circuit 8 and preventing sound skipping due to vibration or the like.
And an SP memory control circuit 10 for controlling the input and output of data to and from the SP memory 9, and an ATRAC (registered trademark) for expanding the data read from the SP memory 9 and outputting a digital audio signal. A decoding circuit 11, an optical pickup moving circuit 12 for moving the optical pickup 3 in a radial direction of the disk 1, a servo control circuit 13 for servo controlling the spindle motor 2 and the optical pickup moving circuit 12, and the optical pickup 3; A system control circuit 14 for controlling each circuit of the MD playback device, a key input unit 15 for giving an external operation command to the system control circuit 14, and a display state of the MD playback device. Display section 16
And these components are connected as shown.

With this configuration, the servo control circuit 13 receives the RF signal from the RF amplifier 4 and
A control signal for controlling the optical pickup moving circuit 12 and the optical pickup 3 is extracted and sent out, and the tracking servo control is performed so that the laser beam does not deviate from the recording track axis of the disk 1.
A tracking ON signal indicating that tracking is ON is output to the decoding circuit 7. Further, the servo control circuit 13 performs spindle servo control by sending out a control signal for rotating the spindle motor 2 to a predetermined speed based on a clock signal included in the EFM signal from the EFM demodulation circuit 5. The system control circuit 14 can send a control signal to each section of the apparatus based on an operation command input from the outside to the key input section 15 to perform a high-speed search operation, a random access play operation, and the like.

Next, referring to FIGS. 5 (b), 6 and 7,
The operation of the ACIRC decoding circuit 7 and the sync detection circuit 8 related to the gist of the present invention will be described in more detail.
As shown in FIG. 5B, the ACIRC decoding circuit 7
Comprises a data processing circuit 71, an address generation circuit 72, and an address initialization circuit 73.

Here, the data processing circuit 71 constitutes a data quality detecting means, and writes data input from the EFM demodulation circuit 5 to the correction memory 6 and reads data from the correction memory 6 to detect errors. This is a circuit which corrects and corrects the data, writes it again in the correction memory 6, reads out data from the correction memory 6 and outputs it to the sync detection circuit 8. The address generation circuit 72 is a circuit that generates an address for writing data to the correction memory 6 and an address for reading data. The address initialization circuit 73 includes the correction memory 6
When the data held in the memory overflows or underflows, or when the EFM signal can be normally extracted, for example, the tracking ON signal from the servo control circuit 13 changes from the tracking OFF state to the OFF state.
This circuit initializes the address of the correction memory 6 when the state becomes N. Although various methods of initializing the address of the correction memory 6 are conceivable, here, the initialization of the read address for outputting data to the sync detection circuit 8 is not performed, and the address for writing the data from the EFM demodulation circuit 5 is not performed. Is initialized to change to the most suitable address. Since the data input to the ACIRC decoding circuit 7 is interleaved by about 1.1 sectors, about 1.1 sectors are required for deinterleaving, and the shortest time from the input to the output of the ACIRC decoding circuit 7 is short. However, the delay is about 1.1 sectors. Here, for simplicity of description, it is assumed that the ACIRC decoding circuit 7 has a delay of 1.5 sectors.

The structure of the data transferred from the ACIRC decoding circuit 7 to the sync detection circuit 8 is as shown in FIG. 6, and the data unit is called a sector. , Abbreviated as “sink”), and the sector address is added, and the result is guided to the sync detection circuit 8. The sync detection circuit 8 detects a sector address following the sync and transfers the sector address to the system control circuit 14. The sync detection circuit 8 regards only the sync detected during the period when the internal detection window is H, as a sync. The detection window has two types of detection modes, a mode 1 in the case of full opening (always H) and a mode 2 in which a detection window of a predetermined length is set during a period in which a sync is likely to be detected. Is shown in FIG. Mode 1 is a mode in which the detection window is fully open, and when the distance between the detected syncs is just one sector length,
Move to mode 2. If the sync is not detected twice consecutively in mode 2, the mode shifts to mode 1.

Next, the sync detection operation will be described with reference to FIG. FIG. 8 shows various signals when the track access is performed after the sector A and the sector B are reproduced, and after the access is completed, the reproduction is started from the middle data of the sector A ′ and the reproduction is performed with the sector B ′ and the sector C ′. 3 shows the waveforms of FIG. In FIG. 8, (a) shows input data of the ACIRC decoding circuit 7, and a shaded portion indicates a sync, and a broken line portion indicates that data is disturbed due to tracking being lost during access and after completion of access. I have. (B) shows tracking O from the servo control circuit 13.
In the N signal, H indicates the tracking ON state and L indicates the tracking OFF state, and the track jump period is L. (C) is an initialization signal of the correction memory 6, (d)
Is output data of the ACIRC decoding circuit 7.
In (d), as in (a), the shaded portion indicates a sync, and the broken line portion indicates that tracking is lost during access and after access is completed, and data is disturbed. (E) shows a detection window of the sync detection circuit 8, and an H period is a period in which sync detection is possible. (F)
Is a sync detection signal, and H indicates that a sync was detected within the detection window. (G) shows the detection mode of the detection window.

If track access is performed during data reproduction, the input data (a) of the ACIRC decoding circuit 7 is disturbed, and the output data (d) of the ACIRC decoding circuit 7 is also disturbed with a delay of 1.5 sectors. After the track access is completed, even if the output data (d) of the ACIRC decoding circuit 7 becomes normal data with a delay of 1.5 sectors, the sync position of the output data (d) of the ACIRC decoding circuit 7 and the detection window (e) , The sync detection signal (f) is not output.

When the sync is not detected twice, the detection mode (g) shifts from the mode 2 to the mode 1, and the detection window (e) is fully opened. When the detection window (e) is fully opened, the sync can be detected. When the sync is detected twice, the detection mode (g) becomes the mode 2, and thereafter, the sync can be stably detected.
The MD playback device shown in FIG. 7 performs a normal playback operation.

[0013]

However, in such a configuration, the mode is not shifted from the mode 2 to the mode 1 until the sink is detected twice consecutively, so that when the access is completed in a short time as shown in FIG. However, there is a problem that even when data is normally output from the ACIRC decoding circuit 7, a state in which a sync cannot be detected continues for a while.

An object of the present invention is to solve the above-mentioned conventional problems, and to improve the speed of access after data is normally output from an ACIRC decode circuit after track access. It is an object to provide a playback device.

[0015]

According to the present invention, there is provided a data reproducing apparatus comprising: reading means for reading data stored in a recording medium; memory means for temporarily holding data read by the reading means; A memory control unit for generating a write address and a read address of the memory unit to control writing and reading of data, a data quality detection unit for detecting the quality of data read by the reading unit, and the data quality detection unit Address holding means for holding a write address when data whose data quality is equal to or more than a predetermined value is held in the memory means, a read address of data output from the memory means, and an address held by the address holding means And comparing means for outputting a data start signal if they match, Serial signal processing the output of the memory means, and intended to be composed of a signal processing means for resetting the predetermined processing by the data start signal, also,
Reading means for reading data stored in a recording medium, memory means for temporarily holding data read by the reading means, and writing and reading of data by generating write and read addresses of the memory means Memory control means for controlling the data quality, data quality detection means for detecting the quality of data read by the reading means, and data whose data quality has become equal to or higher than a predetermined value by the data quality detection means are stored in the memory means. Address holding means for holding the write address when the data is read, and comparing the read address of data output from the memory means with the address held by the address holding means, and outputting a data start signal if they match. Means and the data quality detecting means so that the data quality falls below a predetermined value. A data invalidating unit that invalidates the output of the memory unit during a period from when the data start signal is detected until the data start signal is output, and a signal processing unit that performs signal processing on the output of the data invalidating unit. Things.

According to the present invention, after the track access,
The system control circuit can read the sector address in a short time, so that the position of the optical pickup on the disk can be known. Higher speed can be achieved.

[0017]

Embodiments of the present invention will be described below with reference to the drawings. Note that the same parts as those of the related art are denoted by the same reference numerals, and detailed description thereof will be omitted.

(Embodiment 1) FIG. 1 is a block diagram showing the configuration of an MD reproducing apparatus according to Embodiment 1 of the present invention. FIG. 1A shows the entire configuration, and FIG.
3 shows the internal configuration of the RC decoding circuit. FIG. 2 shows FIG.
FIG. 41 is an explanatory diagram of a sync detection operation in the MD playback device shown in FIG.

In the first embodiment, the parts other than the internal structure of the ACIRC decode circuit and the sync detection circuit are the same as those of the above-mentioned conventional one, so that the description thereof will be omitted, and the emphasis will be placed on these ACIRC decode circuit and the sync detection circuit. Will be described.

The internal configuration of the ACIRC decoding circuit 17 is as shown in FIG. 1B. In addition to the configuration of the conventional ACIRC decoding circuit 7, the data from the EFM demodulation circuit 5 is initialized when the address is initialized. An address holding circuit 74 for holding an address to be written, and an address holding circuit 7
4 is different from that of the first embodiment in that a match detection circuit 75 that outputs a data start signal when the stored address is compared with an address from which data to be output to the sync detection circuit 18 is compared is found.

With such a configuration, for example, when the tracking ON signal changes from OFF to ON while data is being written from the EFM demodulation circuit 5 to the correction memory 6,
An address initialization signal is output from the address initialization circuit 73. When the address initialization signal is output, when the address initialization signal is output, that is, when the tracking
The address when the data input from the EFM demodulation circuit 5 is written to the correction memory 6 at the time of N is held in the address holding circuit 74. Thereafter, the data is subjected to error correction and deinterleaving, and is read from the correction memory 6 after 1.5 sectors, and at the same time, the address held in the address holding circuit 74 by the match detection circuit 75 matches the read address, and the data start signal is output. Is output.

That is, when the tracking ON signal changes from OFF to ON, the data written to the correction memory 6 at that time is read out 1.5 sectors later, and at the same time, a data start signal is output.

The sync detection circuit 18 forcibly shifts the detection mode from mode 2 to mode 1 when a data start signal is input from the ACIR decode circuit 17 in addition to the function of the conventional sync detection circuit 8. It has the function to make it.

The sync detection operation of the MD reproducing apparatus configured as described above will be described with reference to FIG. FIG. 2 shows a case where the track access is performed after the sectors A and B are reproduced, and after the track access is completed, the reproduction is started from the data in the middle of the sector A 'and the reproduction is performed with the sectors B' and C '. 4 shows a signal waveform.

In FIG. 2, (a) shows the input data of the ACIRC decoding circuit 17, and (b) shows the servo control circuit 13.
, H indicates a tracking ON state, and L indicates a tracking OFF state.
(C) is an initialization signal of the correction memory 6, and (d) is an ACIR.
This is output data of the C decode circuit 17. (A),
In (d), the shaded portion indicates a sync, and the broken line portion indicates that tracking is deviated during access and after completion of access, and data is disturbed. (E) shows a data start signal generated by the ACIRC decoding circuit 17, and (f) shows a detection window of the sync detection circuit 18, where the H period is a period during which sync detection is possible. (G) is a sync detection signal, and H indicates that a sync was detected within the detection window. (H) shows the mode of the detection window.

When track access is performed during data reproduction, the input data (a) of the ACIRC decode circuit 17
Is disturbed and the ACIRC decoding circuit 1 is delayed by 1.5 sectors.
7, the output data (d) also starts to be disturbed. However, after the track access is completed, the output data (d) of the ACIRC decoding circuit 17 becomes normal data with a delay of 1.5 sectors, and at the same time, a data start signal is output from the ACIRC decoding circuit 17. The mode (h) is forcibly shifted from the mode 2 to the mode 1, and the detection window (f) is fully opened. Detection window (f)
Becomes fully open, the sync can be detected in all the periods. When the sync is detected twice, the detection mode (h) becomes the mode 2, and thereafter, the sync can be stably detected.

As described above, according to the present embodiment, the normal data is input to the sync detection circuit 18 and the data start signal is input at the same time, and the detection window can be fully opened. Can be detected from the first sync that has become
Since the system control circuit 14 can read the sector address in a short time, the position of the optical pickup 3 on the disk 1 can be known. Speed up to the target sector address can be achieved.

(Embodiment 2) FIG. 3 is a block diagram showing the configuration of an MD reproducing apparatus according to Embodiment 2 of the present invention. FIG. 3 (a) shows the overall configuration, and FIG.
FIG. 3 is a block diagram illustrating an internal configuration of a C decode circuit. FIG. 4 is an explanatory diagram of a sync detection operation in the MD playback device shown in FIG.

The present embodiment is the same as the conventional one except for the configuration of the ACIRC decode circuit and the data mask circuit, and therefore the description thereof is omitted.
The CIRC decode circuit and the data mask circuit will be mainly described.

The internal configuration of the ACIRC decode circuit 27 is as shown in FIG.
Compared with the RC decoding circuit 17, tracking is O
The difference is that a gate generation / generation circuit 76 is provided which outputs a data mask signal in which a period from when the FF becomes the FF until the coincidence detection circuit 75 outputs the data start signal is H. Reference numeral 28 denotes a data mask circuit which forcibly sets input data to a fixed value, for example, 0 while the data mask signal is at H level.
This is a circuit for fixing data.

A description will now be given of the sync detection operation of the MD reproducing apparatus configured as described above. FIG. 4 is an explanatory view showing that the track access is performed after reproducing the sectors A and B, and after the access is completed, the reproduction is started from the middle data of the sector A ′, and the reproduction is performed with the sectors B ′ and C ′. It shows the waveforms of various signals when this operation is performed.

FIG. 4A shows ACIRC deco.
(B) is the servo control circuit 13
, H indicates a tracking ON state, and L indicates a tracking OFF state.
(C) is an initialization signal of the correction memory 6, and (d) is an ACIR.
This is output data of the C-decode circuit 27. (E) is AC
The data start signal generated in the IRC decoding circuit 27, (f) is a data mask signal output from the ACIRC decoding circuit 27, and (g) is an output from the data mask circuit 28. In each of (a), (d), and (g), the shaded portion indicates a sync, and the broken line portion indicates that data is disturbed during access and after the access is completed and tracking is lost. (H) shows a detection window of the sync detection circuit 8, and an H period is a period during which sync detection is possible. (I) is a sync detection signal, and H indicates that a sync was detected within the detection window.
(J) shows the mode of the detection window.

When track access is performed during data reproduction, the input data (a) of the ACIRC decode circuit 27
, And the output data (d) of the ACIRC decoding circuit 27 starts to be disturbed with a delay of 1.5 sectors. However, the data mask signal (f) becomes H at the same time as the start of the track access.
H continues until the output data (d) of the ACIRC decode circuit 27 becomes normal, and the output (g) of the data mask circuit 28, that is, the input data of the sync detection circuit 8 is fixed at 0, and the sync cannot be detected. Becomes Therefore, when the data becomes normal, the detection mode (j) shifts to mode 1 and the detection window (h) is fully opened, so that sync detection is possible.

As described above, according to the present embodiment, since the data held in the correction memory 6 can be invalidated simultaneously with the track access, the detection mode (j)
Can shift to the mode 1 faster than the conventional one, and the sync can be detected in a short time. Further, after the track access, the system control circuit 14 can read the sector address in a short time, so that the position of the optical pickup 3 on the disk 1 can be known in a short time, and when this is different from the access target sector address. By immediately re-accessing the data, the speed up to the target sector address can be achieved.

In this embodiment, the data is forcibly fixed to 0. However, since the pattern of the sync is not a fixed value, the data is not limited to 0 but may be a fixed value. In this embodiment, the data is invalidated by forcibly fixing the data to 0. However, the ACIRC decoding circuit outputs not only the data but also an error flag indicating the reliability of the data, and the sync detection circuit outputs the error flag. When the sink is detected in consideration of the above, the data may be invalid data by setting an error flag to an error.

[0036]

As described above, according to the present invention, it is possible to increase the speed of access after data is normally output from the ACIRC decode circuit after track access. Is obtained.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an MD reproducing apparatus according to a first embodiment of the present invention.

FIG. 2 is an explanatory diagram of a sync detection operation in the MD playback device shown in FIG.

FIG. 3 is a block diagram showing a configuration of an MD reproducing apparatus according to a second embodiment of the present invention.

4 is an explanatory diagram of a sync detection operation in the MD playback device shown in FIG.

FIG. 5 is a block diagram showing the configuration of a general MD playback device.

FIG. 6 is an explanatory diagram of output data of the ACIRC decoding circuit shown in FIG. 5;

FIG. 7 is a transition diagram of a detection mode in the ACIRC decoding circuit shown in FIG. 5;

8 is an explanatory diagram of a sync detection operation in the MD playback device shown in FIG.

[Explanation of symbols]

 Reference Signs List 1 disc 2 spindle motor 3 optical pickup 4 RF amplifier 5 EFM demodulation circuit 6 correction memory 7, 17, 27 ACIRC decoding circuit 8, 18, 28 sync detection circuit 9 shock proof memory (SP memory) 10 SP memory control circuit 11 ATRAC decoding Circuit 12 Optical pickup moving circuit 13 Servo control circuit 14 System control circuit 15 Key input unit 16 Display unit 71 Data processing circuit 72 Address generation circuit 73 Address initialization circuit 74 Address holding circuit 75 Match detection circuit 76 Gate generation circuit

Claims (2)

[Claims] 1. A reading means for reading data stored on a recording medium, a memory means for temporarily holding data read by the reading means, and a write address and a read address for the memory means. Memory control means for controlling writing and reading of data,
Data quality detection means for detecting the quality of the data read by the reading means; and a write address when data whose data quality has reached a predetermined level or more by the data quality detection means is stored in the memory means. Address holding means for comparing the read address of data output from the memory means with the address held by the address holding means, and outputting a data start signal if they match, and an output of the memory means And a signal processing means for resetting a predetermined process by the data start signal. 2. A reading means for reading data stored on a recording medium, a memory means for temporarily holding data read by the reading means, and a write address and a read address for the memory means. Memory control means for controlling writing and reading of data,
Data quality detection means for detecting the quality of the data read by the reading means; and a write address when data whose data quality has reached a predetermined level or more by the data quality detection means is stored in the memory means. Address holding means for comparing the read address of data output from the memory means with the address held by the address holding means, and outputting a data start signal if they match, and the data quality detecting means A data invalidating unit for invalidating the output of the memory unit and a signal processing of the output of the data invalidating unit during a period from when it is detected that the data quality has become equal to or lower than a predetermined value until a data start signal is output. A data reproducing apparatus comprising: signal processing means.