JP2001343966A - Display coordinate transforming circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To speedily conduct rotational or left and right reversal processes at a 90 deg. unit for a display image. SOLUTION: The circuit is provided with an input data buffer circuit 102, a memory interface 103, an address counter 104, a data rearranging circuit 105, an output data buffer circuit 106 and a memory 107. The memory interface 103 conducts burst transfers of the pixel data in terms of a block unit that is constituted of a prescribed number of pixels in the longitudinal and lateral directions, respectively. The memory 107 has a storage region made up with plural banks. Writing and reading of one burst length data are made possible into and from each bank. The circuit 105 rearranges the pixel data in terms of the block unit in accordance with the mode data that indicate rotational display or left and right reversal display in the 90 deg. unit.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display coordinate conversion circuit, and more particularly, to a display coordinate conversion circuit for rotating an image for one screen in units of 90.degree.

[0002]

2. Description of the Related Art A state in which a display device is rotated 90 ° to the left (+
(90 ° rotation), 90 ° clockwise rotation (-90 ° rotation), 180 ° rotation, and mirrored image In, it is necessary to transform the display coordinates of the pixel data constituting the image for one screen so as to cancel the rotation and the horizontal inversion so that the displayed image looks like the same arrangement as the original image. For example, when the display device displaying the original image shown in FIG. 3A is rotated by + 90 °, as shown in FIG. 3B, the image is shifted by −90 so as to cancel the + 90 ° rotation of the display device. ° It is necessary to input to the display device after rotating. Similarly, when the display device is rotated by −90 °, it is necessary to rotate the image by + 90 ° as shown in FIG. 3C, and when the display device is rotated by 180 °,
As shown in FIG. 3D, it is necessary to rotate the image by 180 °. When the image displayed on the display device is reflected on a mirror and viewed, as shown in FIG. 3D, the image is horizontally inverted so as to cancel the left-right inversion by the mirror, and then input to the display device. There is a need.

Conventionally, as a method of rotating or horizontally reversing such a display image in units of 90 °, pixel data for one screen is written in a memory, and the pixel data is adjusted in accordance with the rotated or horizontally reversed image. A method of reading and outputting to the display device so as to be in the arrangement order after conversion, and writing pixel data to an address corresponding to an image after rotation or left / right inversion when writing pixel data for one screen in the memory, There has been known a method of reading data in the display order and outputting the data to a display device.

[0004]

However, a method of reading out pixel data from the above-mentioned memory so as to be arranged in a converted order, or writing pixel data to an address corresponding to an image after rotating or horizontally reversing the memory. In the method, since the read or write address of the memory is not continuous, it is necessary to specify the address of the memory for each pixel. For example, when one screen is composed of 800 × 600 pixels, the number of times of addressing needs to be 480,000 times, and there is a problem that it takes time to perform the rotation or the left / right inversion processing. SUMMARY OF THE INVENTION It is an object of the present invention to provide a display coordinate conversion circuit capable of performing high-speed rotation or horizontal reversal processing in units of 90 °.

[0005]

In order to solve the above-mentioned problems, a display coordinate conversion circuit according to the present invention has an input data buffer circuit for storing input pixel data, and is transferred from the input data buffer circuit. A first memory for storing the pixel data, a data rearranging circuit for rearranging the pixel data transferred from the first memory in a predetermined order and outputting the data, and a rearranged data output from the data rearranging circuit; A second memory for storing the pixel data of the second order, an output data buffer circuit for storing and outputting the rearranged pixel data transferred from the second memory, and writing and reading of the first and second memories. Memory control means for controlling the memory, wherein the memory control means bursts pixel data in units of blocks each having a predetermined number of pixels in the vertical and horizontal directions. Feed, the first and second memory has a storage area comprising a plurality of banks, and each bank 1
The data rearrangement circuit is configured to be capable of writing and reading data of a burst length, and is configured to rearrange pixel data in units of blocks according to mode data indicating rotation display or horizontal reversal display in units of 90 °. It is characterized by having.

In this case, one configuration example of the memory control means is as follows.
During the burst transfer, the transfer preparation of another bank is performed, and the bank is switched for each burst length to continuously perform the burst transfer of the pixel data in the block. Another configuration example of the memory control means is configured such that the number of vertical pixels of a block to be burst-transferred is equal to the number of banks of the first and second memories. One configuration example of the first memory and the second memory includes different storage areas of one semiconductor memory. In this case, one configuration example of the semiconductor memory is a synchronous DRAM (Synchronous DRAM).
Dynamic Random Access Memory) is used.

[0007]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows an embodiment of a display coordinate conversion circuit according to the present invention. The display coordinate conversion circuit includes an input data buffer circuit 102 and a memory interface 1.
03, address counter 104, and data rearranging circuit 1
05, an output data buffer circuit 106, and a memory 107. In this case, pixel data is externally input to the input data buffer circuit 102 as input data,
The mode data is input to the address counter 104 and the data rearranging circuit 105.

Address data used for burst transfer is input from the address counter 104 to the memory interface 103, and burst transfer from the input data buffer circuit 102 to the memory 107 via the memory interface 103, and data sorting circuit from the memory 107 Burst transfer to 105 and data rearranging circuit 105
And a burst transfer from the memory 107 to the output data buffer circuit 106 is possible. Further, the output data buffer circuit 106 is configured to output pixel data after coordinate conversion as output data.

Here, the memory 107 has a storage area composed of a plurality of banks, and can write and read data by burst transfer in which a plurality of data having continuous addresses are continuously transferred collectively and continuously by one address designation. The transfer preparation of another bank can be completed during burst transfer. In this embodiment, for example, as shown in FIG. 2, a synchronous DRAM (Synchr.
onous Dynamic Random Access Memory)
Each bank is used by being divided into an area a for storing pixel data after coordinate conversion and an area b for storing pixel data before coordinate conversion. The memory 107 can store at least one screen of pixel data in a storage area including the a areas (Aa, Ba, Ca, and Da) of all the banks, and stores the pixel data of each bank. b area (Ab, Bb, C-
b, Db) have a storage capacity capable of storing pixel data of at least a predetermined burst length.

[0010] The input data buffer circuit 102 is temporary storage means for temporarily storing input pixel data for a predetermined processing unit. In this case, the predetermined processing unit is obtained by dividing an image for one screen into blocks of the same configuration including a plurality of pixels in each of the vertical and horizontal directions.
In this block, the number of pixels in the vertical direction is the number of banks of the memory 107, and the number of pixels in the horizontal direction is a predetermined burst length. Since the input data buffer circuit 102 receives pixel data constituting an image for one screen in the same order as that scanned by the picture tube of the display device, that is, from left to right and from top to bottom, at least [ The number of display pixels in the horizontal direction (raster direction) of the display device × the number of pixels in the vertical direction in a predetermined processing unit] is sufficient. For example, a predetermined processing unit is constituted by a block composed of 16 pixels of 4 pixels in the vertical direction and 4 pixels in the horizontal direction.
In the case of display by a display device of 800 pixels × 800 pixels, the storage capacity of the input data buffer circuit 102 may be at least 800 pixels × 4 pixels of 3200 pixels.

The address counter 104 is a transfer address notifying unit that generates address data used for burst transfer of pixel data of a predetermined processing unit based on mode data input from the outside and outputs the address data to the memory interface 103. In this case, the address counter 10
Reference numeral 4 denotes an address conversion data table for an image rotated at -90 °, an address conversion data table for an image rotated at + 90 °, an address conversion data table for an image rotated at + 180 °, and an address conversion data table for an image rotated left and right. And selects and uses a data table to be used according to the mode data.

The memory interface 103 is based on address data output from the address counter 104,
Data transfer means for writing data to the memory 107 and reading data from the memory 107 by burst transfer of a predetermined burst length. In this case, since the memory interface 103 continuously writes or reads pixel data of a predetermined processing unit to or from the memory 107, the memory interface 103 completes the preparation for transfer to the next burst transfer target bank during the burst transfer. It is configured.

The memory interface 103 is used to transfer data from the input data buffer circuit 102 to the memory 107, transfer data from the memory 107 to the data rearranging circuit 105, and transfer data from the data rearranging circuit 105 to the memory
7 and the data transfer from the memory 107 to the output data buffer circuit 106 are controlled to be performed by burst transfer. The data transfer and control thereof, and the input of the address data output from the address counter 104 are performed via an address bus, a control bus, and a data bus (not shown).

The data rearrangement circuit 105 has an input register for storing pixel data before rearrangement and an output register for storing pixel data after rearrangement. Pixel data composed of a predetermined processing unit burst-transferred from the area b of the memory 107 by the memory interface 103 is stored in an input register, and then rearranged based on externally input mode data and stored in an output register. You. The rearranged pixel data is stored in the order displayed from the top of the output register, and is burst-transferred from the top of the output register to the area a of the memory 107 by the memory interface 103.

In this case, the input register and the output register are each composed of registers for the number of pixels in the vertical direction of a predetermined processing unit, and each register is configured to store pixel data for a predetermined burst length. . For example, assuming that a predetermined processing unit is a block composed of 16 pixels of 4 × 4 pixels, the input register and the output register are each composed of four registers capable of storing data of 4 pixels. Note that the data rearrangement circuit 105 has -9
It is possible to perform a 0 ° rotation image conversion, a + 90 ° rotation image conversion, a + 180 ° rotation image conversion, and a left / right inversion image conversion. It is configured as follows.

The output data buffer circuit 106 is burst-transferred from the area a of the memory 107 by the memory interface 103 in order to arrange the converted pixel data until it can be output in the same order as scanned by the picture tube of the display device. This is a temporary storage unit for temporarily storing pixel data composed of predetermined processing units. The output data buffer circuit 106 has a storage capacity capable of storing at least pixel data of [the number of display pixels in the horizontal direction (raster direction) of the display device × the number of vertical pixels in a predetermined processing unit].

Next, a coordinate conversion method of the display coordinate conversion circuit will be described with reference to the drawings. When the display device displaying the original image shown in FIG. 3A is installed in a state where the display device is rotated 90 ° to the left (+ 90 ° rotation), the display coordinate conversion circuit rotates the display device 90 ° to the right (−90 °). One screen so that the displayed image looks the same as the original image when it is installed at 90 ° rotation), when it is installed at 180 ° rotation, and when it is installed to look at the image reflected on the mirror. The display coordinates of the pixel data constituting the minute image are subjected to coordinate conversion so as to cancel the rotation and the left-right inversion, and the converted pixel data is output in the same order as that scanned by the image tube.

Here, FIG. 3 (b) shows the +90 of the display device.
FIG. 3 shows an image image obtained by performing a coordinate transformation for rotating the display coordinates of the image by −90 ° so as to cancel the rotation.
(C) shows an image image obtained by performing a coordinate transformation for rotating the display coordinates of the image by + 90 ° so as to cancel the −90 ° rotation of the display device. FIG. 3D shows that the display coordinates of the image are changed by 18 so as to cancel the 180 ° rotation of the display device.
FIG. 3 (e) shows an image image in the case of performing a coordinate transformation that rotates by 0 °, and FIG. 3 shows an image image when coordinate conversion is performed.

First, the arrangement of the pixel data constituting the image shown in FIG. 3 will be described. FIG. 4 is an explanatory diagram showing the arrangement of pixel data constituting the original image shown in FIG.
In this case, the original image shown in FIG. 3A is composed of pixel data arranged in a matrix, as shown in FIG.
a10 is arranged, and the rows are similarly changed to b0 to b10, c
0 to c10, d0 to d10, e0 to e10, f0 to f1
0, g0 to g10, and h0 to h10. Here, the display start position of the screen of the display device is a0,
The display end position is h10.

This display coordinate conversion circuit divides an image for one screen on which pixel data is arranged as shown in FIG. Is performed for each block, and then the display coordinates are converted by arranging the blocks so as to form an image after rotation or after left / right inversion. In this case, the data rearrangement circuit 105 rearranges the pixel data in the block, and the memory interface 103 determines the arrangement of each block based on the address data specified by the address counter 104.
This is done by writing to the area.

Next, a case where the pixel data arrangement is rotated by -90 °, which is performed when the display device is rotated by + 90 °, will be described with reference to FIG. Here, FIG. 5A shows the pixel data arrangement in the display device when the pixel data arrangement shown in FIG. 4 is rotated by -90 °, and the pixel data is shifted rightward from the display start position on the screen of the display device. H0 to a0 are arranged, and the rows are similarly changed to h1 to a1, h2 to a2, and h3.
~ A3, h4 ~ a4, h5 ~ a5, h6 ~ a6, h7 ~
a7, h8 to a8, h9 to a9, and h10 to a10 are arranged in this order. FIG. 5B shows the data rearranging circuit 10.
5 shows a pixel data arrangement before rearrangement and a pixel data arrangement after rearrangement. Here, a case will be described as an example where a block is a block composed of 16 pixels arranged in a matrix of 4 × 4 pixels and a block surrounded by a bold line in the upper left of FIG. 4 is converted.

First, rearrangement in the data rearrangement circuit 105 will be described. Here, taking as an example a case where a block surrounded by a bold line in the upper left of FIG. 4 is converted, this block includes a0 to a3 in the first row and b0 to b in the second row.
The pixel data of d0 to d3 is arranged from left to right in the third and third rows, respectively, c0 to c3 in the fourth row, and FIG.
, A0-a3, b0-b3, c0-c3,
The data are stored in the input register of the data rearranging circuit 105 in the order of d0 to d3. The pixel data stored in the input register is rearranged to d0-a0, d1-a1, d2-
The data are stored in the output register of the data rearranging circuit 105 in the order of a2, d3 to a3.

In this case, as a rearrangement method, for example, pixel data stored in the input register is sequentially taken out from the head a0, and among the four registers constituting the output register, a0 to d0 are assigned to the first register. A1 to d1 are stored in the second register, and a2 to d2 are stored in the third register.
And a3 to d3 are written in the fourth register, respectively. At that time, pixel data is written from the top of each register, and when writing the next data, the previous data is shifted to the lower side.

Next, the arrangement of blocks in the area a of the memory 107 by the memory interface 103 will be described. To output the pixel data arrangement shown in FIG. 5A to the display device, the address counter 104 outputs address data to the memory interface 103. In this case, the address data is stored in the address counter 10 in advance.
4 is generated based on the address conversion data table for image at the time of −90 ° rotation provided in FIG. This address data is stored in the memory 1 to reduce the size of the address conversion data table.
The same address is used in A to D banks 07.

Next, a case where the pixel data arrangement is rotated by + 90 °, which is performed when the display device is rotated by -90 °, will be described with reference to FIG. Here, FIG. 6A shows the pixel data arrangement in the display device when the pixel data arrangement shown in FIG. 4 is rotated by + 90 °, and the pixel data is shifted rightward from the display start position on the screen of the display device. a10 to h10 are arranged, and a9 to h9, a8 to h8,
a7-h7, a6-h6, a5-h5, a4-h4, a
3 to h3, a2 to h2, a1 to h1, and a0 to h0. FIG. 6B shows the data rearranging circuit 10.
5 shows a pixel data arrangement before rearrangement and a pixel data arrangement after rearrangement.

First, the rearrangement in the data rearrangement circuit 105 will be described. Here, taking as an example a case where a block surrounded by a bold line at the upper left of FIG. 4 is converted, as shown in FIG. 6B, the blocks are a0 to a3, b
The data are stored in the input register of the data rearranging circuit 105 in the order of 0 to b3, c0 to c3, and d0 to d3. The pixel data stored in the input register is rearranged and a3 to d
3, a2 to d2, a1 to d1, and a0 to d0 are stored in the output register of the data rearranging circuit 105 in this order.

In this case, as a rearrangement method, for example, pixel data stored in the input register is sequentially taken out from the head a0, and among the four registers constituting the output register, a3 to d3 are assigned to the first register. A2 to d2 in the second register and a1 to d1 in the third register.
And a0 to d0 are written in the fourth register, respectively. At this time, pixel data is written from the lowest order of each register, and when writing the next data, the previous data is shifted to the higher order.

Next, the arrangement of blocks in the area a of the memory 107 by the memory interface 103 will be described. In order to output the pixel data arrangement shown in FIG. 6A to the display device, the address counter 104 outputs address data to the memory interface 103. In this case, the address data is stored in the address counter 10 in advance.
4 is generated based on the + 90 ° rotation-time image address conversion data table. This address data is stored in the memory 1 to reduce the size of the address conversion data table.
The same address is used in A to D banks 07.

Next, a case where the pixel data arrangement is rotated by 180 °, which is performed when the display device is rotated by 180 °, will be described with reference to FIG. Here, FIG. 7A shows the pixel data arrangement in the display device when the pixel data arrangement shown in FIG. 4 is rotated by 180 °, and the pixel data is shifted rightward from the display start position on the screen of the display device. h10 to h0 are arranged, and the rows are similarly changed to g10 to g0 and f10 to f0.
0, e10 to e0, d10 to d0, c10 to c0, b1
0 to b0 and a10 to a0. FIG.
7B illustrates the pixel data arrangement before rearrangement and the pixel data arrangement after rearrangement in the data rearrangement circuit 105.

First, the rearrangement in the data rearrangement circuit 105 will be described. Here, taking as an example a case where a block surrounded by a bold line in the upper left of FIG. 4 is converted, as shown in FIG. 7B, the blocks are a0 to a3, b
The data are stored in the input register of the data rearranging circuit 105 in the order of 0 to b3, c0 to c3, and d0 to d3. The pixel data stored in the input register is rearranged to d3 to d
0, c3 to c0, b3 to b0, and a3 to a0 are stored in the output register of the data rearrangement circuit 105 in this order.

In this case, as a rearrangement method, for example, pixel data stored in the input register is sequentially fetched from the head a0, and among the four registers constituting the output register, d3 to d0 are assigned to the first register. C3 to c0 in the second register and b3 to b0 in the third register
And a3 to a0 are written in the fourth register, respectively. At that time, pixel data is written from the top of each register, and when writing the next data, the previous data is shifted to the lower side.

Next, the arrangement of blocks in the area a of the memory 107 by the memory interface 103 will be described. To output the pixel data arrangement shown in FIG. 7A to the display device, the address counter 104 outputs address data to the memory interface 103. In this case, the address data is stored in the address counter 10 in advance.
4 is generated based on the 180-degree rotation image address conversion data table provided in FIG. This address data is stored in the memory 1 to reduce the size of the address conversion data table.
The same address is used in A to D banks 07.

Next, a case where the pixel data arrangement is reversed left and right, which is performed when an image on the display device is reflected on a mirror and viewed, will be described with reference to FIG. Here, FIG.
(A) shows the pixel data arrangement in the display device when the pixel data arrangement shown in FIG. 4 is inverted left and right, and the pixel data is a10 from the display start position on the screen of the display device to the right.
To a0 are arranged, and the rows are similarly changed to b10 to b0, c
10 to c0, d10 to d0, e10 to e0, f10 to f
0, g10 to g0, and h10 to h0. FIG. 8B shows a pixel data arrangement before rearrangement and a pixel data arrangement after rearrangement in the data rearrangement circuit 105.

First, rearrangement in the data rearrangement circuit 105 will be described. Here, taking as an example a case where a block surrounded by a thick line in the upper left of FIG. 4 is converted, as shown in FIG. 8B, the blocks are a0 to a3, b
The data are stored in the input register of the data rearranging circuit 105 in the order of 0 to b3, c0 to c3, and d0 to d3. The pixel data stored in the input register is rearranged and a3 to a
0, b3 to b0, c3 to c0, and d3 to d0 are stored in the output register of the data rearrangement circuit 105 in this order.

In this case, as a rearrangement method, for example, pixel data stored in the input register is sequentially taken out from the head a0, and among the four registers constituting the output register, a3 to a0 are assigned to the first register. B3 to b0 in the second register and c3 to c0 in the third register
And d3 to d0 in the fourth register, respectively. At that time, pixel data is written from the top of each register, and when writing the next data, the previous data is shifted to the lower side.

Next, the arrangement of blocks in the area a of the memory 107 by the memory interface 103 will be described. In order to output the pixel data arrangement shown in FIG. 8A to the display device, the address counter 104 outputs address data to the memory interface 103. In this case, the address data is stored in the address counter 10 in advance.
4 is generated based on the left-right reversal image address conversion data table. This address data is stored in the memory 107 to reduce the size of the address conversion data table.
A to D use the same address.

Next, the operation of the display coordinate conversion circuit will be described with reference to the flowchart shown in FIG. When mode data designating a display coordinate conversion mode is input to the address counter 104 and the data rearranging circuit 105, the address counter 104 and the data rearranging circuit 1
In step 05, the designated conversion mode is set (step S1). Further, the address counter 104
Generates address data for burst transfer corresponding to the designated conversion mode, and outputs the address data to the memory interface 103 (step S2).

Next, pixel data constituting an image for one screen is input to the input data buffer circuit 102 in the same order as that scanned by the picture tube (step S3). Next, it is determined by the memory interface 103 whether the pixel data input to the input data buffer circuit 102 has been completed for a predetermined processing unit, and data input to the input data buffer circuit 102 is continued until it is completed (step S4).
When the pixel data has been prepared for a predetermined processing unit, the memory interface 103 burst-transfers the pixel data for the processing unit from the input data buffer circuit 102 to the area b of the memory 107 (step S5).

Next, in order to perform rearrangement, the memory interface 103 stores the pixel data of the processing unit in the memory 1.
The burst transfer is performed from the area b 07 to the data rearranging circuit 105 (step S6). Next, the data rearranging circuit 105 rearranges the transferred pixel data for the processing unit based on the designated conversion mode (step S).
7). Next, the memory interface 103 burst-transfers the pixel data of the processing unit rearranged from the data rearrangement circuit 105 to the area a of the memory 107 (step S8).

Next, the memory interface 103 determines whether or not the rearrangement of all processing units has been completed, and repeats steps S3 to S8 until completion (step S9). When the rearrangement of all processing units is completed, the memory interface 103 burst-transfers pixel data from the area a of the memory 107 to the output data buffer circuit 106 for each processing unit (step S10). The output data buffer circuit 106 outputs the burst-transferred pixel data in the same order as that scanned by the picture tube (step S11).

Next, burst transfer by the memory interface 103 will be described in detail with reference to FIG. FIG. 10 is an explanatory diagram showing the flow of writing and reading of the memory 107 by the memory interface 103. First, as shown in FIG. 10A, pixel data of a block constituting a processing unit is burst-transferred and written into the area b of the memory 107 from the input data buffer circuit 102. In this case, the memory interface 103
The pixel data of the first row of the predetermined block stored in the input data buffer circuit
Prepare for burst transfer to bank.

When the transfer preparation is completed, the pixel data of the first row of the predetermined block is burst-transferred and written into the area b (A-b) of the bank A of the memory 107. Here, the memory interface 103 prepares and completes the transfer to the next bank B during the burst transfer to the bank A. When the burst transfer to the bank A is completed, the pixel data of the second row of the predetermined block is burst-transferred and written to the area b (Bb) of the bank B of the memory 107. Here, the memory interface 103 prepares and completes the transfer to the next C bank during the burst transfer to the B bank.

When the burst transfer to the B bank is completed, the pixel data of the third row of the predetermined block is continuously stored in the memory 107.
And is written to the b area (Cb) of the C bank of FIG. Here, the memory interface 103
During burst transfer to bank C, preparation for transfer to the next bank D is made and completed. When the burst transfer to the C bank is completed, the pixel data of the fourth row of the predetermined block is burst-transferred and written into the b area (D-b) of the D bank of the memory 107.

Next, as shown in FIG. 10B, a predetermined block of pixel data is burst-transferred from the area b of the memory 107 to the data rearrangement circuit 105, and the data rearrangement circuit 105 performs predetermined rearrangement. And memory 1
07 is burst-transferred to area a. In this case, the memory interface 103 reads out the pixel data stored in the area b (A-b) of the bank A of the memory 107 by burst transfer and prepares to write the data into the input register of the data rearrangement circuit 105.

When the transfer preparation is completed, the pixel data of the first row of the predetermined block is burst-transferred from the b area (Ab) of the A bank of the memory 107 and written into the input register of the data rearranging circuit 105. Here, the memory interface 103 prepares and completes the transfer from the next bank B during the burst transfer from the bank A.
When the burst transfer from the bank A is completed, the pixel data of the second row of the predetermined block is burst-transferred from the area b (Bb) of the bank B of the memory 107 and written into the input register of the data rearrangement circuit 105. . Here, the memory interface 103 prepares and completes the transfer from the next bank C during the burst transfer from the bank B.

When the burst transfer from the bank B is completed, the pixel data of the third row of the predetermined block is burst-transferred from the area b (Cb) of the bank C of the memory 107 and the input register of the data rearranging circuit 105 is successively transferred. Written to Here, the memory interface 103
During burst transfer from a bank, preparation for transfer from the next D bank is made and completed. When the burst transfer from the C bank is completed, the pixel data of the fourth row of the predetermined block is burst-transferred from the b area (Db) of the D bank of the memory 107 and written into the input register of the data rearrangement circuit 105. .

Next, the memory interface 103 prepares for burst transfer of the pixel data rearranged by the data rearrangement circuit 105 and stored in the output register to the A bank of the memory 107. Data sorting circuit 105
Is configured to complete the sorting before the transfer preparation is completed. When the transfer preparation is completed, the pixel data for the first burst length stored in the output register of the data rearranging circuit 105 is burst-transferred and written into the area a (A-a) of the bank A of the memory 107. In this case, the address Aa is designated by the address counter 104 so as to be a position where the predetermined block is arranged after the coordinate conversion. Here, the memory interface 103 prepares and completes the transfer to the next bank B during the burst transfer to the bank A.

When the burst transfer to the bank A is completed, the pixel data of the next burst length stored in the output register of the data rearranging circuit 105 is continuously stored in the memory 107 in the memory B.
The data is burst-transferred and written to the area a (Ba) of the bank. In this case, the write address of Ba is set to a position where the predetermined block is arranged after the coordinate conversion.
Specified by the address counter 104. Here, the memory interface 103 prepares and completes the transfer to the next C bank during the burst transfer to the B bank. When the burst transfer to the B bank is completed, the next burst length pixel data stored in the output register of the data rearrangement circuit 105 is burst transferred to the area a (Ca) of the C bank of the memory 107. Written. In this case, the write address of Ca is designated by the address counter 104 so as to be a position where the predetermined block is arranged after the coordinate conversion.

Here, the memory interface 103
During burst transfer to bank C, preparation for transfer to the next bank D is made and completed. When the burst transfer to the C bank is completed, the pixel data for the next burst length stored in the output register of the data rearrangement circuit 105 is burst-transferred to the area a (Da) of the bank D of the memory 107 and written. It is. In this case, the write address of Da is specified by the address counter 104 so as to be a position where the predetermined block is arranged after the coordinate conversion.

Next, FIG. 10A and FIG. 10A are used until the rearrangement of all blocks constituting the image data is completed.
The process of (b) is repeated, and the pixel data of one screen after the coordinate conversion is stored in the area a of the memory 107. When the rearrangement of all the blocks is completed, the pixel data is burst-transferred from the area a of the memory 107 to the output data buffer circuit 106 as shown in FIG. Here, the memory interface 103 starts data transfer from a block including pixel data at a display start position in the image after the coordinate conversion, and performs data transfer in the order in which the blocks are displayed.

In this case, the memory interface 103
Is the memory 107 specified by the address counter 104
Preparation for burst transfer of pixel data from a predetermined address in area a (A-a) of bank A to a predetermined address of output data buffer circuit 106 also designated by address counter 104 is performed. When the transfer preparation is completed, the pixel data is stored in the area a (A-a) of the bank A of the memory 107.
, And is written to the output data buffer circuit 106. Here, the memory interface 103
During the burst transfer from the A bank, the transfer preparation from the next B bank is completed in the same manner as the A bank.

When the burst transfer from the bank A is completed, the area a (B−
Pixel data is burst-transferred from a) and written to the output data buffer circuit 106. Here, during the burst transfer from the B bank, the memory interface 103 prepares and completes the transfer preparation from the next C bank in the same manner as the A bank. When the burst transfer from bank B is completed,
Subsequently, pixel data is burst-transferred from the area a (Ca) of the C bank of the memory 107 and written to the output data buffer circuit 106.

Here, the memory interface 103
During burst transfer from bank C, preparation for transfer from the next bank D is performed and completed in the same manner as bank A. When the burst transfer from the C bank is completed, the memory 107 continues.
, Pixel data is burst-transferred from the a-area (Da) of the D bank and written to the output data buffer circuit 106. The processing shown in FIG. 10C is repeated until pixel data corresponding to the storage capacity of the output data buffer circuit 106 is transferred. Further, the output data buffer circuit 10
When all the pixel data stored in the memory 107 is output, the same processing is performed until all the pixel data stored in the area a of the memory 107 is transferred.

According to this embodiment, when writing and reading data to and from the memory 107, data transfer is not interrupted by transfer preparation except for the first bank, so that the number of address designations per block is substantially four. Already
The display coordinate conversion can be processed at a higher speed than in the above-described conventional example. For example, in a case where an image consisting of 600 pixels vertically and 800 pixels horizontally is divided into blocks each having 4 pixels vertically and 4 pixels horizontally and display coordinate conversion is performed, addressing per block becomes 4 times for 30000 blocks. , 1
In the display coordinate conversion of the screen, addressing is performed 120,000 times. On the other hand, according to the above-described conventional example, 480,000 addressing operations are required for the display coordinate conversion of an image having the same number of pixels. Therefore, according to this embodiment, the number of times of address designation can be reduced to 1/4 as compared with the conventional example described above. Further, since the data before rearrangement and the data after rearrangement are stored in the memory 107, the number of components can be reduced, and the effect of downsizing the circuit and reducing the cost can be obtained.

In this embodiment, the number of banks of the memory 107 is four, but the number of banks is not limited to this. For example, if the processing unit is a block of 8 × 4 pixels using a memory having 8 banks without changing the burst length, the number of times of addressing can be further reduced by half. In this case, the effect is obtained that the data amount of the address conversion data table of the address counter 104 can be halved, but on the contrary, the storage capacity of the input data buffer circuit 102 and the output data buffer circuit 106 is required twice.

Further, the number of registers of the data rearranging circuit 105 is required twice, and the time required for rearranging data is also doubled. When the number of banks is reduced, the number of times of addressing increases, and conversely, the input data buffer circuit 1
02, the scale of the output data buffer circuit 106 and the data rearranging circuit 105 is reduced. Therefore, it is desirable to determine the number of banks in consideration of the increase and decrease of the circuit scale and the speed of the circuit element due to these advantages and disadvantages. Note that only four banks may be used by using a memory having eight banks.

Although the burst length is four pixel data, the burst length is not limited to this. For example, if the burst length is set to 8 pixel data without changing the number of banks and the processing unit is a block of 4 × 8 pixels, the number of times of addressing can be further reduced by half compared to the embodiment. In this case, the output data buffer circuit 10
6 times the storage capacity. Further, the capacity of the register of the data rearranging circuit 105 is required twice, and the time required for rearranging the data is also doubled. Therefore, it is desirable to determine the burst length in consideration of the increase and decrease of the circuit scale and the speed of the circuit element due to these advantages and disadvantages.

[0058]

As described above, the display coordinate conversion circuit according to the present invention has an input data buffer circuit for storing input pixel data and a first data storage circuit for storing pixel data transferred from the input data buffer circuit. , A data rearranging circuit that rearranges and outputs pixel data transferred from the first memory in a predetermined order, and a second memory that stores rearranged pixel data output from the data rearranging circuit. A second memory, an output data buffer circuit for storing and outputting rearranged pixel data transferred from the second memory, and a memory control means for controlling writing and reading of the first and second memories. The memory control means burst-transfers pixel data in units of blocks each having a predetermined number of pixels in each of the vertical and horizontal directions. It has a storage area comprising a plurality of banks, and writing and reading of data of one burst length to each bank capable constructed, data rearrangement circuit,
Since the pixel data is rearranged in units of blocks according to the mode data indicating the rotation display or the left-right inverted display in units of 90 °, transfer preparation for another bank is performed during burst transfer, and for each burst length, By switching the bank, the pixel data in the block can be continuously burst-transferred, and the effect that the rotation in 90 ° units or the left / right inversion processing can be performed at high speed can be obtained. Further, since the two memories used for the burst transfer are configured by different storage areas of one semiconductor memory, the effects of miniaturizing the circuit and reducing the cost can be obtained.

[Brief description of the drawings]

FIG. 1 is a block diagram of a display coordinate conversion circuit according to the present invention.

FIG. 2 is a configuration diagram illustrating a configuration of a memory in FIG. 1;

FIG. 3 is an explanatory diagram showing images before and after coordinate transformation.

FIG. 4 is an explanatory diagram showing a pixel data arrangement before coordinate conversion.

FIG. 5 is an explanatory diagram for explaining rearrangement of pixel data by −90 ° rotation;

FIG. 6 is an explanatory diagram illustrating rearrangement of pixel data by + 90 ° rotation.

FIG. 7 is an explanatory diagram for explaining rearrangement of pixel data by 180 ° rotation;

FIG. 8 is an explanatory diagram illustrating rearrangement of pixel data by horizontal inversion.

FIG. 9 is a flowchart showing the operation of the display coordinate conversion circuit of the present invention.

FIG. 10 is an explanatory diagram showing a flow of writing and reading of the memory.

[Explanation of symbols]

101: display coordinate conversion circuit, 102: input data buffer circuit, 103: memory interface, 104: address counter, 105: data rearrangement circuit, 106:
Output data buffer circuit, 107: memory.

 ──────────────────────────────────────────────────続 き Continued from the front page F term (reference) 5B069 BC02 CA02 DC04 DC20 DD13 DD20 LA12 5C023 AA03 AA05 AA14 BA15 CA01 CA05 DA04 DA08 5C082 AA01 BA02 BA12 BB22 BB46 CA44 CA46 CB05 DA63 DA86 EA15 MM02

Claims (5)

[Claims] 1. An input data buffer circuit for storing input pixel data, a first memory for storing the pixel data transferred from the input data buffer circuit,
A data rearranging circuit that rearranges the pixel data transferred from the first memory in a predetermined order and outputs the rearranged pixel data, and a second memory that stores the rearranged pixel data output from the data rearranging circuit. A memory, an output data buffer circuit that stores and outputs the rearranged pixel data transferred from the second memory, and a memory control unit that controls writing and reading of the first and second memories. Wherein the memory control means burst-transfers the pixel data in units of blocks each having a predetermined number of pixels in the vertical and horizontal directions, and the first and second memories have a storage area composed of a plurality of banks. And data of one burst length can be written and read to and from each bank, and the data rearrangement circuit performs a rotation display in units of 90 ° or a left display. Display coordinate transformation circuit, characterized in that the pixel data in accordance with the mode data indicating the highlight is configured to sort the blocks. 2. The memory control unit according to claim 1, wherein the memory control unit performs a transfer preparation for another bank during the burst transfer, switches the bank for each burst length, and continuously performs a burst transfer of the pixel data in the block. A display coordinate conversion circuit characterized in that: 3. The memory control unit according to claim 1, wherein the memory control means is configured such that the number of vertical pixels of the block to be burst-transferred matches the number of banks of the first and second memories. A display coordinate conversion circuit. 4. The display coordinate conversion circuit according to claim 1, wherein the first memory and the second memory are different storage areas of one semiconductor memory. 5. The semiconductor memory according to claim 4, wherein said semiconductor memory is a synchronous DRAM (Synchronous DRAM).
ous Dynamic Random Access Memory).