JP2001339666A - Method and device for processing image - Google Patents

Abstract

PROBLEM TO BE SOLVED: To appropriately display an image corresponding to picture signal. SOLUTION: A signal detecting circuit 2 detects a start position for taking in picture signal and a taken-in size. An image conversion control circuit 11 controls a low-pass filter 12 and an interpolation circuit 13 corresponding to a conversion ratio determined by the start position for taking-in the picture signal and an output size. The interpolation circuit 13, based on control by the image conversion control circuit 11, so converts the number of pixels as to match the output size for the picture signal in a specified frequency band.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing apparatus and method, and more particularly, to a method of setting a display range according to a signal standard of a video signal and displaying the video signal without protruding from a display portion of the display device. The present invention relates to an image processing apparatus and method that can be used.

[0002]

2. Description of the Related Art Conventionally, television broadcasting has been NTSC (Nation
al Television System Committee), the conventional television receiver usually receives an interlaced video signal (525i) having 525 scanning lines and displays it. I can do it.

However, recently, an interlaced video signal (480i) having 480 scanning lines, a 480p video signal (progressive video signal) for displaying 480 scanning lines in a line-sequential manner, and a 720 scanning signal A television receiver capable of displaying a 720p video signal for displaying lines in a line-sequential manner and a 1080i video signal in high-definition television broadcasting is also appearing.

In such a television receiver, an effective portion of the video signal in the horizontal and vertical directions is basically displayed. On the other hand, in a CRT, overscan occurs due to fluctuations in the deflection system or high-voltage system, and a part of the effective portion goes out of the display range, resulting in missing images or conversely, underscan. However, a part of the invalid portion may fall within the display range, and a signal or noise other than the video signal of the invalid portion may be displayed as noise. Therefore, in the CRT, the video signal is displayed by overscan in order to at least make noise in an invalid portion of the video signal invisible.

[0005]

However, as described above, in a CRT, there is a problem that a so-called image defect occurs when an overscan is performed.

Conversely, when trying to prevent image missing, underscan occurs as described above, and the invalid portion appears as noise.

[0007] The present invention has been made in view of such circumstances, and it is an object of the present invention to display an image corresponding to a video signal without excess or deficiency.

[0008]

An image processing apparatus according to the present invention comprises a setting means for setting a start position and a capture range of an input video signal, and a capture means for capturing a video signal in a capture range set by the setting means. Conversion means for converting the number of pixels or the number of scanning lines of the video signal captured by the capture means according to a conversion ratio determined by the display range; and a frame signal to be added to the video signal converted by the conversion means. It is characterized by comprising a generating means for generating, and an adding means for adding a frame signal generated by the generating means to a peripheral portion of the video signal converted by the converting means.

[0009] The setting means may set a start position and a capture range according to a signal standard of a video signal.

[0010] The capturing means may capture a range slightly smaller than the capturing range of the video signal set by the setting means.

The capturing means detects a range in which the video signal exists when the range in which the video signal exists is smaller than the capturing range of the video signal set by the setting means,
It can be set as the capture range.

The conversion ratio is set to a value such that the video signal falls within the display range even when the deflection system or the high voltage system has the largest fluctuation.

[0013] The generation means may generate a frame signal corresponding to the input video signal.

According to the image processing method of the present invention, a setting step of setting a start position and a capture range of an input video signal, a capture step of capturing a video signal in a capture range set by the processing of the setting step, and a capture step A conversion step of converting the number of pixels or the number of scanning lines of the video signal captured by the processing according to the conversion ratio determined by the display range, and a frame signal added to the video signal converted by the processing of the conversion step. It is characterized by including a generating step of generating and an adding step of adding a frame signal generated by the processing of the generating step to a peripheral portion of the video signal converted by the processing of the converting step.

In the image processing apparatus and method according to the present invention, the start position and the capture range of the input video signal are set, the video signal in the set capture range is captured, and the number of pixels of the captured video signal or The number of scanning lines is converted in accordance with a conversion ratio determined by the display range, a frame signal to be added to the converted video signal is generated, and the frame signal is added to a peripheral portion of the video signal.

[0016]

FIG. 1 is a block diagram showing a configuration example of an image processing apparatus to which the present invention is applied. Video signal a
Is input from an external device (not shown) to the signal detection circuit 2 and the low-pass filter (LPF) 12 of the video signal converter 5 via the input terminal 1. The signal detection circuit 2 outputs, among the input video signals a,
Active-POSITION (count value of a counter) indicating a section at a level equal to or higher than a predetermined threshold value and indicating a start position thereof;
ACTIVE-SIZE (count value of the counter) indicating a period during which the operation is continued is supplied to the terminal a of the switch 3 and the terminal a of the switch 4, respectively.

The microcomputer 6 supplies to the terminal b of the switch 3 a command for setting a start position for capturing the video signal (hereinafter referred to as ACTIVE-POSITION) based on the input signal format (signal standard of the video signal). And capture size of video signal a (hereinafter referred to as ACTI
Command to set VE-SIZE) switch 4
To the terminal b. The microcomputer 6 also
A command for setting a display size (hereinafter, referred to as DISPLY-SIZE) on the output side of a video signal based on an input signal format, and an output timing (hereinafter, DISPLY-SIZE)
A command for setting “−POSITION” is supplied to the image conversion control circuit 11 and the display control circuit 16 of the video signal converter 5, respectively. The microcomputer 6 further supplies a frame signal generating circuit 8 with a frame signal setting signal for the video signal.

The switch 3 normally selects the terminal b. However, when the video signal from the signal detection circuit 2 is supplied to the image conversion control circuit 11 based on a command from the microcomputer 6, the terminal a is selected. To switch.
The switch 4 normally selects the terminal b, but when supplying the video signal from the signal detection circuit 2 to the image conversion control circuit 11 based on a command from the microcomputer 6,
Switching is performed to select terminal a. Accordingly, the image conversion control circuit 11 is supplied with ACTIVE-POSITION (capture start position) and ACTIVE-SIZE (capture size) from the signal detection circuit 2 or the microcomputer 6.

The image conversion control circuit 11 includes a signal detection circuit 2
Or an ACTIVE-SIZE from the microcomputer 6,
DISP of video signal supplied from microcomputer 6
The frequency characteristic of the low-pass filter 12 and the interpolation coefficient of the interpolation circuit 13 are controlled in accordance with the conversion ratio determined by LAY-SIZE (output size). The low-pass filter 12 is controlled based on the control of the image conversion control circuit 11,
The frequency band of the input video signal a is limited and supplied to the interpolation circuit 13. The interpolation circuit 13 includes the image conversion control circuit 1
Based on the control 1, the number of pixels of the video signal of a predetermined frequency band supplied from the low-pass filter 12 is converted to match the DISPLAY-SIZE by an interpolation method such as cubic interpolation.

The memory controller 14 includes an interpolation circuit 13
The image signal before and after the number of pixels is converted by the image conversion control circuit 1 is temporarily stored in the field memory 15.
1 and DISPLAY-POS supplied via the interpolation circuit 13
The video signal b after the pixel number conversion stored in the field memory 15 is read based on ITION (output timing). The read video signal b is supplied to the terminal a of the switch 7 and the frame signal generation circuit 8 via the interpolation circuit 13.

The frame signal generation circuit 8 generates a frame signal c based on the video signal b supplied from the interpolation circuit 13 and supplies the frame signal c to the terminal b of the switch 7. The display control circuit 16 controls the switch 7 based on the control of the microcomputer 6. The switch 7 is switched to select the terminal a when supplying the video signal b from the interpolation circuit 13 to the display device 9 based on the control of the display control circuit 16;
When the frame signal c from the frame signal generation circuit 8 is supplied to the display device 9, the terminal b is switched to be selected. The display device 9 displays the video signal b and the frame signal c supplied via the switch 7.

FIG. 2 is a block diagram showing a detailed configuration of the signal detection circuit 2. The level comparator 21 compares the level of the input video signal a with a predetermined threshold level which is set in advance. If the former is larger than the latter, the level is compared with the valid part of the video signal specified by the signal standard. When it is determined that there is, the detection signal d is supplied to the signal position detection circuit 22.

The signal position detecting circuit 22 includes a level comparator 2
1, the value of the dot clock counter indicating the position from the generation timing of the horizontal synchronization signal supplied from the horizontal counter 23, and the detection signal d supplied from the vertical counter 24. Based on the value of the line clock counter indicating the position,
A range where an effective portion of the video signal exists is detected. Then, the signal position detection circuit 22 outputs the detected video signal capture start position to the terminal a of the switch 3 as ACTIVE-POSITION, and determines the range in which the video signal exists (video signal capture size) as ACTIVE-POSITION. Switch 4 as SIZE
Is output to the terminal a.

The horizontal counter 23 supplies the count value of the dot clock counter indicating the position from the generation timing of the horizontal synchronization signal to the signal position detection circuit 22. The vertical counter 24 supplies the count value of the line clock counter indicating the position from the generation timing of the vertical synchronization signal to the signal position detection circuit 22.

FIG. 3 is a block diagram showing a detailed configuration of the frame signal generating circuit 8. As shown in FIG. The smoothing circuit 31 includes the interpolation circuit 13
The luminance signal of the supplied video signal b is averaged for a certain period to generate an average luminance level signal e, which is supplied to the amplifier 32. The amplifier 32 amplifies or attenuates the average luminance level signal e supplied from the smoothing circuit 31 to generate a signal f that optimizes the level of the frame signal with respect to the video signal, and supplies the signal f to the terminal a of the switch 33. . A setting signal g from the microcomputer 6 is connected to a terminal b of the switch 33.
Is supplied.

The switch 33 is connected to the microcomputer 6
When the signal f from the amplifier 32 is supplied to the signal generating circuit 34 (that is, when the level of the frame signal c follows the level of the video signal) based on the control of (a), switching is performed so as to select the terminal a. When the setting signal g from the microcomputer 6 is supplied to the signal generation circuit 34 (that is, when the level of the frame signal c is a fixed value), the terminal b
Can be switched to select. Signal generation circuit 34
Generates a frame signal c (video signal) having a brightness based on the signal f or the setting signal g supplied through the switch 33 and outputs the frame signal c (video signal) to the terminal b of the switch 7.

FIG. 4 is a diagram for explaining an effective display range of a video signal of each signal standard. For a 480i video signal,
While the total number of horizontal pixels is 858, the number of effective pixels is 720, and the total number of vertical lines of the field is 2
In contrast to 62.5, the number of valid lines is 242.5. In the case of a 480p video signal, the total number of pixels in the horizontal direction is 858, whereas the number of effective pixels is 720,
While the total number of vertical lines in the field is 483, the number of valid lines is 525. In the case of a 720p video signal, the total number of effective pixels is 1440 while the total number of horizontal pixels is 1650, and the number of effective lines is 7 while the total number of vertical lines in the field is 750.
20. In the case of a 1080i video signal, the total number of pixels in the horizontal direction is 2200, whereas the number of effective pixels is 19
20 and the total number of vertical lines in the field is 56
The effective line number is 540, whereas the number is 2.5.

That is, in the case of a 480i video signal, the horizontal display effective rate is 0.84 and the vertical display effective rate is 0.92. In the case of a 480p video signal, the horizontal display effective rate is 0.84, and the vertical display effective rate is 0.92. In the case of a 720p video signal, the horizontal display effective rate is 0.87 and the vertical display effective rate is 0.96. For a 1080i video signal,
The horizontal display effective ratio is 0.87, and the vertical display effective ratio is 0.96.

According to the present invention, it is possible to display such video signals having different effective rates without protruding from the display portion of the display device.

Next, the basic operation of the image processing apparatus shown in FIG. 1 will be described below.

The level comparator 21 of the signal detection circuit 2 compares the level of the input video signal a with a predetermined threshold level, and when the former is larger than the latter, the validity of the video signal specified by the signal standard is determined. The signal is determined to be a part, and the detection signal d is supplied to the signal position detection circuit 22. The signal position detection circuit 22 is configured to detect the value of the detection signal d supplied from the level comparator 21, the value of the dot clock counter supplied from the horizontal counter 23, and the value of the line clock counter supplied from the vertical counter 24. ACTIVE-POSITION and ACTIVE indicating the range where the effective part of the video signal exists
Generate -SIZE.

For example, as shown in FIG. 5A, the signal position detection circuit 22 outputs to the terminal a of the switch 3 a position where the level of the input video signal becomes higher than the threshold value as ACTIVE-POSITION. From the ACTIVE-POSITION, the range where the video signal exists (the effective part of the input signal)
Output to the terminal a of the switch 4 as ACTIVE-SIZE.

Although not shown, a range in which the effective portion in the vertical direction of the video signal exists is also detected. That is, the values corresponding to the first to nth scanning lines of the video signal are output to the terminal a of the switch 3 as ACTIVE-POSITION, and correspond to N scanning lines continuing from the ACTIVE-POSITION. The value is output to the terminal a of the switch 4 as ACTIVE-SIZE.

The image conversion control circuit 11 includes a signal detection circuit 2
The low-pass filter 12 corresponds to the conversion ratio determined by the ACTIVE-SIZE (FIG. 5 (A)) from the CPU and the DISPLAY-SIZE (display window) of the video signal from the microcomputer 6 (FIG. 5 (B)). And the interpolation coefficient of the interpolation circuit 13 are controlled. Low-pass filter 1
2 restricts the frequency band of the input video signal a based on the control of the image conversion control circuit 11.

The interpolation circuit 13 controls the memory controller 14 to temporarily store the video signal in the predetermined frequency band supplied from the low-pass filter 12 in the field memory 15 when enlarging the video signal. Then, the interpolation circuit 13 outputs the DISPLAY-POSITION via the memory controller 14.
(Output timing) The video signal stored in the field memory 15 is read out based on (FIG. 5B), and DISPLAY-SIZE is controlled based on the control of the image conversion control circuit 11.
Is converted (enlarged) so as to meet the requirements, and supplied to the terminal a of the switch 7 and the frame signal generation circuit 8, respectively.

On the other hand, when reducing the video signal of a predetermined frequency band supplied from the low-pass filter 12, the interpolation circuit 13 controls the DI based on the control of the image conversion control circuit 11.
After the number of pixels is converted (reduced) so as to conform to SPLAY-SIZE, the memory controller 14 is controlled to temporarily store the video signal with the converted number of pixels in the field memory 15. Then, the interpolation circuit 13 includes a memory controller 14
Via DISPLAY-POSITION (output timing)
Based on (FIG. 5B), the video signal after the pixel number conversion stored in the field memory 15 is read and supplied to the terminal a of the switch 7 and the frame signal generation circuit 8, respectively.

Here, the interpolation circuit 13 converts, for example, all the input video signals basically into a total of 220 pixels in the horizontal direction.
The number of pixels is converted so that 0, the number of valid pixels is 1728, the total number of vertical lines in the field is 562.5, and the number of valid lines is 486. That is, in this case, DISPLAY-S
IZE (display window) is 1728 × 972 (frame).

Specifically, as shown in FIG. 4, in the case of an input signal (video signal) having a signal standard of 480i, the number of pixels 720 in the horizontal direction is converted to 1728, and the number of lines in the vertical direction is 242.5. Is converted to 486 (field). In the case of an input signal having a signal standard of 480p, the number of pixels 720 in the horizontal direction is converted into 1728, and the number of lines 483 in the vertical direction is converted into 486 (field). In the case of a 720p input signal, the number of pixels in the horizontal direction is 14
40 is converted to 1728, and the number of vertical lines 720
Is converted to 486 (field). Signal standard is 10
In the case of an 80i input signal, the number 1920 of pixels in the horizontal direction is converted to 1728, and the number 540 of lines in the vertical direction is 48.
6 (field).

In this embodiment, however, the range in which the effective pixels are actually detected is taken in by the signal detection circuit 2 as an effective portion (ACTIVE-SIZE) and converted. Note that this range is fixed at least in the field, and is set to a different value for each line to prevent image distortion.

The smoothing circuit 31 of the frame signal generating circuit 8 generates an average luminance level signal e of the luminance signal of the read video signal b after the pixel number conversion. The amplifier 32 includes a smoothing circuit 3
A signal f that amplifies or attenuates the average luminance level signal e from 1 so that the luminance of the frame signal with respect to the video signal is optimized.
Generate The signal generating circuit 34 outputs a frame signal c of a brightness (luminance) based on the signal f (a value following the luminance of the video signal).
Is generated and supplied to the terminal b of the switch 7.

As shown in FIG. 5B, the display control circuit 16 reads the video signal after the pixel number conversion in accordance with the output timing (DISPLAY-POSITION).
Switch 7 to terminal a, then DISPLAY
Hold for -SIZE. Then, the display control circuit 16
DISPLAY-POSITION and the DISPLAY-POSITION
-Switch the switch 7 to the terminal b for a predetermined period after the end of SIZE.

As shown in FIG. 5B, the display device 9 displays the range of the size of the display portion of the video signal b and the frame signal c supplied via the switch 7.

As a result, as shown in FIG. 6, the frame 9C is displayed inside the display portion 9A of the display device 9, and the image of the input video signal is displayed in the display window 9B further inside. You. As a result, a part of the effective portion of the video signal does not go out of the display portion 9A, and the ineffective portion of the video signal does not appear as noise. It can be displayed on the display device 9 without lack.

Since the brightness of the frame 9C corresponds to the average value of the brightness of the video signal, the display window 9B
The occurrence of burn-in at (the boundary between the image and the frame 9C) is suppressed.

The display device 9 has a CR as shown in FIG.
If a T (Cathode Ray Tube) 41 is used, when a bright (high-brightness) pixel is output, a large amount of the beam current flows. There is a characteristic that the angle becomes large. Therefore, a bright image has a larger display area 9A than a dark image.
Therefore, the image is displayed larger and only a relatively narrow range of the image corresponding to the input signal is displayed.

However, in the present invention, since the frame 9C is provided as described above, when the image is bright,
Since the width of the frame 9C is only narrowed, if the width of the frame 9C is set in accordance with the expansion rate in the brightest image,
As shown in FIG. 8, an image corresponding to a video signal can always be displayed without excess or deficiency.

As described above, the effective portion in the horizontal and vertical directions of the video signal is converted into a fixed display range regardless of the signal standard (type) of the video signal, and is displayed together with the frame signal. In addition, a part of the effective part of the video signal does not go out of the display range, and an invalid part of the video signal does not appear as noise.

The values of ACTIVE-POSITION and ACTIVE-SIZE can be set to predetermined values based on the format of the input video signal. At this time,
The switches 3 and 4 are both switched to the terminal b based on a command from the microcomputer 6. The image conversion control circuit 11 receives an ACTIVE- signal supplied from the microcomputer 6 via the terminal b of the switch 4.
The interpolation circuit 13 is controlled according to the conversion ratio determined by SIZE (FIG. 5A) and DISPLAY-SIZE of the video signal (FIG. 5B), and the video read from the field memory 15 is controlled. The signal is converted to the number of pixels. At this time, pixels in a range slightly inside the specified ACTIVE-SIZE can be captured. Thus, it is possible to suppress a situation in which a signal in an ineffective portion is originally captured as a signal in an effective portion and is displayed as noise due to a variation in a video signal.

The switch 33 of the frame signal generating circuit 8 is independent of the switching of the terminals a and b of the switches 3 and 4.
Is switched to the terminal a or the terminal b. The microcomputer 6 controls the frame signal generation circuit 8 and the switch 3
When the terminal 3 is switched to the terminal b, the setting signal g is supplied to the signal generation circuit 34, and a frame signal c having a brightness based on the setting signal g (fixed value) is generated. Even in this case,
If the value of the setting signal g is set not to be black but to have a slightly bright luminance, it is possible to suppress burn-in at the boundary between the image and the frame.

As described above, according to the present invention, a video signal larger than a predetermined threshold level is detected as a range where an effective portion exists, and ACTIVE-POSITION and AC of the detected video signal are detected.
The number of pixels of the video signal may be converted using TIVE-SIZE, or the number of pixels of the video signal may be converted using ACTIVE-POSITION and ACTIVE-SIZE preset based on the input signal format. May be.

[0051]

As described above, according to the image processing apparatus and method of the present invention, the start position and the capture range of the input video signal are set, and the video signal in the set capture range is captured and captured. Converts the number of pixels or the number of scanning lines of the converted video signal according to the conversion ratio determined by the display range, generates a frame signal to be added to the converted video signal, and adds a frame signal to the periphery of the video signal As a result, an image corresponding to the video signal can be displayed without excess or deficiency.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration example of an image processing apparatus to which the present invention has been applied.

FIG. 2 is a block diagram showing a detailed configuration of a signal detection circuit 2.

FIG. 3 is a block diagram showing a detailed configuration of a frame signal generation circuit 8;

FIG. 4 is a diagram illustrating an effective display range of a video signal of each signal standard.

FIG. 5 is a diagram illustrating the conversion of the number of pixels of a video signal in the horizontal direction.

FIG. 6 is a diagram illustrating a display example of a video signal whose pixel number has been converted.

FIG. 7 is a diagram illustrating a CRT 41.

FIG. 8 is a diagram illustrating a display example of a converted video signal.

[Explanation of symbols]

2 signal detection circuit, 5 video signal converter, 6 microcomputer, 8 frame signal generation circuit, 9 display device, 11 image conversion control circuit, 12 LPF, 13
Interpolation circuit, 14 memory controller, 15 field memory, 16 display control circuit, 21 level comparator, 22 signal position detection circuit, 23 horizontal counter, 24 vertical counter, 31 smoothing circuit,
32 amplifier, 34 signal generation circuit, 41 CRT

 ────────────────────────────────────────────────── ─── Continued on the front page (72) Inventor Hiroyuki Kojima 6-35 Kita-Shinagawa, Shinagawa-ku, Tokyo Sony Corporation F-term (reference) 5C025 AA28 BA02 BA05 BA13 BA20 BA24 BA27 BA28 BA30 CA09 CB10 DA10 5C058 AA01 BA33 BA35 BB13 BB16 BB17 BB19 BB25 5C063 AA01 AA06 AA10 AB01 AC01 BA06 BA08 CA01 CA14 CA16 CA23 CA25 CA29 CA40

Claims (7)

[Claims] 1. A setting means for setting a start position and a capture range of an input video signal; a capture means for capturing the video signal in a capture range set by the setting means; A conversion unit that converts the number of pixels or the number of scanning lines of the video signal according to a conversion ratio determined by a display range; and a generation unit that generates a frame signal to be added to the video signal converted by the conversion unit. An image processing apparatus comprising: an adding unit that adds the frame signal generated by the generating unit to a peripheral portion of the video signal converted by the converting unit. 2. The image processing apparatus according to claim 1, wherein the setting unit sets a start position and a capture range according to a signal standard of the video signal. 3. The image processing apparatus according to claim 1, wherein the capturing unit captures a range slightly smaller than a capturing range of the video signal set by the setting unit. 4. When the range in which the video signal exists is smaller than the range in which the video signal is set by the setting unit, the capturing unit detects the range in which the video signal exists, and captures the detected range. The image processing apparatus according to claim 1, wherein the range is a range. 5. The apparatus according to claim 1, wherein the conversion ratio is set to a value such that the video signal falls within the display range even when the deflection system or the high-voltage system has the largest fluctuation. The image processing apparatus according to any one of the preceding claims. 6. The image processing apparatus according to claim 1, wherein the generation unit generates the frame signal corresponding to the input video signal. 7. A setting step of setting a start position and a capture range of an input video signal, a capture step of capturing the video signal in a capture range set by the processing of the setting step, and a process of the capture step. A conversion step of converting the number of pixels or the number of scanning lines of the captured video signal in accordance with a conversion ratio determined by a display range; and a frame signal to be added to the video signal converted by the processing of the conversion step. Image processing, comprising: a generating step of generating; and an adding step of adding the frame signal generated by the processing of the generating step to a peripheral portion of the video signal converted by the processing of the converting step. Method.