JP2001338913A - Plasma etching silicon electrode plate generating less particles - Google Patents
Plasma etching silicon electrode plate generating less particlesInfo
- Publication number
- JP2001338913A JP2001338913A JP2000159451A JP2000159451A JP2001338913A JP 2001338913 A JP2001338913 A JP 2001338913A JP 2000159451 A JP2000159451 A JP 2000159451A JP 2000159451 A JP2000159451 A JP 2000159451A JP 2001338913 A JP2001338913 A JP 2001338913A
- Authority
- JP
- Japan
- Prior art keywords
- electrode plate
- plasma etching
- silicon
- particles
- wafer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Drying Of Semiconductors (AREA)
- ing And Chemical Polishing (AREA)
Abstract
Description
【0001】[0001]
【発明の属する技術分野】この発明は、プラズマエッチ
ング装置に使用するパーティクル発生の少ないシリコン
電極板に関するものであり、特に半導体装置を構成する
層間絶縁膜のエッチングに際してパーティクル発生が極
めて少ないシリコン電極板に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a silicon electrode plate used in a plasma etching apparatus and having a small particle generation, and more particularly to a silicon electrode plate having a very small particle generation when etching an interlayer insulating film constituting a semiconductor device. Things.
【0002】[0002]
【従来の技術】一般に、半導体装置を製造する工程の一
つにSiウエハをエッチングする工程があり、Siウエ
ハをエッチングするための装置として、プラズマエッチ
ング装置が用いられている。さらに具体的に述べると、
Siウエハの表面に酸化シリコンからなる層間絶縁膜を
形成し、さらにその上にフォトレジスト膜を局部的に形
成し、前記層間絶縁膜のフォトレジスト膜の無い部分を
エッチング面としてエッチングすることが行なわれてい
る。この時使用されるプラズマエッチング装置は、例え
ば図1に示されるように、真空容器1内に電極板2およ
び架台3が間隔をおいて設けられており、架台3の上に
層間絶縁膜(図示せず)を形成したSiウエハ4を載置
し、エッチングガス7をシリコン電極板2に設けられた
貫通細孔5を通してSiウエハ4に向って流しながら高
周波電源6により電極板2と架台3の間に高周波電圧を
印加することができるようになっている。2. Description of the Related Art Generally, one of the processes for manufacturing a semiconductor device includes a process for etching a Si wafer, and a plasma etching device is used as a device for etching a Si wafer. More specifically,
An interlayer insulating film made of silicon oxide is formed on the surface of a Si wafer, a photoresist film is locally formed thereon, and etching is performed using a portion of the interlayer insulating film without the photoresist film as an etching surface. Have been. In the plasma etching apparatus used at this time, for example, as shown in FIG. 1, an electrode plate 2 and a gantry 3 are provided at an interval in a vacuum vessel 1, and an interlayer insulating film (FIG. The silicon wafer 4 on which the electrode plate 2 and the pedestal 3 are mounted by the high-frequency power source 6 while flowing the etching gas 7 toward the Si wafer 4 through the through holes 5 provided in the silicon electrode plate 2. A high frequency voltage can be applied in between.
【0003】供給されたエッチングガス7はこの高周波
電圧の印加によりシリコン電極板2と架台3の間の空間
でプラズマ10となり、このプラズマ10がSiウエハ
に当ってSiウエハ4の表面がエッチングされる。前記
シリコン電極板2は円盤状の単結晶シリコンで構成され
ており、この単結晶シリコン円盤の平面に対して直角方
向に複数の貫通細孔5が設けられている。The supplied etching gas 7 is turned into a plasma 10 in the space between the silicon electrode plate 2 and the gantry 3 by application of the high frequency voltage, and the plasma 10 hits the Si wafer and the surface of the Si wafer 4 is etched. . The silicon electrode plate 2 is made of a disc-shaped single-crystal silicon, and a plurality of through-holes 5 are provided in a direction perpendicular to the plane of the single-crystal silicon disc.
【0004】ところが、従来の単結晶シリコンからなる
シリコン電極板を用いてSiウエハをプラズマエッチン
グした場合、プラズマエッチングしたSiウエハ表面に
粒径:0.5μm以上の粗大パーティクルが多数付着
し、かかる粗大パーティクルが多数付着したSiウエハ
は不良品となり、プラズマエッチングしたSiウエハの
歩留りの低下が問題点となっている。However, when a conventional silicon electrode plate made of single-crystal silicon is used to plasma-etch a Si wafer, a large number of coarse particles having a particle size of 0.5 μm or more adhere to the surface of the plasma-etched Si wafer. A Si wafer to which a large number of particles have adhered becomes a defective product, and the yield of the plasma-etched Si wafer has been reduced.
【0005】この問題点を解決するために、従来は、図
2(a)に示されるように、シリコン電極板2の貫通細
孔5の端部に面取り8を施したり、または図2(b)に
示されるように、シリコン電極板2の貫通細孔5を成形
するときに壁面から内部に向かって成長するマイクロク
ラック9の長さを10μm以下に抑えたりして粒径:
0.5μm以上の粗大パーティクルの発生を防止してい
る。In order to solve this problem, conventionally, as shown in FIG. 2A, a chamfer 8 is formed at the end of the through hole 5 of the silicon electrode plate 2, or as shown in FIG. As shown in ()), when forming the through pores 5 of the silicon electrode plate 2, the length of the microcracks 9 growing from the wall surface toward the inside is suppressed to 10 μm or less, and the particle diameters are as follows:
The generation of coarse particles of 0.5 μm or more is prevented.
【0006】[0006]
【発明が解決しようとする課題】しかし、近年、半導体
装置の高性能化に伴って、Siウエハ表面に付着するパ
ーティクルをさらに少なくするよう求められており、前
記従来の単結晶シリコン電極板を用いると、粒径:0.
5μm以上の粗大パーティクルの発生は防止できるが、
粒径:0.3μm以上のさらに微細なパーティクルの発
生までも少なくすることはできない。However, in recent years, as the performance of semiconductor devices has been improved, it has been required to further reduce the number of particles adhering to the surface of the Si wafer. And particle size: 0.
Although the generation of coarse particles of 5 μm or more can be prevented,
Particle size: generation of finer particles of 0.3 μm or more cannot be reduced.
【0007】[0007]
【課題を解決するための手段】そこで、本発明者等は、
プラズマエッチングしたSiウエハ表面に粗大パーティ
クルだけでなく、さらに微細なパーティクルの付着を防
止すべく研究を行った結果、一般に、従来の引き上げ法
によって得られた単結晶シリコンインゴットにはCOP
(Crystal Originated Parti
cle)欠陥、FDR(フロー・パターン・デフェク
ト)欠陥、LSTD(赤外散乱体)欠陥などの成長欠陥
(As−grownn欠陥)を含むことが知られてお
り、この成長欠陥の中でもCOP欠陥の少ない単結晶シ
リコンで作製した電極板を用いてプラズマエッチングを
行なうと、プラズマエッチングの際に発生するパーティ
クル数が少なくなり、COP欠陥の密度が104個/c
m3を越えて含む単結晶シリコンからなる電極板を用い
てプラズマエッチングを行うと、Siウエハ表面に付着
する0.3μm以上のパーティクル数が急増する、など
の研究結果が得られたのである。Means for Solving the Problems Accordingly, the present inventors have
As a result of research to prevent not only coarse particles but also fine particles from adhering to the surface of the plasma-etched Si wafer, the single crystal silicon ingot obtained by the conventional pulling method generally has COP.
(Crystal Originated Parti
cle) defects, FDR (flow pattern defect) defects, and growth defects (As-grown defects) such as LSTD (infrared scatterer) defects. Among these growth defects, there are few COP defects. When plasma etching is performed using an electrode plate made of single crystal silicon, the number of particles generated during plasma etching is reduced, and the density of COP defects is 10 4 / c.
Research results have shown that when plasma etching is performed using an electrode plate made of single crystal silicon containing more than m 3 , the number of particles of 0.3 μm or more adhering to the surface of the Si wafer rapidly increases.
【0008】この発明は、かかる研究結果に基づいてな
されたものであって、(1)COP欠陥の密度が104
個/cm3以下の単結晶シリコンからなるパーティクル
発生の少ないプラズマエッチング用シリコン電極板、に
特徴を有するものである。The present invention has been made based on the results of such research, and (1) the density of COP defects is 10 4
The present invention is characterized by a plasma etching silicon electrode plate made of single crystal silicon having a particle size of not more than 3 pieces / cm 3 and having few particles.
【0009】前記COP欠陥密度が104個/cm3以下
の単結晶シリコン製電極板を製造するには、単結晶シリ
コンインゴットをシリコン融液から引き上げる際に、全
長に亘って従来の温度域(900〜1100℃)よりも
高い1200〜1400℃の温度域に1時間以上単結晶
シリコンインゴットを保持することによりCOP欠陥密
度が104個/cm3以下の単結晶シリコンインゴットを
作製し、このようにして得られたCOP欠陥密度が10
4個/cm3以下の単結晶シリコンインゴットを切断して
単結晶シリコンの円板を作製し、この単結晶シリコン円
板に貫通細孔を形成することにより得られる。In order to manufacture a single-crystal silicon electrode plate having a COP defect density of 10 4 / cm 3 or less, when pulling a single-crystal silicon ingot from a silicon melt, a conventional temperature range (over the entire length) is used. By holding the single crystal silicon ingot in a temperature range of 1200 to 1400 ° C. higher than 900 to 1100 ° C. for one hour or more, a single crystal silicon ingot having a COP defect density of 10 4 / cm 3 or less is produced. COP defect density obtained by
It is obtained by cutting a single crystal silicon ingot of 4 pieces / cm 3 or less to produce a single crystal silicon disk, and forming through-pores in the single crystal silicon disk.
【0010】単結晶シリコンに含まれるCOP欠陥の数
を測定するには、SC1洗浄液(RCA標準1液=NH
4OH/H2O2/H2O)を用いて単結晶シリコンの
表面を繰り返し洗浄することにより単結晶シリコンの表
面に現れるエッチピットを拡大化し、この拡大化したエ
ッチピットをパーティクルカウンター(たとえばSS6
200)で検出し測定する。COP欠陥は微細であって
も、繰り返し洗浄することにより拡大化されたエッチピ
ットとして現れるために検出が可能となるのである。In order to measure the number of COP defects contained in single-crystal silicon, SC1 cleaning liquid (RCA standard 1 liquid = NH
The surface of the single crystal silicon is repeatedly washed with 4 OH / H 2 O 2 / H 2 O to enlarge the etch pits appearing on the surface of the single crystal silicon. SS6
200). Even if the COP defect is fine, it can be detected because it appears as an enlarged etch pit by repeated cleaning.
【0011】さらに、本発明者らは、(a)一方向凝固
組織を有する鋳造体シリコンインゴットは通常の鋳造体
シリコンインゴットと比べて純度が高くかつCOP欠陥
密度が少なくすることができ、COP欠陥密度が104
個/cm3以下の一方向凝固組織を有する鋳造体シリコ
ンインゴットから作製したシリコン電極板を用いてプラ
ズマエッチングを行なうと、プラズマエッチングの際に
発生するパーティクル数が少なくなる、(b)このCO
P欠陥密度が104個/cm3以下の一方向凝固組織を有
する鋳造体シリコンインゴットは、凝固方向の温度勾配
をG(mm/時)、一方向凝固の凝固速度をR:(K/
mm)とすると、GR(K/時)を1〜20の範囲内に
小さくし、さらにG/R(mm2/K・時)を10〜1
000の範囲に制御することにより得られる、などの研
究結果が得られたのである。Further, the present inventors have found that (a) a cast silicon ingot having a unidirectionally solidified structure has a higher purity and a lower COP defect density than an ordinary cast silicon ingot, Density is 10 4
When plasma etching is performed using a silicon electrode plate manufactured from a cast silicon ingot having a unidirectional solidification structure of not more than 3 pieces / cm 3, the number of particles generated during plasma etching is reduced.
A cast silicon ingot having a unidirectional solidification structure with a P defect density of 10 4 / cm 3 or less has a temperature gradient in the solidification direction of G (mm / hour) and a solidification rate of the unidirectional solidification of R: (K /
mm), the GR (K / hr) is reduced within the range of 1 to 20 and the G / R (mm 2 / K · hr) is reduced to 10 to 1
Thus, research results were obtained, such as that it could be obtained by controlling to a range of 000.
【0012】したがって、この発明は、(2)COPの
密度が104個/cm3以下の一方向凝固組織を有するシ
リコン鋳造体からなるパーティクル発生の少ないプラズ
マエッチング用シリコン電極板、に特徴を有するもので
ある。前記COP欠陥を全くなくすことはコストがかか
りすぎるのでコスト的に見てCOP欠陥密度の一層好ま
しい範囲は10〜103個/cm3である。Accordingly, the present invention is characterized by (2) a silicon electrode plate for plasma etching, which is made of a silicon casting having a unidirectionally solidified structure having a COP density of 10 4 / cm 3 or less and has little particle generation. Things. Eliminating the COP defects at all costs too much, so a more preferable range of the COP defect density in terms of cost is 10 to 10 3 / cm 3 .
【0013】一方向凝固組織を有する高純度シリコン鋳
造体に含まれるCOP欠陥を測定するには、前記単結晶
におけるCOP欠陥の測定と同じ方法でエッチングし、
カウントの際に粒界によるものを除去することにより検
出することができる。In order to measure a COP defect contained in a high-purity silicon casting having a unidirectionally solidified structure, etching is performed in the same manner as in the measurement of the COP defect in the single crystal.
It can be detected by removing those due to grain boundaries during counting.
【0014】[0014]
【発明の実施の形態】実施例1 単結晶シリコンインゴットをシリコン融液から引き上げ
る際に、全長に亘って表1に示される温度および時間に
単結晶シリコンインゴットを保持することにより、直胴
部の直径:300mm、長さ:300mmを有し、全長:6
00mmの寸法を有する単結晶シリコンインゴットを作製
し、これら単結晶シリコンインゴットの直胴部をダイヤ
モンドハンドソーにより厚さ:7mmに切断し、研摩加工
して直径:280mm、厚さ:4.5mmの寸法を有する単
結晶シリコン板を作製し、この単結晶シリコン板にドリ
ル加工により直径:0.45mmの貫通細孔を形成するこ
とにより、本発明プラズマエッチング用シリコン電極板
(以下、本発明電極板という)1〜6および従来プラズ
マエッチング用シリコン電極板(以下、従来電極板とい
う)1を作製した。DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiment 1 When a single-crystal silicon ingot is pulled up from a silicon melt, the single-crystal silicon ingot is held at the temperature and time shown in Table 1 over its entire length, so that the straight body portion is removed. Diameter: 300mm, length: 300mm, total length: 6
A single crystal silicon ingot having a size of 00 mm was prepared, and the straight body of the single crystal silicon ingot was cut into a thickness of 7 mm with a diamond hand saw and polished to dimensions of a diameter of 280 mm and a thickness of 4.5 mm. A silicon electrode plate for plasma etching of the present invention (hereinafter, referred to as the electrode plate of the present invention) is prepared by forming a through-hole having a diameter of 0.45 mm by drilling a single crystal silicon plate having 1) to 6 and a conventional silicon electrode plate for plasma etching (hereinafter referred to as a conventional electrode plate) 1.
【0015】これら本発明電極板1〜6および従来電極
板1の表面を鏡面研磨したのち、85℃に加熱したSC
1洗浄液に40分間浸漬することによりSC1洗浄を行
なった。このとき使用するSC1洗浄液は、H2O2水溶
液(比重1.1)、NH4OH(比重0.9)、および
H2OをH2O:H2O2:NH4OH=5:1:1の容積
比で混合することにより作製した。かかる本発明電極板
1〜6および従来電極板1の鏡面研磨表面をSC1洗浄
液で3回洗浄すると、COP欠陥がエッチピットとして
顕在化し、この顕在化したエッチピットの数をパーティ
クルカウンターにより測定し、本発明電極板1〜6およ
び従来電極板1に含まれるCOP欠陥密度を求め、その
結果を表1に示した。The surfaces of the electrode plates 1 to 6 of the present invention and the conventional electrode plate 1 are mirror-polished and then heated to 85 ° C.
The SC1 cleaning was performed by immersing in one cleaning solution for 40 minutes. The SC1 cleaning solution used at this time was an H 2 O 2 aqueous solution (specific gravity 1.1), NH 4 OH (specific gravity 0.9), and H 2 O as H 2 O: H 2 O 2 : NH 4 OH = 5: It was prepared by mixing at a volume ratio of 1: 1. When the mirror-polished surfaces of the electrode plates 1 to 6 of the present invention and the conventional electrode plate 1 are washed three times with the SC1 cleaning solution, COP defects are revealed as etch pits, and the number of the revealed etch pits is measured by a particle counter. The COP defect densities contained in the electrode plates 1 to 6 of the present invention and the conventional electrode plate 1 were determined, and the results are shown in Table 1.
【0016】一方、CVDによりSiO2の積層を施し
た直径:200mmのSiウエハを用意し、これをプラズ
マエッチング装置にセットし、本発明電極板1〜6およ
び従来電極板1を用いて、 チャンバー内圧力:50Pa、 ガス流量比:Ar/CHClF3/CH4 =300/1
5/15(SCCm)、 高周波電力:1.5KW、 エッチング時間:2min.、 の条件でプラズマエッチングを行ない、Siウエハ表面
に付着する直径:0.3μm以上のパーティクル数を測
定し、その結果を表1に示した。On the other hand, a Si wafer having a diameter of 200 mm, on which SiO 2 was laminated by CVD, was prepared, set in a plasma etching apparatus, and a chamber was formed using the electrode plates 1 to 6 of the present invention and the conventional electrode plate 1. Internal pressure: 50 Pa, gas flow ratio: Ar / CHClF3 / CH4 = 300/1
Plasma etching was performed under the following conditions: 5/15 (SCCm), high frequency power: 1.5 KW, etching time: 2 min., And the number of particles having a diameter of 0.3 μm or more adhering to the surface of the Si wafer was measured. The results are shown in Table 1.
【0017】[0017]
【表1】 [Table 1]
【0018】表1に示される結果から、本発明電極板1
〜6を用いてプラズマエッチングを行った場合と従来電
極板1を用いてプラズマエッチングを行った場合を比較
すると、本発明電極板1〜6を用いてプラズマエッチン
グを行った場合にSiウエハ表面に付着する0.3μm
以下のパーティクル発生数は格段に少ないことがわか
る。From the results shown in Table 1, the electrode plate of the present invention 1
When the plasma etching was performed using the electrode plates 1 to 6 of the present invention, the plasma etching was performed using the electrode plates 1 to 6 of the present invention. 0.3μm to adhere
It can be seen that the number of generated particles below is extremely small.
【0019】実施例2 一方向凝固鋳型の縦方向の温度勾配をG(mm/h)、
一方向凝固速度をR(K/mm)を表1に示される値と
なるようにし、冷却速度GR(K/h)およびG/R
(mm2/Kh)の値が表1に示される値となるように
制御しながら一方向凝固させることにより、一方向凝固
組織を有し、直径:300mm、長さ:300mmmの寸法
を有する円柱状鋳造体シリコンインゴットを作製し、胴
部をダイヤモンドハンドソーにより厚さ:7mmに切断
し、研摩加工して直径:280mm、厚さ:4.5mmの寸
法を有する一方向凝固組織を有する鋳造体シリコン板を
作製し、この一方向凝固組織を有する鋳造体シリコン板
にドリル加工により直径:0.45mmの貫通細孔を形成
し、本発明電極板7〜11および従来電極板2を作製し
た。Example 2 The temperature gradient in the longitudinal direction of the unidirectional solidification mold was G (mm / h),
The unidirectional solidification rate was adjusted so that R (K / mm) became the value shown in Table 1, and the cooling rate GR (K / h) and G / R
A circle having a unidirectionally solidified structure and a diameter of 300 mm and a length of 300 mm by being unidirectionally solidified while controlling the value of (mm 2 / Kh) to be the value shown in Table 1. A columnar cast silicon ingot was prepared, and the body was cut to a thickness of 7 mm with a diamond hand saw and polished to give a cast silicon having a unidirectionally solidified structure having a diameter of 280 mm and a thickness of 4.5 mm. A plate was prepared, and through-holes having a diameter of 0.45 mm were formed in the cast silicon plate having the unidirectional solidification structure by drilling to prepare the electrode plates 7 to 11 of the present invention and the conventional electrode plate 2.
【0020】これら本発明電極板7〜11および従来電
極板2の表面を鏡面研磨したのち、85℃に加熱したS
C1洗浄液に40分間浸漬することによりSC1洗浄を
行なった。このとき使用するSC1洗浄液は、実施例1
で使用したSC1洗浄液と同じSC1洗浄液を使用し
た。本発明電極板7〜11および従来電極板2の表面を
SC1洗浄液で洗浄すると、COP欠陥がエッチピット
として顕在化すると同時に結晶粒界も顕在化するところ
から、結晶粒界のカウント数を除いた補正値をエッチピ
ットの数としてパーティクルカウンターにより測定し、
本発明電極板7〜11および従来電極板2に含まれるC
OP欠陥密度を求め、その結果を表2に示した。The surfaces of the electrode plates 7 to 11 of the present invention and the conventional electrode plate 2 are mirror-polished and then heated to 85 ° C.
SC1 cleaning was performed by immersing in C1 cleaning solution for 40 minutes. The SC1 cleaning solution used at this time was the same as in Example 1.
The same SC1 washing solution as that used in the above was used. When the surfaces of the electrode plates 7 to 11 of the present invention and the conventional electrode plate 2 were cleaned with the SC1 cleaning solution, the count number of the crystal grain boundaries was excluded because the COP defects became obvious as etch pits and the crystal grain boundaries also appeared. Measure the correction value as the number of etch pits with a particle counter,
C contained in the electrode plates 7 to 11 of the present invention and the conventional electrode plate 2
The OP defect density was determined, and the results are shown in Table 2.
【0021】このようにして得られた本発明電極板7〜
11および従来電極板2を実施例1で用意したプラズマ
エッチング装置にセットし、実施例1と同じ条件でプラ
ズマエッチングを行ない、Siウエハ表面に付着する直
径:0.3μm以上のパーティクル数を測定し、その結
果を表2に示した。The thus obtained electrode plates 7 to 7 of the present invention
11 and the conventional electrode plate 2 were set in the plasma etching apparatus prepared in Example 1, plasma etching was performed under the same conditions as in Example 1, and the number of particles having a diameter of 0.3 μm or more adhering to the surface of the Si wafer was measured. The results are shown in Table 2.
【0022】[0022]
【表2】 [Table 2]
【0023】表2に示される結果から、本発明電極板7
〜11を用いてプラズマエッチングを行った場合と従来
電極板2を用いてプラズマエッチングを行った場合を比
較すると、Siウエハ表面に付着する0.3μm以下の
パーティクル発生数は格段に少ないことがわかる。From the results shown in Table 2, the electrode plate 7 of the present invention was
Comparing the case where the plasma etching was performed using Nos. 11 to 11 and the case where the plasma etching was performed using the conventional electrode plate 2, it was found that the number of particles of 0.3 μm or less adhering to the surface of the Si wafer was extremely small. .
【0024】[0024]
【発明の効果】上述のように、この発明のシリコン電極
板を用いてSiウエハをプラズマエッチングすると、パ
ーティクル発生による不良品発生を大幅に減らすことが
でき、半導体装置産業の発展に大いに貢献しうるもので
ある。As described above, when a silicon wafer is plasma-etched using the silicon electrode plate of the present invention, the occurrence of defective products due to the generation of particles can be greatly reduced, and can greatly contribute to the development of the semiconductor device industry. Things.
【図1】従来のプラズマエッチング装置の断面説明図で
ある。FIG. 1 is an explanatory sectional view of a conventional plasma etching apparatus.
【図2】従来のシリコン電極板における貫通細孔の断面
説明図である。FIG. 2 is an explanatory cross-sectional view of a through hole in a conventional silicon electrode plate.
【符号の説明】 1 真空容器 2 シリコン電極板 3 架台 4 Siウエハ 5 貫通細孔 6 高周波電源 7 プラズマエッチングガス 8 面取り 9 マイクロクラック 10 プラズマ[Description of Signs] 1 vacuum vessel 2 silicon electrode plate 3 mount 4 Si wafer 5 penetrating pore 6 high frequency power supply 7 plasma etching gas 8 chamfering 9 micro crack 10 plasma
Claims (2)
晶シリコンからなることを特徴とするパーティクル発生
の少ないプラズマエッチング用シリコン電極板。1. A silicon electrode plate for plasma etching with less generation of particles, comprising a single crystal silicon having a COP density of 10 4 / cm 3 or less.
向凝固組織を有するシリコン鋳造体からなることを特徴
とするパーティクル発生の少ないプラズマエッチング用
シリコン電極板。2. A silicon electrode plate for plasma etching with less generation of particles, comprising a silicon casting having a unidirectionally solidified structure having a COP density of 10 4 / cm 3 or less.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2000159451A JP4117438B2 (en) | 2000-05-30 | 2000-05-30 | Silicon electrode plate for plasma etching with less generation of particles |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2000159451A JP4117438B2 (en) | 2000-05-30 | 2000-05-30 | Silicon electrode plate for plasma etching with less generation of particles |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2001338913A true JP2001338913A (en) | 2001-12-07 |
JP4117438B2 JP4117438B2 (en) | 2008-07-16 |
Family
ID=18663770
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2000159451A Expired - Lifetime JP4117438B2 (en) | 2000-05-30 | 2000-05-30 | Silicon electrode plate for plasma etching with less generation of particles |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP4117438B2 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2015164179A (en) * | 2014-01-29 | 2015-09-10 | 三菱マテリアル株式会社 | Electrode plate for plasma processing devices, and method for manufacturing the same |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP7302951B2 (en) | 2018-06-28 | 2023-07-04 | 日東電工株式会社 | Polarizer manufacturing method and polarizer manufacturing apparatus |
-
2000
- 2000-05-30 JP JP2000159451A patent/JP4117438B2/en not_active Expired - Lifetime
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2015164179A (en) * | 2014-01-29 | 2015-09-10 | 三菱マテリアル株式会社 | Electrode plate for plasma processing devices, and method for manufacturing the same |
Also Published As
Publication number | Publication date |
---|---|
JP4117438B2 (en) | 2008-07-16 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP2000349073A (en) | Silicon electrode plate | |
JP4045592B2 (en) | Silicon electrode plate for plasma etching | |
JP2011071361A (en) | Method of reproducing silicon component for plasma etching apparatus, as well as silicon component for plasma etching apparatus | |
JP4535283B2 (en) | Single crystal silicon electrode plate for plasma etching with less in-plane variation of specific resistance | |
JP6398827B2 (en) | Method for manufacturing electrode plate for plasma processing apparatus | |
JP4117438B2 (en) | Silicon electrode plate for plasma etching with less generation of particles | |
JP2003051485A (en) | Coating silicon electrode plate for plasma etching | |
JPH09129605A (en) | Plasma etching single crystal silicon electrode plate | |
JP2007273707A (en) | Method for carrying out uniformly plasma etching of wafer surface using silicon electrode board of almost the same size as wafer | |
JP2001102357A (en) | Plasma etching electrode plate and manufacturing method therefor | |
JPH09245994A (en) | Electrode for processing device utilizing plasma, and manufacture of same electrode | |
JPH08134667A (en) | Anode electrode plate for plasma etching | |
JP4883368B2 (en) | Single crystal silicon electrode plate for plasma etching | |
JP2004247350A (en) | Plasma processing silicon plate | |
JP2006196491A (en) | Plasma etching electrode plate | |
JP2000306886A (en) | Plasma etching electrode | |
JP2000138206A (en) | Electrode plate for plasma etching system enabling formation of uniformly etched surface | |
JP4045591B2 (en) | Electrode plate for plasma etching | |
JP4517364B2 (en) | Silicon electrode plate for plasma etching | |
JPH06177076A (en) | Electrode for plasma etching | |
JPH10265976A (en) | Production of plasma etching electrode | |
TWI759981B (en) | Plasma resistant members, parts for plasma processing apparatus and plasma processing equipment | |
JP3339429B2 (en) | Electrode plate of plasma etching equipment that can form uniform etching surface | |
JPH10125651A (en) | Perforated electrode plate | |
JPH10275802A (en) | Manufacture of plasma-etching electrode |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20051130 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20071112 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20071115 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20080326 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20080408 |
|
R150 | Certificate of patent or registration of utility model |
Free format text: JAPANESE INTERMEDIATE CODE: R150 Ref document number: 4117438 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20110502 Year of fee payment: 3 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20110502 Year of fee payment: 3 |
|
S531 | Written request for registration of change of domicile |
Free format text: JAPANESE INTERMEDIATE CODE: R313531 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20110502 Year of fee payment: 3 |
|
R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20110502 Year of fee payment: 3 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20120502 Year of fee payment: 4 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20120502 Year of fee payment: 4 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20130502 Year of fee payment: 5 |
|
EXPY | Cancellation because of completion of term |