JP2001338911A - Plasma processing equipment and fabrication method for semiconductor equipment - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide plasma processing equipment which prevents charging damages of an object to be processed or nonuniform plasma processing speed within the surface of the object; and a method for fabricating high quality semiconductor equipment which does not cause nonuniform plasma processing or charging damages. SOLUTION: The plasma etching equipment has a processing chamber 1, a lower electrode 2 and an upper electrode 3 which are placed facing each other in the processing chamber 1, and a magnet 4 which is placed along the periphery of the processing chamber 1. The magnet 4 forms a graded magnetic field in a manner that the field strength in a direction of E1×B, which is the drift direction of electron near the electrode 2 is weaker in the downstream than that of the upstream. At the time of etching process, a high frequency electric power is applied to the upper electrode 3 as well by an upper high frequency power source.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a plasma processing apparatus for performing plasma processing on an object to be processed such as a semiconductor substrate, and a method for manufacturing a semiconductor device using the plasma processing.

[0002]

2. Description of the Related Art In a semiconductor device manufacturing process, for example, an etching process is sometimes performed to process a thin film such as an insulating film formed on the surface of a wafer into a fine pattern. Various types of etching apparatuses have been conventionally proposed,
Among them, a magnetron-type plasma etching apparatus has attracted attention.

[0003] This magnetron type plasma etching apparatus has, for example, a pair of upper electrode and lower electrode opposed to each other in a processing chamber so that a wafer can be mounted on the lower electrode. A high-frequency power source for applying high-frequency power is connected to the lower electrode on which the wafer is mounted. After the etching gas is introduced into the processing chamber, when high-frequency power is applied to the lower electrode on which the wafer is mounted, an electric field is formed between the pair of electrodes,
This electric field generates plasma of the etching gas.
In addition, a negative self-bias voltage is generated at the lower electrode on which the wafer is mounted, whereby ions in the plasma generated in the processing chamber are attracted toward the lower electrode.
Then, the attracted ions collide with the wafer surface, whereby the thin film formed on the wafer surface is etched.

[0004] When ions collide with the wafer surface (refer to the surface of the wafer itself or the surface of a thin film formed thereon), secondary electrons are emitted from the wafer surface. The emitted secondary electrons are accelerated in a direction away from the wafer and move in the plasma because a negative self-bias voltage is generated in the lower electrode. Then, in the process of moving in the plasma, it collides with neutral atoms and molecules, causing ionization of neutral atoms and neutral molecules. Therefore, the longer the moving distance of the secondary electrons in the plasma, the higher the frequency of collision between the secondary electrons and the neutral atoms / molecules, so that the density of the plasma can be increased.

[0005] Focusing on this, in the magnetron type plasma etching apparatus, along the outer periphery of the processing chamber,
A magnet for forming a parallel magnetic field in a direction orthogonal to the electric field is arranged between the pair of electrodes. According to this,
Secondary electrons generated by collision of ions with the wafer surface are subjected to Lorentz force by an electric field and a parallel magnetic field formed between a pair of electrodes, and are orthogonal to a plane including the direction of the electric field and the direction of the parallel magnetic field. It moves (E × B drift) while performing cycloid motion in the direction (E × B direction). As a result, the moving distance of the secondary electrons in the plasma is increased, and the density of the plasma is increased.

[0006]

However, when the secondary electrons drift by E × B, the electron density becomes higher toward the downstream side in the E × B direction, so that the self-bias voltage generated at the lower electrode becomes non-uniform in the plane. Would. When the self-bias voltage generated at the lower electrode becomes non-uniform in the plane, an in-plane potential difference is generated on the surface of the wafer mounted on the lower electrode, thereby causing a current to flow on the wafer surface and destroying a gate oxide film and the like. Such charging damage may be given to the wafer. In addition, the E × B drift of the secondary electrons causes in-plane non-uniformity of the ion density incident on the wafer surface, and as a result, may cause in-plane non-uniformity in the speed of the etching process on the wafer surface.

Therefore, a magnet is designed so that a gradient magnetic field whose magnetic field strength becomes weaker toward the downstream side in the E × B direction is formed to compensate for the in-plane non-uniformity of the self-bias voltage due to the E × B drift. A technique has been proposed in which a magnet is rotated to ensure uniformity of an etching processing speed. Devices employing this technology are DR
This is called an M (Dipole Ring Magnet) plasma etching apparatus. However, in this DRM plasma etching apparatus, the magnet design must be changed many times until the optimum value of the magnetic field strength gradient is obtained so that the self-bias voltage becomes uniform in the plane. Cost is high. Further, when process conditions such as the atmospheric pressure in the processing chamber and the amount of high-frequency power applied to the lower electrode are changed, there is a problem that the magnet must be redesigned each time. Further, since the density of ions incident on the wafer surface is not necessarily uniform in the plane, a configuration for rotating the magnet is indispensable to ensure uniformity of the etching processing speed, which complicates the apparatus configuration. There are also problems.

As another technique, a constant high-frequency power is also applied to an upper electrode opposed to a lower electrode on which a semiconductor wafer is mounted, and near this upper electrode, E × of secondary electrons near the lower electrode is applied. A technique has been proposed in which secondary electrons are subjected to E × B drift in a direction opposite to the direction of B drift to thereby make the plasma density uniform in the plane. A device employing this technology is a BED (Balanced Electron D
rift) It is called plasma etching equipment.

This BED plasma etching apparatus uses a D
It has an advantage that it can be designed easily as compared with the RM plasma etching apparatus, and that a configuration for rotating the magnet is not required. However, in the BED plasma etching apparatus, the distance between the upper electrode and the lower electrode cannot be increased. This is because if the distance between the upper electrode and the lower electrode is increased, secondary electrons drifting in the vicinity of the lower electrode cannot move (diffuse) toward the upper electrode, and the plasma density cannot be made uniform in the plane. is there. If the distance between the upper electrode and the lower electrode can be increased, the in-plane pressure difference on the wafer surface can be reduced, and the uniformity of the etching rate can be further improved. Further, since the plasma potential can be lowered, damage to the inner wall of the processing chamber caused by the plasma can be reduced.

Accordingly, a first object of the present invention is to provide a plasma processing apparatus which can prevent charging damage to an object to be processed and prevent in-plane non-uniformity in the speed of plasma processing on the object to be processed. To provide.
A second object of the present invention is to provide a plasma processing apparatus capable of reducing labor and cost required for development. Further, a third object of the present invention is to provide a plasma processing apparatus capable of designing a large space between the first electrode and the second electrode.

A fourth object of the present invention is to provide a method for manufacturing a high-quality semiconductor device free from unevenness in plasma processing and charging damage.

[0012]

According to a first aspect of the present invention, there is provided a plasma processing apparatus for performing a plasma process on an object to be processed. A first electrode having a mounting surface for mounting, a second electrode disposed opposite to the mounting surface of the first electrode, and supplying a constant high-frequency power to the first electrode. A plasma generating means for generating plasma between the first and second electrodes, and a magnetic field for causing electrons in the plasma generated between the first and second electrodes to perform an E × B drift. A magnetic field forming means for forming an intensity gradient such that the magnetic field intensity on the downstream side in the E × B drift direction on the electrode side of the first electrode is weaker than that on the upstream side in the E × B drift direction;
The high-frequency power is supplied to the second electrode to generate an electric field between the second electrode and the plasma in a direction opposite to the electric field formed between the first electrode and the plasma. A plasma density adjusting means for adjusting an in-plane distribution of plasma density on the surface.

According to the present invention, since the intensity of the magnetic field formed between the first and second electrodes has a gradient, the surface of the self-bias voltage generated at the first electrode by the E × B drift is reduced. Since the internal non-uniformity is compensated to some extent, it is possible to suppress charging damage to the workpiece. Further, by adjusting the in-plane distribution of the plasma density by the plasma density adjusting means, the plasma density on the mounting surface can be made uniform in the plane.
As a result, the self-bias voltage generated in the first electrode can be made uniform in the plane, and charging damage to the object due to non-uniform self-bias voltage in the plane can be further suppressed.

Further, since the plasma density can be made uniform in the plane, the speed of the plasma processing for the object to be processed can be made uniform in the plane. Therefore, there is no need to rotate the magnet to ensure uniformity of the plasma processing speed, and the apparatus configuration can be simplified as compared with the DRM plasma processing apparatus. Furthermore, if the in-plane non-uniformity of the self-bias voltage is appropriately compensated by giving a gradient to the magnetic field strength as described above, the self-bias voltage can be made uniform by adjusting the power supplied to the second electrode. Therefore, there is no need to strictly design the magnetic field forming means. Therefore, as compared with the DRM plasma processing apparatus, the labor and cost required for developing the apparatus can be reduced.

In addition, since the magnetic field intensity on the downstream side in the E × B drift direction is weaker than that on the upstream side in the E × B drift direction, electrons drifting near the first electrode are not most downstream in the E × B drift direction. After drifting to the side, it is possible to move favorably from the vicinity of the first electrode toward the second electrode. Therefore, the distance between the first electrode and the second electrode can be designed to be wider than that of the BED plasma processing apparatus. Therefore, the in-plane pressure difference on the surface of the processing object can be reduced, and the uniformity of the plasma processing speed can be further improved. Further, since the plasma potential can be lowered, damage to the inner wall and the like of the processing chamber accommodating the first and second electrodes can be reduced.

According to a second aspect of the present invention, in the magnetic field forming means, the magnet elements which are adjacent to each other form a predetermined angle of magnetization and are substantially symmetric with respect to the center of the processing chamber. From among a plurality of magnet elements arranged along the outer periphery of the processing chamber so that the magnetization directions of
It may be configured by removing a predetermined magnet element. More specifically, as described in claim 3, the magnetic field forming means sets the direction of the magnetic field formed by the magnetic field forming means to the NS direction, and sets the direction orthogonal to the NS direction to E-S.
In the −W direction, a predetermined number of magnet elements located on the NW side and the SW side are removed from the plurality of magnet elements, and a predetermined number of magnet elements on the W side are left. Is also good.

According to a fourth aspect of the present invention, there is provided a method of manufacturing a semiconductor device by performing a plasma treatment on a surface of a semiconductor substrate, wherein the semiconductor substrate is mounted on a substrate mounting surface of a first electrode. A mounting step, and plasma generation for supplying a constant high-frequency power to the first electrode to generate plasma between the first electrode and a second electrode disposed opposite to the substrate mounting surface. A magnetic field for causing electrons in the plasma generated between the first and second electrodes to drift by E × B, and a magnetic field intensity on the first electrode side downstream of the E × B drift direction being E × B. A magnetic field forming step of forming an intensity gradient so as to be weaker than the upstream side in the B drift direction, and supplying high-frequency power to the second electrode,
A plasma density adjusting step of adjusting an in-plane distribution of plasma density on the mounting surface by generating an electric field between the second electrode and the plasma in a direction opposite to an electric field formed between the electrode and the plasma. And a method for manufacturing a semiconductor device.

According to the present invention, the same effect as that described in relation to the first aspect can be obtained, and the in-plane uniform plasma processing can be performed without causing charging damage to the semiconductor substrate. it can. Therefore, it is possible to manufacture a high-quality semiconductor device free from unevenness in plasma processing and charging damage.

[0019]

Embodiments of the present invention will be described below in detail with reference to the accompanying drawings. FIG. 1 is an illustrative sectional view showing a configuration of a plasma etching apparatus according to one embodiment of the present invention. This plasma etching apparatus is, for example, a semiconductor wafer Wa as an object to be processed.
(Exposed surface on semiconductor wafer Wa; semiconductor wafer W
a) The surface of the semiconductor wafer Wa or the surface of the thin film formed thereon is subjected to an etching process to process a thin film such as an insulating film formed on the surface of the semiconductor wafer Wa into a fine pattern. , A processing chamber 1, a lower electrode 2 and an upper electrode 3 which are disposed in the processing chamber 1 so as to face each other in a vertical direction, and a magnet 4 which is disposed along the outer peripheral surface of the processing chamber 1. .

The lower electrode 2 includes an electrode body 21 provided through the bottom of the processing chamber 1 and the electrode body 2.
1 and a wafer mounting electrode plate 22 fixed to the upper surface of the wafer. A lower high-frequency power supply 5 is connected to the electrode main body 21, and high-frequency power of a predetermined frequency (for example, 13.56 MHz) is applied from the lower high-frequency power supply 5. The upper surface of the wafer mounting electrode plate 22 is a mounting surface on which a semiconductor wafer Wa as an object to be processed is mounted.

The upper electrode 3 is arranged, for example, at a position 27 mm away from the upper surface of the lower electrode 2. The upper electrode 3 includes an electrode central portion 31 provided through the top surface of the processing chamber 1 and a ring-shaped electrode outer peripheral portion 32 provided around the electrode central portion 31.
The electrode outer peripheral portion 32 is provided so as to penetrate through the top surface of the processing chamber 1 via the insulator 321. A plurality of gas supply ports 33 are formed on the lower surface of the electrode central portion 31 so as to open. A gas supply path 34 communicating with a gas supply port 33 is formed inside the electrode central portion 31, and an etching gas as a processing gas is supplied to the gas supply path 34 from a gas supply source (not shown). It has become. As an etching gas, for example, Ar / C ₄ F ₈ / CO
/ O ₂ or the like can be used.

The electrode central portion 31 is connected to the ground and is always kept at the ground potential. On the other hand, the electrode outer peripheral portion 32 is insulated from the electrode central portion 31 (earth) by being attached to the top surface of the processing chamber 1 via the insulator 321 as described above. Is connected to the upper high-frequency power supply 6,
A predetermined frequency (for example, 10
(0 MHz).

The magnet 4 comprises a lower electrode 2 and an upper electrode 3
And a magnetic field B in one direction substantially parallel to the upper surface of the lower electrode 2 (wafer mounting electrode plate 22). As shown in FIG. 2, the magnet 4 includes, for example, 28 magnet elements 41.
When the direction of the magnetic field B is the NS direction, a gradient magnetic field is formed in which the magnetic field strength on the W (waist) side is weaker than the magnetic field strength on the E (east) side. Such a magnet 4 is, for example, substantially on a circumference centered on an axis O passing through the center of the processing chamber 1 so as to form a parallel magnetic field in the NS direction in which the magnetic field intensity distribution is substantially in-plane uniform. It can be configured by removing four magnet elements (shown by broken lines in FIG. 2) arranged on the W side from 32 magnet elements arranged at equal intervals. The magnet elements 41 located at positions symmetrical with respect to the axis O are magnetized so as to form magnetic fields in the same direction.

The magnet as the magnetic field forming means for forming the magnetic field B is not limited to the configuration shown in FIG. 2, but a gradient in which the magnetic field intensity on the W (waist) side is weaker than the magnetic field intensity on the E (east) side. Other configurations capable of forming a magnetic field may be used. When performing an etching process on the surface of the semiconductor wafer Wa, first, the semiconductor wafer Wa is mounted on the wafer mounting electrode plate 22 of the lower electrode 2 with the surface thereof facing upward. Next, the atmosphere in the processing chamber 1 is evacuated by an exhaust mechanism (not shown), and after the inside of the processing chamber 1 is almost evacuated, an etching gas is introduced into the processing chamber 1 from the gas supply path 34 and the gas supply port 33. Is done. Then, in a state where the processing gas is filled in the processing chamber 1, for example, the lower high-frequency power source 5
From the upper high frequency power supply 6 to the upper electrode 3.
0 W high frequency power is applied. Thereby, plasma of the etching gas is generated in the processing chamber 1.

The electrons in the plasma thus generated are attracted to the lower electrode 2 and the upper electrode 3, and are incident on the semiconductor wafer Wa and the upper electrode 3 on the lower electrode 2, respectively. Causes a negative self-bias voltage. As a result, a potential difference is generated between the semiconductor wafer Wa and the plasma, and an electric field (lower self-biasing electric field) E1 due to the potential difference is generated near the surface of the semiconductor wafer Wa. This lower self-bias electric field E
Due to 1, the ions in the plasma are accelerated toward the semiconductor wafer Wa and collide with the surface of the semiconductor wafer Wa, whereby the thin film formed on the surface of the semiconductor wafer Wa is etched.

When the ions collide with the surface of the semiconductor wafer Wa, secondary electrons are emitted from the surface of the semiconductor wafer Wa. The emitted secondary electrons are applied to the lower self-biasing electric field E1 and the magnetic field B formed by the magnet 4.
Of the lower self-bias electric field E1 and the direction perpendicular to the plane including the direction of the magnetic field B (E1 × B direction) while drifting. This allows secondary electrons to drift a long distance in the plasma, so that the frequency of collision between the secondary electrons and neutral atoms / molecules can be increased, and the density of the plasma can be increased.

Further, in this embodiment, the magnetic field intensity formed in the magnetic field B formed by the magnet 4 becomes lower toward the downstream of the E1 × B direction (the W side shown in FIG. 2) which is the electron drift direction near the lower electrode 2. The slope is weakened. As a result, the in-plane non-uniformity of the self-bias voltage generated in the lower electrode 2 due to the drift of electrons is compensated to some extent, so that charging damage due to the in-plane non-uniformity of the self-bias voltage is suppressed from being applied to the semiconductor wafer Wa. it can.

On the other hand, when a negative self-bias voltage is generated in the upper electrode 3, a potential difference is also generated between the upper electrode 3 and the plasma, and an electric field (upper self-bias electric field) E2 due to this potential difference is generated on the lower surface of the upper electrode 3. It occurs near. Therefore, near the lower surface of the upper electrode 3, electrons in the plasma receive Lorentz force due to the upper self-biasing electric field E2 and the magnetic field B formed by the magnet 4,
It drifts while cycloidally moving in a direction (E2 × B direction) perpendicular to the plane including the direction of the upper self-bias electric field E2 and the direction of the magnetic field B. The electron drift direction (E2 × B direction) is opposite to the secondary electron drift direction (E1 × B direction) near the surface of the semiconductor wafer Wa. Therefore, if the magnitude of the high-frequency power applied to the upper electrode 3 is set so that the upper self-bias electric field E2 of an appropriate strength is generated, the electrons in the plasma can be dispersed almost uniformly. The plasma density distribution on the wafer Wa can be made uniform in the plane. Therefore, a uniform plasma etching process can be performed on the semiconductor wafer Wa.

FIG. 3 is a view showing the in-plane distribution of the self-bias voltage Vdc generated in the lower electrode 2 in the plasma etching apparatus according to this embodiment, and FIG.
FIG. 4 is a diagram showing an in-plane distribution of a self-bias voltage Vdc generated at a lower electrode in a D plasma etching apparatus. The conventional BED plasma etching apparatus is an apparatus as described in the section of “Problems to be Solved by the Invention”, and is for forming a parallel magnetic field having a uniform magnetic field intensity distribution between the lower electrode and the upper electrode. It has a magnet.
The distance between the lower electrode and the upper electrode is set to 27 mm as in the device according to this embodiment.

FIGS. 3 and 4 show that 13.5 is applied to the lower electrode.
A high-frequency power of 6 MHz and 800 W is supplied, and a high-frequency power of 13.56 MHz and 800 W is applied to the lower electrode. And the self-bias voltage Vdc generated at the lower electrode when 100 MHz, 100 W high frequency power is supplied to the upper electrode.
And a curve C2 representing the in-plane distribution of the graph. In FIGS. 3 and 4, the horizontal axis represents W on the lower electrode.
The position in the −E direction is taken, and the vertical axis represents the absolute value of the self-bias voltage Vdc generated at the lower electrode.

3 and 4 show that the conventional BED
In a plasma etching apparatus, if no high-frequency power is applied to the upper electrode, the self-bias voltage Vdc generated at the lower electrode
According to the present embodiment in which the magnetic field B formed by the magnet 4 has a gradient, the self-bias generated in the lower electrode 2 can be achieved without applying high frequency power to the upper electrode 3. It is understood that the variation of the voltage Vdc is small. Also, curves C1 and C2 in FIG.
It is understood from the comparison with the above that when the high-frequency power is applied to the upper electrode 3, the variation of the self-bias voltage Vdc generated in the lower electrode 2 is further suppressed. Therefore, according to this embodiment, the self-bias voltage Vdc generated in the lower electrode 2 can be made substantially uniform in the plane, and the charging damage to the processing object due to the non-uniform self-bias voltage Vdc in the plane can be further suppressed. can do. If the in-plane non-uniformity of the self-bias voltage Vdc is moderately compensated by giving a gradient to the magnetic field intensity, the self-bias voltage Vdc can be made substantially uniform by applying high-frequency power to the upper electrode 3. Therefore, it is not necessary to strictly design the magnet 4, and the labor and cost required for developing the device can be reduced.

FIG. 5 shows an ion current density J on the lower electrode 2 in the plasma etching apparatus according to this embodiment.
FIG. 6 is a diagram showing an in-plane distribution of ions, and FIG.
FIG. 4 is a diagram showing an in-plane distribution of an ion current density Jion on a lower electrode in a plasma etching apparatus. FIGS. 5 and 6 show a curve C3 representing the in-plane distribution of the ion current density Jion when a high frequency power of 13.56 MHz and 1500 W is supplied to the lower electrode and no high frequency power is supplied to the upper electrode. And a curve C4 representing the in-plane distribution of the ion current density Jion when a high frequency power of 13.56 MHz and 800 W is supplied to the upper electrode and a high frequency power of 100 MHz and 100 W is supplied to the upper electrode. In FIGS. 5 and 6, the horizontal axis represents the WE on the lower electrode.
The vertical axis indicates the value of the ion current density Jion.

From the comparison between FIG. 5 and FIG.
In a plasma etching apparatus, when the distance between the lower electrode and the upper electrode is set to 27 mm, the in-plane distribution of the ion current density Jion on the lower electrode regardless of whether high frequency power is supplied to the upper electrode. In contrast, in the plasma etching apparatus according to the present embodiment, when high-frequency power is applied to the upper electrode 3, the in-plane distribution of the ion current density Jion on the lower electrode 2 varies. It is understood that it is small. Even if the distance between the lower electrode 2 and the upper electrode 3 is set relatively large, the in-plane distribution of the ion current density Jion can be made substantially uniform because the electron drift direction near the lower electrode 2 Since the magnetic field strength on the downstream side in the E1 × B direction is weaker than that on the upstream side, electrons drifting in the vicinity of the lower electrode 2 can move favorably from the vicinity of the first electrode toward the second electrode. Because.

According to this embodiment, the distance between the lower electrode 2 and the upper electrode 3 can be designed to be wider than that of the conventional BED plasma processing apparatus, so that the in-plane pressure difference on the surface of the workpiece can be reduced. The size can be reduced, and the uniformity of the plasma processing speed can be further improved. Also,
Since the plasma potential can be lowered, damage to the inner wall of the processing chamber 1 caused by the plasma can be reduced. FIG. 7 shows a plasma etching apparatus according to this embodiment, in which a Si wafer formed on a surface of a semiconductor wafer Wa is formed.
FIG. 8 is a diagram showing the in-plane distribution of the etching rate when the O ₂ etching processing is performed. FIG. 8 shows the etching processing of the SiO ₂ formed on the surface of the semiconductor wafer Wa in the conventional BED plasma etching apparatus. It is a figure which shows the in-plane distribution of the etching processing speed at the time of performing.

FIGS. 7 and 8 show a curve C5 showing the in-plane distribution of the etching rate in the WE direction and a curve C6 showing the in-plane distribution of the etching rate in the NS direction. I have. 7 and 8, the horizontal axis indicates the position on the surface of the semiconductor wafer Wa, and the vertical axis indicates the value of the etching rate (Etch Rate). 7 and 8, it can be seen from the comparison of the conventional BED plasma etching apparatus that the etching processing speed varies greatly in the conventional BED plasma etching apparatus, whereas the plasma etching apparatus according to the present embodiment shows that the etching processing speed is substantially uniform in the plane. Can understand. Therefore, in the plasma etching apparatus according to this embodiment, it is not necessary to rotate the magnet 4 in order to secure uniformity of the etching processing speed,
The apparatus configuration can be simplified as compared with the DRM plasma processing apparatus.

Although the rotation of the magnet 4 is not described in this embodiment, the magnet 4 may be rotated about an axis O passing through the center of the processing chamber 1 or may be fixedly arranged so as not to rotate. It may be. However, by rotating the magnet 4, the in-plane distribution of the etching processing speed can be made more uniform. Further, the present invention can be embodied in other forms. For example, in the above-described embodiment, a plasma etching apparatus has been described as an example. However, the present invention is not limited to this plasma etching apparatus. For example, plasma processing is performed on an object to be processed by a plasma ashing apparatus or a plasma CVD (Chemical Vapor Deposition) apparatus. The present invention can be widely applied to a coating apparatus.

In addition, various changes can be made within the scope of the matters described in the claims.

[Brief description of the drawings]

FIG. 1 is an illustrative sectional view showing a configuration of a plasma etching apparatus according to an embodiment of the present invention.

FIG. 2 is an illustrative plan view for describing a configuration of a magnet.

FIG. 3 is a diagram showing an in-plane distribution of a self-bias voltage generated in a lower electrode in the plasma etching apparatus according to the embodiment.

FIG. 4 is a diagram showing an in-plane distribution of a self-bias voltage generated in a lower electrode in a conventional BED plasma etching apparatus.

FIG. 5 is a diagram showing an in-plane distribution of ion current density on a lower electrode in the plasma etching apparatus according to the embodiment.

FIG. 6 is a diagram showing an in-plane distribution of ion current density on a lower electrode in a conventional BED plasma etching apparatus.

FIG. 7 is a diagram showing an in-plane distribution of an etching processing speed when etching is performed on SiO ₂ formed on the surface of a semiconductor wafer in the plasma etching apparatus according to this embodiment.

FIG. 8 is a diagram showing an in-plane distribution of an etching processing speed when etching is performed on SiO ₂ formed on the surface of a semiconductor wafer in a conventional BED plasma etching apparatus.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Processing chamber 2 Lower electrode (1st electrode) 3 Upper electrode (2nd electrode) 4 Magnet (magnetic-field formation means) 41 Magnet element 5 Lower high-frequency power supply (plasma generation means) 6 Upper high-frequency power supply (plasma density adjustment means) B Magnetic field E1 × B drift direction (E × B drift direction) E1 Lower self-bias electric field (electric field formed between first electrode and plasma) E2 Upper self-bias electric field (formed between second electrode and plasma) Electric field) Wa Semiconductor wafer (workpiece)

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Ryu Umihara 05 Aoba, Aramaki, Aoba-ku, Sendai-shi, Miyagi Pref. (72) Inventor Hisaka Ohmasa 21 F. Term, Rohm Co., Ltd., 21 Mizozaki-cho, Ukyo-ku, Kyoto City (Reference) 4K030 CA04 FA03 HA06 JA07 KA30 KA32 KA34 LA15 4K057 DA16 DB06 DD01 DE06 DE14 DE20 DM03 DM16 DM24 DN01 5F004 AA01 AA06 BA08 BA09 BB07 BB13 BD01 BD04 CA03 CA06 DA00 DA23 DA26 DB03

Claims (4)

[Claims] 1. A plasma processing apparatus for performing plasma processing on an object to be processed, comprising: a first electrode having a mounting surface on which the object is mounted; and a mounting surface of the first electrode. A second electrode disposed opposite to the first electrode; a plasma generating means for supplying a constant high-frequency power to the first electrode to generate plasma between the first and second electrodes; And a magnetic field for causing the electrons in the plasma generated between the second electrodes to perform an E × B drift, such that the magnetic field strength on the first electrode side on the downstream side in the E × B drift direction is higher than that on the upstream side in the E × B drift direction. Magnetic field forming means for forming an intensity gradient so as to be weaker, and supplying high frequency power to the second electrode to generate an electric field in a direction opposite to an electric field formed between the first electrode and plasma. What is generated between the second electrode and the plasma The plasma processing apparatus which comprises a plasma density adjusting means for adjusting the in-plane distribution of the plasma density on the placing surface. 2. The magnetic field forming means, wherein magnetization directions of magnet elements adjacent to each other form a predetermined angle, and
From a plurality of magnet elements arranged along the outer periphery of the processing chamber such that the magnetization directions of the magnet elements at positions substantially symmetric with respect to the center of the processing chamber are substantially the same, a predetermined magnet element is formed. 2. The plasma processing apparatus according to claim 1, wherein the plasma processing apparatus is configured by removing. 3. The magnetic field forming means according to claim 1, wherein a direction of a magnetic field formed by said magnetic field forming means is an NS direction, and a direction orthogonal to said direction is an EW direction. 3. A plasma processing method according to claim 2, wherein a predetermined number of magnet elements located on the NW side and the SW side are removed from the above, and a predetermined number of magnet elements on the W side are left. apparatus. 4. A method for manufacturing a semiconductor device by performing a plasma process on a surface of a semiconductor substrate, the method comprising: mounting a semiconductor substrate on a substrate mounting surface of a first electrode; A plasma generation step of supplying a constant high-frequency power to a first electrode to generate plasma between a second electrode disposed opposite to the first electrode and the substrate mounting surface; And a magnetic field for causing the electrons in the plasma generated between the second electrodes to perform an E × B drift by changing the magnetic field strength on the first electrode side downstream of the E × B drift direction from the upstream side of the E × B drift direction. A magnetic field forming step of forming an intensity gradient so as to be weaker, and supplying high-frequency power to the second electrode to generate an electric field in a direction opposite to an electric field formed between the first electrode and plasma. Between the second electrode and the plasma And a plasma density adjusting step of adjusting the in-plane distribution of the plasma density on the mounting surface by producing the semiconductor device.