JP2001337847A - Processor circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a processor circuit which utilizes the idle time of a processor efficiently, and further performs higher speed processing by the processor, and an idle time measuring device employing the same. SOLUTION: The processor circuit has an output port 5 which holds predetermined output level for a certain time period, and then inverts to return to the steady state, only when no tasks are executed except for the task executed for only wasting the processing time of a processor 2.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a processor circuit, and more particularly to a processor circuit which operates by so-called multitask programming for executing a plurality of tasks in parallel.

[0002]

2. Description of the Related Art Conventionally, so-called multitask programming for executing a plurality of tasks in parallel has been performed in a processor. This is because, in general, the real-time OS (RTOS) puts the task that has the highest priority at that time into an execution state, so that a plurality of processes assigned to each task are effectively realized at the same time. In other words, for example, operations performed by humans or processing that is slower than the processing capability of a processor (CPU), such as a peripheral device such as a hard disk or a printer, are performed as if each task were executed in a time-sharing manner. It can be operated in parallel as independent processing as if the CPU were monopolized.

[0003] Regardless of whether or not an RTOS is used, an interrupt is generated due to a match of a timer counter or an input signal to an external port, and a corresponding process is started, so that the processor can operate as if it were a plurality. Can be performed as if they are being executed at the same time.

[0004]

However, in such multi-task programming, there is actually a time when all tasks are not executed, that is, a free time of the processor, and it is necessary to increase the processing amount for this time. In some cases, the performance of a device in which this processor is incorporated can be improved. However, if the amount of processing is increased, there is no room for the processing time of the processor.Therefore, in order to determine a safe increase in the processing amount, it is necessary to know the free time of the processor correctly. It was difficult to quantify with high accuracy.

That is, conventionally, a method has been considered in which, for example, port output is appropriately performed at various points in a program statement, and this is observed from the outside. However, in this method, processing is terminated at the end of each processing section, that is, processing is performed at another processing section. It was necessary to know exactly what had shifted, and for that, the processor had to individually measure all the time devoted to practical processing and sum them up. At this time, the above-described interrupt processing must also be a measurement target as long as it is likely to be executed. In order to perform such a measurement, an instruction code for performing port output must be added to a necessary part of the program as needed, but on the other hand, there is a problem that the instruction code itself causes an error in a measurement result. is there.

Further, a method has been considered in which a general-purpose timer interrupt provided in a processor is used to continuously reset a counter in a section to be measured. In this case, if the processing is shifted to a section that is not to be measured, an interrupt is eventually generated. Conversely, the fact that this interrupt has not been generated indicates that the processing section has been executed for a period of time (substantially, of the processor). (Free time). However, this method has a fundamental problem that the general-purpose timer interrupt function of the processor must be devoted to measuring the processing time.

Furthermore, a debugger compatible with the RTOS generally has a function of visually displaying the execution state of a task, but the measurement accuracy is several tens ms to several hundreds ms.
It is an order and in order to perform higher-precision measurement,
As in the past, the method has to rely on a method of tracing a program one step at a time to accumulate processing time, which has a problem that the storage capacity of the trace result is limited, or that setting and procedures are complicated.

As described above, conventionally, it has been difficult to simply and accurately determine the idle time of the processor.

[0009] Conventionally, in the above-mentioned processor, a fixed time interval often has to be intentionally created by a program. this is,
For example, this is a process in which the level of a signal connected to the light emitting device is periodically switched to create blinking light.

As a specific method, as shown in FIG. 5, for example, assuming that control is performed by an RTOS, even if processing requests are continuously made from a host device, the processing requests are accepted for a certain period of time. It is done while placing. However, in this method, it is difficult to accurately control the delay time in a unit of several μs, so that when this method is adopted, it is permissible that a delay larger than an actually required time interval is generated. There must be.

In this method, that is, by executing the instruction code of several steps to several tens steps without using the function of the RTOS, a certain time interval can be provided. Specifically, for example, the second and third
This is the method.

As a second method, as shown in FIG.
The time elapsed from the previous process is measured by a program, the progress is determined, and the execution of the process is controlled based on the determination. In this case, the determination as to whether or not a predetermined time has elapsed from the previous processing includes (1) capturing a timer request flag, (2) comparing the flag, and (3) returning to (1) if there is no interrupt request. (4) The interrupt request is cleared and the subsequent processing is continued. The reset of the clock is performed in such a procedure as (1) writing # 0 into a timer counter (a counter updated with the clock) and (2) restarting the timer.
Further, (1) prohibition of interruption to this timer, (2)
Setting of clock, frequency division ratio, etc., (3) setting of capture counter (compared value for judging timeout),
(4) Initial settings such as writing an initial value to the timer counter must be performed. However, in this case, the functions required for time measurement need not be complicated and versatile timer functions generally provided in a processor, but very simple functions are sufficient.

As a third method, as shown in FIG.
Regardless of how much time has elapsed since the previous processing was executed, after receiving a processing request, a certain amount of time is spent before executing the requested processing. This method does not require a timer function, and is simple to program (for example, it can be realized by stacking as many instruction codes as necessary to waste time unnecessarily), so that a small time unit can be realized. Can handle. However, even in this method, at the stage of making a processing request, even if sufficient time has elapsed since the previous processing, the time interval that must be guaranteed is unconditionally wasted. Become. That is, the delay of this time interval always occurs every time from when the processing request is issued to when the processing is actually executed.

As described above, conventionally, it has been difficult to simply and accurately determine the time interval by the processing of the processor.

As described above, in the conventional processor circuit, the measurement of the idle time of the processor and the control of the time interval could not be performed simply and with high accuracy, so that the processing capability of the processor was effectively used. There was a problem that it could not be done.

The present invention has been made in view of such a problem, and in order to effectively use the processing capability of a processor,
It is an object of the present invention to provide a processor circuit that enables simple and accurate time measurement and time control.

[0017]

In order to achieve the above object, a processor circuit according to the present invention is characterized in that a processing section (IDL) which simply wastes the processing time of the processor.
E section), when there is no other task to be executed, the IDLE section is executed and the IDE
In the L section, programming is performed so as to continue to specify the output level of the output port and the time to hold it,
According to the state of the output port, the fact that the IDLE section is being executed, that is, that there is no other task to be executed (the idle time of the processor has occurred) can be observed from outside the processor. It is in the point which did.

That is, a device for measuring the output level of the output port is connected to the output port, and the output port obtains the time indicating the designated output level, thereby increasing the idle time of the processor. It can be measured with high accuracy.

Alternatively, a device for converting the output level of the output port into a visible or audible signal is connected to the output port, and it is possible to sense whether the output port indicates a specified output level. In such a case, it may be possible to easily determine that the processor has idle time.

In the above description, the specification of the output level of the output port and the time at which the output level is to be held is not always performed at only one location in the processing section in which the processing time of the processor is simply wasted. Which part of the processing section is to be performed should be changed according to the purpose.

Also, a feature of the processor circuit according to the present invention is that an output port for holding a designated output level for a designated time and thereafter inverting and returning to a steady state is provided.
Along with the state of the output port, the function information set in the circuit and the internal information in the operation process are connected to the input / output space of the processor as a register. The point is that input and output can be freely performed.

That is, by changing the contents of these registers by a program, it is possible to freely change the output level and the time for which the output level is to be held. By doing so, it is possible to easily and accurately determine the elapse of a minute time without allocating the general-purpose timer function of the processor.

Further, by combining the above means, the processing capability of the processor can be more effectively utilized.

[0024]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a first embodiment of a processor circuit according to the present invention will be described with reference to FIGS.

The processor circuit 1 according to the first embodiment
Has a processor 2 on a control board (not shown).

An output port 5 is connected to the processor 2 via an address bus 3 and a data bus 4.

The output port 5 has a selector 6. The selector 6 has a write enable signal (wen in FIG. 1) and a signal (FIG. 1) for selecting a counter 7 or a register 8 described later. sel)
A signal such as input data (din in FIG. 1) to be written into the counter 7 and the register 8 is input.

The selector 6 determines the result (out in FIG. 1) of wen, sel, or the result of comparing a counter 7 described later with the register 8.
Then, based on the determination, a signal obtained by adding din to the data to the counter 7 (d-cnt in FIG. 1) or the data to the register 8 (d-reg in FIG. 1) to +1 or -1. (Up in FIG. 1
d) or the comparison value (reg) of the register 8 is substituted.

A counter 7 is connected to the selector 6. This counter 7 receives a clock signal (clk)
The data (d-cnt) from the selector 6 is fetched in synchronism with the above, and the fetched value is output as the value (cnt) of the counter 7.

The counter 7 includes an up / down unit 9
Is connected to a signal (fnc) for selecting the function (+ 1 / −1) of the counter 7.
Is entered. The up / down unit 9 adds the current value of the counter 7 based on the fnc to +
The value (upd) is output to the selector 6 as well as 1 or -1.

A register 8 is connected to the selector 6, and the register 8 holds a comparison value (reg). This comparison value (reg) is output to the selector 6.

A comparator 10 is connected to the counter 7 and the register 8, and the comparator 10 outputs a result (out) of comparing the contents of the counter 7 and the register 8 with each other. This result is obtained, for example, by measuring the output waveform of a logic analyzer, etc.
Depending on the recording device, it can be observed as a waveform as shown in FIG. 2 or FIG.

The output port 5 having such a configuration is
Under the control of the processor 2, the predetermined output level (voltage) is held only during a time when all tasks other than the task executed only to waste the processing time of the processor 2 are not executed. It has become.

Here, the predetermined output level is defined as the level shown in FIG.
As shown in FIG. 3 and FIG. 3, the output level is higher or lower than a certain value (0 in FIGS. 2 and 3).

Hereinafter, a state in which the output port 5 has not reached the predetermined output level (0 in FIGS. 2 and 3) is referred to as a steady state. Further, the process of reactivating the output level to the predetermined output level is called refresh.

As shown in FIG. 2, after the output level of the output port 5 reaches a predetermined output level, it naturally attenuates and returns to a steady state. That is, the output level of the output port keeps the predetermined output level for a certain period of time and then reverses to return to a steady state. However, as long as the refresh is repeated, a predetermined output level is maintained as shown in FIGS.

Note that, as described above, the refresh operation is performed within a time period in which all tasks other than the task executed merely to waste the processing time of the processor 2 are not executed. This refresh may be executed in the idle task having the lowest priority, that is, without the substance of the process (hereinafter referred to as task i), and the refresh may be described in the RTOS kernel. It may be executed. Therefore, when the refresh is executed in the task i, the time during which all the tasks other than the task executed merely to waste the processing time of the processor 2 are not executed is the time other than the task i to be refreshed. Is a time during which all tasks are not executed (hereinafter, the same meaning is used unless otherwise specified).

Next, the operation of the first embodiment will be described.

In this embodiment, the refresh is performed by the task i having the lowest priority. In the present embodiment, a result (out) of comparing the contents of the counter and the register by connecting a device for measuring and recording an output waveform such as a logic analyzer to the output destination of the output port 5, that is, the output port 5 is observed.

First, when the program is started, a predetermined output level to be held for the output port 5 is set to a state higher than the steady state as shown in FIG. 2 or lower as shown in FIG. Set whether to be in the state. further,
At this time, a time interval T of each output level, that is, a refresh cycle is set. The setting of the time interval T may be performed by giving a counter in units of several tens of ns to state or several μs.

The task i basically repeats an infinite loop because it does not try to receive a message, but it is actually stopped when another task is running. Then, when all the tasks other than the task i have stopped their operations and are waiting for an interrupt, the RTOS kernel activates the task i to start the execution of the refresh. Note that the refresh may be started by writing a predetermined level to be held, or by writing a counter when the time interval T is set.

By starting the refresh, the output port 5 can hold a predetermined output level. At this time, the output level waveform of the output port 5 is measured by a device for measuring the output waveform such as the logic analyzer.

As a result, as shown in FIGS. 2 and 3, the holding time of the predetermined output level, that is, the activation time of task i can be measured.

Therefore, according to the first embodiment, the output port 5 that holds the predetermined output level only during the time when all tasks other than the task i are not executed is provided. By measuring the holding time of the predetermined output level, the idle time of the processor 2 can be determined with high accuracy. Further, since it is only necessary to embed “refresh” in the measurement section of the program, the program can be easily modified. Therefore, the burden on the processor 2 is small, the configuration is simple, and the reliability of the measurement itself is high.

Next, the second embodiment of the processor circuit according to the present invention will be described.
An embodiment will be described.

The processor circuit (not shown) according to the second embodiment does not differ from the processor circuit 1 according to the first embodiment in the basic configuration.

The processor circuit according to the second embodiment has the same output port (not shown) as the output port 5.
have.

The output destination of this output port is connected to an input / output space of another processor circuit (not shown) via a signal line.

The other processor circuit repeats the same process (task execution) a plurality of times in succession. At this time, a predetermined time interval is set between the previous process and the subsequent process. It is designed to be provided.

The processor circuit according to the second embodiment interrupts the other processor circuit using the output of the output port in order to control the predetermined time interval. That is, in the second embodiment, the processor circuit is used as a timer function.

Next, the operation of the second embodiment will be described.

First, the resetting of the timer function is performed at the start of the refresh of the output port, that is, when the predetermined output level rises.

Then, it is determined whether or not a predetermined time has elapsed from the previous processing by the other processor circuit.
This determination is made by determining whether the output of the output port has returned to a steady state after the rise of the predetermined output level. This judgment can be generally performed by one instruction.

If the output of the output port has not returned to the steady state, the above determination is made again without starting the subsequent processing. On the other hand, when the output of the output port returns to the steady state, the subsequent processing is started. This is a process having both the advantages of the above-described conventional second method (FIG. 5) and third method (FIG. 6). That is, in the second embodiment, similarly to the third method, only a small time unit can be handled by simple programming (in this second embodiment, “refresh” is embedded in a program measurement section). Instead, the time interval can be appropriately controlled by the timer function as in the second method. Further, differently from the second method, the determination as to whether or not a predetermined period of time has elapsed in the previous processing is (1) comparison with the input of the port, and (2) the processing returns to (1) if the state has not returned to the steady state. , And so on. In addition, resetting of the clock is sufficient only by refreshing the port. Furthermore, the initial settings need only be (1) setting the level to be held, and (2) setting the time to be held (T in FIGS. 2 and 3).

Therefore, according to the second embodiment, it is possible to easily determine whether or not a predetermined time has elapsed from the previous processing based on the output level of the output port. When the same process is executed a plurality of times in succession, a fixed time interval between the previous process and the subsequent process can be easily and accurately controlled.

Next, the third embodiment of the processor circuit according to the present invention will be described.
As an embodiment, an embodiment of a processor free time measuring apparatus to which a processor circuit according to the present invention is applied will be described with reference to FIG. It should be noted that portions having the same or similar basic configuration as the first embodiment of the processor circuit 1 will be described using the same reference numerals.

The processor free time measuring device 12 in this embodiment has the processor circuit 1.

The output port 5 of the processor circuit 1 is connected to a measuring unit 13 for measuring the output level waveform of the output port 5. The measurement unit 13 may be, for example, a logic analyzer.

Further, the measuring unit 13 is connected to a calculating unit 14 for calculating the idle time of the processor 2 based on the predetermined output level measured by the measuring unit 13. Based on the time during which the predetermined output level is held, the operation unit 14 is a time during which all tasks other than the task executed to simply waste the processing time of the processor 2 are not executed. The idle time of the processor 2 is calculated.

Next, the operation of the present embodiment will be described. In this embodiment, the refresh is performed by the task i having the lowest priority.

When the program is started, the predetermined output level to be held for the output port 5 is set to a state higher than the steady state as shown in FIG. 2 or lower as shown in FIG. Set whether to be in the state. further,
At this time, a time interval T of each output level, that is, a refresh cycle is set. The setting of the time interval T may be performed by giving a counter in units of several tens of ns to state or several μs.

The task i basically repeats an infinite loop because it does not try to receive a message. However, the task i is practically stopped when another task is running. Then, when all the tasks other than the task i have stopped their operations and are waiting for an interrupt, the RTOS kernel activates the task i to start the execution of the refresh. Note that the refresh may be started by writing a predetermined level to be held, or by writing a counter when the time interval T is set.

By starting the refresh, the output port 5 can hold a predetermined output level. At this time, the waveform of the output level of the output port 5 is measured by the measuring unit 13.

Then, the calculating unit 14 calculates the idle time of the processor 2 based on the predetermined output level of the output port 5 measured by the measuring unit 13. Since the holding time of the predetermined output level corresponds to the time during which all tasks other than the task i are not executed, that is, the idle time of the processor, the idle time can be easily measured.

Therefore, according to the present embodiment, the holding time (FIGS. 2 and 3) of the predetermined output level by the output port 5 is measured by the measuring unit 13 and the idle time of the processor 2 is determined based on the measurement result. Can be calculated by the calculation unit 14, so that the idle time of the processor 2 can be determined with high accuracy. Also, since it is only necessary to embed "refresh" in the measurement section of the program,
The program can be easily modified. Therefore, the burden on the processor 2 is small, the configuration is simple, and the reliability of the measurement itself is high.

The present invention is not limited to the above-described embodiment, but can be variously modified as needed.

For example, by connecting a display device such as an LED to the output port 5, the current value (cnt) of the counter 7 and the result (out) of comparing the counter 7 with the register 8 are visually displayed. It may be. In this case, for example, the blinking interval or the brightness of the LED may be changed depending on the idle time of the processor 2 or the frequency (temporal density) at which a specific processing section is executed. Alternatively, a buzzer or the like may be connected to the output port 5 so as to notify by sound, instead of visually displaying.

Furthermore, the unused bits of the general-purpose input / output port
It may be assignable. Furthermore, independent and parallel measurement may be performed not only for one bit but also for a plurality of bits. It can also be 8, 16 or 32 bits. Further, the predetermined output level may be held until a timer interrupt or a port interrupt occurs. Further, the time during which the output level is held may be internally counted to generate an interrupt.

By combining these, it is possible to apply an application such as quantifying the internal stress based on the time based on the number of times a certain process is performed and issuing a warning or a stop.

Further, together with the state of the output port 5,
The function information set in the processor circuit 1 and the internal information in the operation process are connected as a register to the input / output space of another processor circuit, and the contents of the register are stored in a program executed in the other processor circuit. May be freely input / output.

In such a case, by changing the contents of the register by a program, the output level of the output port 5 and the time (T in FIG. 3) for holding the output level can be freely changed. By reading the contents of the register programmatically and determining this,
Without losing the general-purpose timer function of the processor, the elapse of a minute time can be determined easily and with high accuracy.

Further, the specification of the output level of the output port 5 and the time to hold it is not always performed in only one processing section in which the processing time of the processor is simply wasted. Which part of the section is performed should be changed according to the purpose.

[0073]

As described above, according to the processor circuit of the present invention, the idle time of the processor can be indicated by the output port, and the output level of this output port is measured to determine the idle time of the processor. Since the output level can be used as a timer function when another processor performs the same processing a plurality of times in succession, effective use of the idle time of the processor and further high-speed processing by the processor can be performed. It can be realized.

[Brief description of the drawings]

FIG. 1 is a diagram showing an embodiment of a processor circuit according to the present invention.

FIG. 2 is a diagram showing a level output of an output port in the embodiment of the processor circuit according to the present invention;

FIG. 3 is a diagram showing a level output of an output port in the embodiment of the processor circuit according to the present invention, which is different from FIG. 2;

FIG. 4 is a block diagram showing an embodiment of a processor free time measuring apparatus to which the processor circuit is applied in the embodiment of the processor circuit according to the present invention;

FIG. 5 is an explanatory view showing a first method conventionally employed for providing a certain time interval between a previous process and a subsequent process and performing the same process continuously a plurality of times;

FIG. 6 is an explanatory diagram showing a second method which has been conventionally adopted for providing a certain time interval between a previous process and a subsequent process and performing the same process continuously a plurality of times;

FIG. 7 is an explanatory diagram showing a third method conventionally employed for performing the same process a plurality of times continuously with a certain time interval provided between a previous process and a subsequent process.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Processor circuit 2 Processor 5 Output port 12 Free time measuring device for processor 13 Measurement unit 14 Operation unit

Claims (5)

[Claims] 1. A processor circuit comprising an output port for holding a designated output level for a designated time and then inverting the output level to return to a steady state. 2. An output port for holding a designated output level for a designated time and thereafter inverting and returning to a steady state, wherein the output port is held at the designated output level. A processor circuit to which a device for measuring time spent is connected. 3. An output port for holding a specified output level for a specified time and then inverting and returning to a steady state, wherein the output level of the output port is a visible or audible signal. A processor circuit, which is connected to a device for converting data into a data. 4. An output port for holding a designated output level for a designated time, and thereafter inverting and returning to a steady state, wherein the output port is connected to an input / output space of a processor. Processor circuit. 5. A value indicating an output level of an output port provided in the circuit, a value indicating a time to hold the output port, and a value indicating other function information, or a value indicating a process in which the circuit operates. A processor circuit, wherein a value indicating internal information is connected as a register to an input / output space of a processor.