JP2001337728A - Voltage detecting device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a voltage detecting device which can hasten a response time for output without increasing consumed current against up and down of detected voltage of power supply. SOLUTION: In normal condition, detected voltage VD is inputted to a transistor Q2, and simultaneously a reference voltage VR is inputted to a transistor Q2. If the detected voltage VD is lower than the reference voltage VR, a transistor Q6 is turned on. Following this, inputs to the transistors Q1, Q2 are changed by switching of switch elements 131-134, and the transistor Q6 becomes off. If the detected voltage is higher than the reference voltage, the transistor Q6 goes back to off. A circuit generating a signal for power output 16 generates the signal responding to the result of the detected voltage by using the timing that the transistor Q6 becomes on.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] The present invention relates to a battery voltage life,
The present invention relates to a voltage detection device that detects a decrease in a power supply voltage of a microcomputer and outputs a predetermined signal in response to the detection, and particularly to a response device that has a quick response time when the detected voltage decreases and increases.

[0002]

2. Description of the Related Art As a conventional voltage detecting device of this kind,
For example, the one shown in FIG. 6 is known.

[0003] As shown in FIG.
It comprises at least a voltage detection circuit 1, a reference voltage generation circuit 2, a differential amplification circuit 3, a binary signal output circuit 4, and an inverter 5.

As shown in FIG. 6, a voltage detection circuit 1 divides a power supply voltage V of a power supply (not shown) by resistors R1 and R2,
The divided voltage is obtained as the detection voltage VD of the power supply. An NMOS transistor Q8 for hysteresis is connected between an intermediate terminal of the resistor R2 and the ground. The reference voltage generation circuit 2 generates a reference voltage VR to be input to the differential amplifier circuit 3.

The differential amplifier circuit 3 receives the detection voltage VD of the voltage detection circuit 1 and the reference voltage VR from the reference voltage generation circuit 2 and outputs an output voltage corresponding to the difference between the two voltages. . That is, as shown in FIG. 6, the differential amplifier circuit 3 includes two input signal NMOSs forming a differential pair.
An N for a constant current source for supplying a constant current to the transistors Q1 and Q2 and a differential pair of the NMOS transistors Q1 and Q2.
It comprises a MOS transistor Q3 and PMOS transistors Q4 and Q5 forming a current mirror circuit.

The gate of the NMOS transistor Q1 has
The detection voltage VD detected by the voltage detection circuit 1 is input,
The reference voltage VR generated by the reference voltage generation circuit 2 is input to the gate of the NMOS transistor Q2. Further, a predetermined DC bias voltage VB is supplied to the gate of the NMOS transistor Q3.

[0007] The binary signal output circuit 4 receives the output signal of the differential amplifier circuit 3 and generates a binary signal corresponding to the input signal. As shown in FIG. , A PMOS transistor Q6 and an NMOS transistor Q7 for a constant current source are connected in series. And PM
The drain voltage of the NMOS transistor Q2 is supplied to the gate of the OS transistor Q6. A predetermined DC bias voltage VB is supplied to the gate of the NMOS transistor Q7, whereby the NMOS transistor Q7 forms a constant current source circuit. The inverter 5 inverts the binary signal of the binary signal output circuit 4, and its input is connected to a common connection of the MOS transistors Q 6 and Q 7, and its output is connected to the output terminal 6.

Next, an example of the operation of the conventional voltage detecting device having such a configuration will be described with reference to FIG.

Now, for example, when the detection voltage VD of the voltage detection circuit 1 exceeds the reference voltage VR (VD> VR),
The current I1 flowing through the NMOS transistor Q1 is NMOS
It becomes larger than the current I2 flowing through the transistor Q2 (I1> I2). Therefore, the NMOS transistor Q2
, The PMOS transistor Q6 is turned off, and the output of the binary signal output circuit 4 goes to the “L” level. This output is inverted by the inverter 5 and becomes "H".
Therefore, the output of the output terminal 6 becomes "H" level.

On the other hand, when the detection voltage VD of the voltage detection circuit 1 is lower than the reference voltage VR (VD <VR), the NMOS
The current I1 flowing through the transistor Q1 becomes smaller than the current I2 flowing through the NMOS transistor Q2 (I1 <I
2). As a result, the drain voltage of the NMOS transistor Q2 becomes low, so that the PMOS transistor Q6 is turned on, and the output of the binary signal output circuit 4 becomes "H" level.
This output is inverted by the inverter 5 and becomes "L" level, so that the output of the output terminal 6 becomes "L" level.

[0011]

By the way, in the conventional device shown in FIG. 6, as described above, the PMOS transistor Q6 is turned on and its output becomes "H" level, and the output of the output terminal 6 becomes "L" level. It's fast. However, as described above, there is an inconvenience that the PMOS transistor Q6 is turned off and its output becomes "L" level, and the output of the output terminal 6 becomes "H" level generally late.

This inconvenience is because the NMOS transistor Q7 forms a constant current source circuit, and the constant current value cannot be generally increased in order to realize low current consumption. Therefore, it is desired to eliminate the above disadvantages without increasing current consumption.

In view of the above, an object of the present invention is to provide a voltage detecting device which can shorten the output response time without increasing current consumption when a detected voltage such as a power supply voltage decreases and increases. To provide.

[0014]

Means for Solving the Problems In order to solve the above problems and achieve the object of the present invention, each of the inventions according to claims 1 to 5 is configured as follows.

That is, according to the first aspect of the present invention, a differential amplifying means for outputting a signal corresponding to a difference between a detection voltage input to two input terminals and a reference voltage, a transistor and a constant current A binary signal output means for outputting a predetermined binary signal based on the output signal; and generating a predetermined output signal based on a detection result based on a predetermined change in the binary signal. Input signal switching means for inputting the detection voltage and the reference voltage to the two input terminals alternately so that they do not overlap with each other in accordance with the output signal generated by the output signal generation means. And means.

According to a second aspect of the present invention, in the voltage detecting device according to the first aspect, the input switching means selectively inputs the detected voltage to the two input terminals of the differential amplifying means. A first selector, a second selector for selectively inputting the reference voltage to the two input terminals of the differential amplifier, and an output signal generated by the output signal generator. Control means for controlling each selection operation of the first selection means and the second selection means,
It is characterized by consisting of.

According to a third aspect of the present invention, there is provided a differential amplifier which can output two output signals corresponding to a difference between a detection voltage and a reference voltage, a transistor and a constant current circuit for supplying a constant current to the transistor. A binary signal output unit that outputs a predetermined binary signal based on the output signal; and an output signal generation unit that generates a predetermined output signal according to a detection result based on a predetermined change in the binary signal. Output switching means for selectively outputting two output signals from the differential amplifying means to the binary signal output means in accordance with the output signal generated by the output signal generating means. It is a feature.

According to a fourth aspect of the present invention, in the voltage detecting device of the third aspect, the output switching means selectively outputs two output signals of the differential amplifying means to the binary signal output means. It is characterized by comprising selection means for outputting and control means for controlling the selection operation of the selection means.

According to a fifth aspect of the present invention, in the voltage detection device according to any one of the first to fourth aspects, the differential amplifying means comprises a pair of differential pairs forming a differential pair. And a MOS transistor for supplying a constant current to the pair of MOS transistors, and the binary signal output means includes a MOS transistor serving as a load of the differential amplifying means and a constant current for the MOS transistor. And a MOS transistor for supplying a current.

As described above, according to the first, second, or fifth aspect of the present invention, the output signal generation means outputs the detection result based on a predetermined change of the binary signal of the binary signal output means. Such a predetermined output signal is generated. Also, the input switching means may alternately input the detection voltage and the reference voltage to two input terminals of the differential amplifying means according to the output signal generated by the output signal generating means so that the two do not overlap. I made it.

On the other hand, in each of the inventions according to claims 3 to 5, the output signal generating means outputs the predetermined output signal concerning the detection result based on a predetermined change of the binary signal of the binary signal output means. Generated. Further, the output switching means responds to the output signal generated by the output signal generation means,
The output signals from the differential output means are alternately selected and output to the binary signal output means.

Therefore, according to the present invention, the transistor of the binary signal output means can be turned on, for example, from off to on at both the timing when the detected voltage such as the power supply voltage is lower than and higher than the reference voltage, and the timing of the change. Thus, an output signal indicating the result of voltage detection can be generated.

Therefore, according to the present invention, the output response time can be reduced without increasing the constant current of the constant current circuit of the binary signal output means when the detection voltage such as the power supply voltage decreases and increases. Can be faster.

[0024]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a circuit diagram showing an example of the configuration of the first embodiment of the voltage detecting device of the present invention.

As shown in FIG. 1, the voltage detecting device according to the first embodiment includes a voltage detecting circuit 11, a reference voltage generating circuit 12, an input switching circuit 13, a differential amplifier circuit 14, At least a signal output circuit 15, an output signal generation circuit 16, an inverter 17, a latch circuit 18, and a reset circuit 19 are provided.

Here, the differential amplifier means is a differential amplifier circuit 14.
The binary signal output means corresponds to the binary signal output circuit 15, the output signal generation means corresponds to the output signal generation circuit 16 and the like, and the input switching means corresponds to the input switching circuit 13 and the like.

More specifically, the voltage detection circuit 11 comprises:
As shown in FIG. 1, a power supply voltage V of a power supply (not shown) is divided by resistors R11, R12, and R13, and the divided voltage is obtained as a detection voltage VD of the power supply. The resistance R1
An NMOS transistor Q8 for hysteresis is connected between the common connection of the resistor 2 and the resistor R13 and the ground. The output of the flip-flop circuit 24 is supplied to the gate of the NMOS transistor Q8. The reference voltage generation circuit 12 generates a reference voltage VR to be input to the differential amplifier circuit 14.

The input switching circuit 13 includes a voltage detection circuit 1
1 for alternately inputting the detection voltage VD to the NMOS transistors Q1 and Q2 of the differential amplifier circuit 14 and alternately inputting the reference voltage VR of the reference voltage generation circuit 12 to the NMOS transistors Q1 and Q2. is there.

For this purpose, the resistance R1 of the voltage detection circuit 11
1 and the resistor R12 are connected to a NMOS through a switch element 131 such as a transmission gate.
A switching element 132 connected to the gate of the transistor Q1 and including a transmission gate and the like.
Is connected to the gate of the NMOS transistor Q2. Here, the transmission gate is NM
The transmission gate is a combination of an OS transistor and a PMOS transistor.

The reference voltage V of the reference voltage generation circuit 12
R is supplied to the gate of the NMOS transistor Q2 via a switch element 133 such as a transmission gate and to the gate of the NMOS transistor Q1 via a switch element 134 such as a transmission gate.

Further, the switch elements 131 to 134
The on / off control is performed by the control voltage VS from the latch circuit 18. That is, the switch elements 131 and 133 are turned on when the control voltage VS from the latch circuit 18 is at the “H” level, and the switch elements 1 and 133 are turned on.
32 and 134 are turned on when the control voltage VS is at the “L” level.

The structure of the differential amplifier circuit 14 is the same as that of the differential amplifier circuit 3 shown in FIG. 6, so that the same components are denoted by the same reference numerals and description thereof will be omitted. The configuration of the binary signal output circuit 15 is the same as that of the binary signal output circuit 4 shown in FIG. 6, and therefore, the same components are denoted by the same reference numerals and description thereof will be omitted.

The output signal generation circuit 16 includes an AND gate 2
3 and a flip-flop circuit 24, which generates and outputs a predetermined signal as described later according to the output of the binary signal output circuit 15.

That is, the AND gate 23 has one input terminal connected to the drain of the PMOS transistor Q6, a reset signal supplied from the reset circuit 19 to the other input terminal, and an output terminal connected to the flip-flop circuit 24. Is connected to the input terminal C. In the flip-flop circuit 24, the output terminal Q is connected to the input terminal D, and the output signal is fed back to the input. The reset signal from the reset circuit 19 is supplied to the reset terminal R of the flip-flop circuit 24. The output signal of the flip-flop circuit 24 is input to the next-stage inverter 17 and is also supplied to the gate of the NMOS transistor Q8.

The inverter 17 inverts the output signal of the flip-flop circuit 24, outputs the inverted signal to the output terminal 6, and outputs the inverted signal to the inverter 20 and the latch circuit 18.

The latch circuit 18 includes a NAND gate 181,
182 is a crossover as shown in FIG. 1, in which the output signal of the inverter 17 is stored and the storage can be reset by a reset signal from the reset circuit 19.

That is, to the input side of the NAND gate 181, the output of the inverter 17 and the output of the NAND gate 182 are input. Also, NAND Gate 1
The output of 81 is input to the NAND gate 182. Furthermore, a signal obtained by inverting the output of the inverter 17 by the inverter 20 and a reset signal of the reset circuit 19 are input to the input side of the NAND gate 182. The output of the NAND gate 182 is connected to the switch elements 131 to 13 of the input switching circuit 13.
4 is supplied as a control signal for controlling these on and off.

The reset circuit 19 generates a reset signal for resetting the latch circuit 18 and the flip-flop circuit 24. As shown in FIG. 1, a resistor R21 and a capacitor C21 are connected in series between the power supply and the ground. , And a reset signal is taken out from the common connection point.

Next, the flip-flop circuit 2 shown in FIG.
4 will be described in detail with reference to FIG.

As shown in FIG. 2, the input terminal D is connected to one input terminal of a NAND gate 243 via an inverter 241 and a switch element 242 including a transmission gate and the like. In addition, NAND gate 243
Is connected to one of its own input terminals via an inverter 245 and a switch element 244 including a transmission gate and the like. Further, an output terminal of the NAND gate 243 is connected to one input terminal of the NAND gate 248 via a switch element 246 including a transmission gate and the like and an inverter 247.

The output terminal of the NAND gate 248 is
Switch element 2 composed of transmission gate, etc.
49 is connected to a common connection point between the switch element 246 and the inverter 247, and the common connection point is connected to the inverter 2
It is connected to the output terminal Q via 50. The output terminal Q is connected to the input terminal D. Further, the switch elements 242, 244, 246, 249 are connected to the input terminal C.
When the input signal input to the input terminal C is at “H” level, the switch elements 244 and 246 are turned on, and the input signal input to the input terminal C is set to “L”.
At the time of the level, the switch elements 242 and 249 are turned on.

Next, an example of the operation of the first embodiment having such a configuration will be described with reference to FIGS.

In FIG. 3, at time t1, the switch elements 131 and 133 are on because the control voltage VS from the latch circuit 18 is at the "H" level as shown in FIG. Therefore, the detection voltage VD of the voltage detection circuit 11 becomes the input voltage V1 of the MOS transistor Q1, and the reference voltage VR of the reference voltage generation circuit 12 becomes
This becomes the input voltage V2 of the transistor Q2.

Then, at time t1, when the power supply voltage V decreases, the detection voltage VD decreases accordingly.
As shown in (B), the input voltage V1 of the MOS transistor Q1 also decreases. Then, at time t2, the input voltage V1 drops to the reference voltage VR, and continues to drop at time t3, whereupon the output of the differential amplifier circuit 14 (the drain voltage of the MOS transistor Q2) goes to "L" level.
As a result, MOS transistor Q6 turns on, and its output voltage V3 rises from "L" level to "H" level at time t3 as shown in FIG. 3 (D).

Here, the input voltage V1 drops to the reference voltage VR at time t2, and the output voltage V3 of the MOS transistor Q6 immediately rises at time t3 without rising to the "H" level. This is due to a response delay. Therefore, a period T1 from time t2 to time t3 is a response delay of the differential amplifier circuit 14.

As described above, when output voltage V3 of MOS transistor Q6 attains the "H" level at time t3, output voltage V of flip-flop circuit 24 is thereby set.
4 rises from the "L" level to the "H" level as shown in FIG. This output voltage V4 is supplied to the inverter 17
And an output voltage V5 is obtained from the output terminal 6 as shown in FIG. The output voltage V5 is input to and stored in the latch circuit 18, and at the same time, the output of the latch circuit 18 changes from “H” level to “L” level.

As a result, the switching elements 131 and 133 are turned off and the switching elements 132 and 134 are turned on, so that the reference voltage VR of the reference voltage generation circuit 12 becomes the input voltage V1 of the MOS transistor Q1 and the voltage detection circuit The detection voltage VD of 11 becomes the input voltage V2 of the MOS transistor Q2. As a result, since the input voltage of the differential amplifier circuit 14 is switched by the input switching circuit 13, the output of the differential amplifier circuit 14 (the MOS transistor Q2
Drain voltage) goes high, and as shown in FIG. 3D, the output voltage V3 of the MOS transistor Q6 falls from the high level to the low level at time t4. As a result, MOS transistor Q6 is turned off.

Thereafter, as shown in FIG. 3A, since the power supply voltage V is in a state of being reduced until time t5, the voltage of each section does not change. When the power supply voltage V starts increasing at time t5, the detection voltage VD increases accordingly, and the input voltage V2 of the MOS transistor Q2 also increases as shown in FIG. Then, at time t6, the input voltage V2 rises to the reference voltage VR, and further rises at time t7, whereupon the output of the differential amplifier circuit 14 (the drain voltage of the MOS transistor Q2) goes to "L" level. As a result, MOS transistor Q6 is turned on, and its output voltage V3 rises from "L" level to "H" level at time t7 as shown in FIG. 3 (D). Here, the period T1 from the time t6 to the time t7 is the same as that of the differential amplifier 1
4 is a response delay.

As described above, when output voltage V3 of MOS transistor Q6 attains "H" level at time t7,
As a result, the output voltage V4 of the flip-flop circuit 24 falls from the "H" level to the "L" level as shown in FIG. This output voltage V4 is inverted by the inverter 17, and an output voltage V5 as shown in FIG. Therefore, the output voltage V5 from the output terminal 6 becomes a predetermined output signal according to the detection result.

The output voltage V5 of the inverter 17 is input to and stored in the latch circuit 18, and at the same time, the control voltage V3 from the latch circuit 18 changes from "L" level to "H" as shown in FIG. To the level. For this reason,
Since the switch elements 131 and 133 are turned on and the switch elements 132 and 134 are turned off, the voltage detection circuit 11
Is the input voltage V of the MOS transistor Q1.
1 and the reference voltage V of the reference voltage generation circuit 12
R becomes the input voltage V2 of the MOS transistor Q2.

As described above, since the input voltage of the differential amplifier circuit 14 is switched by the input switching circuit 13, the output of the differential amplifier circuit 14 becomes "H" level, and FIG.
As shown in the figure, the output voltage V3 of the MOS transistor Q6
Falls from the "H" level to the "L" level at time t8. As a result, MOS transistor Q6 is turned off.

As described above, in the first embodiment, normally, when the detection voltage VD is input to the transistor Q1, the reference voltage VR is input to the transistor Q2, and the detection voltage VD is lower than the reference voltage VR. , The transistor Q6 is turned on. Thereafter, by switching the switch elements 131 to 134, the transistor Q
1, the input of Q2 is switched to turn off the transistor Q6, and when the detection voltage VD exceeds the reference voltage VR, the transistor Q6 is turned on again.
Further, the output signal generation circuit 16 generates an output signal indicating the result of the voltage detection using the timing at which the transistor Q6 is turned on.

For this reason, according to the first embodiment, the binary signal output circuit 15 is provided at both timings when the detection voltage VD such as the power supply voltage falls below the reference voltage VR and when it rises above the reference voltage VR.
MOS transistor Q6 can be turned on from off. As a result, the constant current supplied by the MOS transistor Q7 of the binary signal output circuit 15 does not increase when the detection voltage such as the power supply voltage decreases and when the detection voltage increases.
Output response time can be shortened.

Next, the configuration of a second embodiment of the voltage detecting device of the present invention will be described with reference to FIG.

In the first embodiment shown in FIG. 1, the input switching circuit 13 is provided on the input side of the differential amplifier circuit 14, and the detection voltage VD input to the two MOS transistors Q1 and Q2 of the differential amplifier circuit 14 and the reference voltage This is to switch between the voltage VR.

However, in the second embodiment, the detection voltage VD and the reference voltage VR input to the two MOS transistors Q1 and Q2 of the differential amplifier circuit 14 are not switched,
Outputs from the transistors Q1 and Q2 are selectively extracted by an output switching circuit 31 as output switching means.

Therefore, in the second embodiment, the input switching circuit 13 of the first embodiment is replaced by an output switching circuit 31, and the other parts are the same as those of the first embodiment. The same components are denoted by the same reference numerals, and the description of the configuration will be omitted. The description will focus on the configurations of the differential amplifier circuit 14 and the output switching circuit 31.

As shown in FIG. 4, the output switching circuit 31 includes MOS transistors Q1 and Q2 of the differential amplifier circuit 14.
In order to selectively output the output from the second stage to the binary signal output circuit 15 at the next stage, switches 311, 313 comprising transmission gates and the like, and switches 312, 314 comprising transmission gates, etc. are provided.

Further, the switch elements 311 to 314
The on / off control is performed by the control voltage VS from the latch circuit 18. That is, switch elements 311 and 313 are turned on when control voltage VS from latch circuit 18 is at “H” level, and switch elements 311 and 313 are turned on.
12 and 314 are turned on when the control voltage VS is at the “L” level.

More specifically, in the differential amplifier circuit 14, the drain of the PMOS transistor Q4 and the PMOS
Switching elements 311, 312 are connected in series between the drain of the transistor Q5. The common connection of the switching elements 311 and 312 is PM
It is connected to both gates of OS transistors Q4 and Q5. Further, the drain of the NMOS transistor Q1 is
NMO is connected to the gate of the PMOS transistor Q6.
The drain of the S transistor Q2 is connected to the gate of the PMOS transistor Q6.

Next, an example of the operation of the second embodiment having such a configuration will be described with reference to FIGS.

In FIG. 5, at time t1, the switch elements 311 and 313 are on because the control voltage VS from the latch circuit 18 is at the "H" level as shown in FIG. Therefore, the gate and the drain of the PMOS transistor Q4 are connected by the switch element 311 and the drain of the PMOS transistor Q2 and the gate of the PMOS transistor Q6 are connected by the switch element 313.

When power supply voltage V decreases at time t1, detection voltage VD decreases accordingly as shown in FIG. 5B, and this detection voltage VD is input to the gate of MOS transistor Q1. . Then, at time t2, the detection voltage VD decreases to the reference voltage VR, and continues to decrease. At time t3, the output of the differential amplifier circuit 14 (the drain voltage of the MOS transistor Q2) goes to the “L” level. As a result, MOS transistor Q6 turns on, and its output voltage V3 rises from "L" level to "H" level at time t3 as shown in FIG. 5 (D). Here, a period T1 from time t2 to time t3 is a response delay of the differential amplifier circuit 14.

As described above, at time t3, when output voltage V3 of MOS transistor Q6 attains the "H" level, output voltage V of flip-flop circuit 24 is thereby set.
4 rises from the "L" level to the "H" level as shown in FIG. This output voltage V4 is supplied to the inverter 17
And an output voltage V5 is obtained from the output terminal 6 as shown in FIG. The output voltage V5 is input to and stored in the latch circuit 18, and at the same time, the output of the latch circuit 18 changes from “H” level to “L” level.

Thus, the switching elements 311 and 313 are turned off, and the switching elements 312 and 314 are turned on. Therefore, the connection between the gate and the drain of the PMOS transistor Q4 is released, and the connection between the drain of the PMOS transistor Q2 and the gate of the PMOS transistor Q6 is also released. At the same time, the gate and drain of the PMOS transistor Q5
At the same time, the drain of the PMOS transistor Q1 and the gate of the PMOS transistor Q6 are connected by the switch element 314.

As described above, since the output of the differential amplifier circuit 14 is switched by the output switching circuit 31, the output of the differential amplifier circuit 14 (the drain voltage of the MOS transistor Q2) becomes "H" level. As a result, the output voltage V3 of the MOS transistor Q6 becomes, as shown in FIG.
At time t4, the voltage falls from the “H” level to the “L” level. As a result, MOS transistor Q6 is turned off.

Thereafter, as shown in FIG. 5A, since the power supply voltage V is in a state of being reduced until time t5, the voltage of each section does not change. At time t5, when the power supply voltage V starts to increase, the detection voltage VD is accordingly increased as shown in FIG.
It rises as shown in (B). Then, at time t6, the detection voltage VD rises to the reference voltage VR, and further continues to rise at time t7, whereupon the output of the differential amplifier circuit 14 (the drain voltage of the MOS transistor Q2) becomes "L" level. As a result, MOS transistor Q6 turns on, and its output voltage V3 rises from the "L" level to the "H" level at time t7, as shown in FIG. 5D. Here, a period T1 from time t6 to time t7 is a response delay of the differential amplifier circuit 14.

As described above, when output voltage V3 of MOS transistor Q6 attains the "H" level at time t7,
As a result, the output voltage V4 of the flip-flop circuit 24 falls from the "H" level to the "L" level as shown in FIG. This output voltage V4 is inverted by the inverter 17, and an output voltage V5 as shown in FIG. Therefore, the output voltage V5 from the output terminal 6 becomes a predetermined output signal according to the detection result.

The output voltage V5 of the inverter 17 is input to and stored in the latch circuit 18, and at the same time, the output voltage V3 of the latch circuit 18 changes from the "L" level to the "H" level as shown in FIG. Changes to For this reason, the switching elements 311, 313 are turned on, and the switching elements 31
2, 314 are turned off, so that the PMOS transistor Q
4 is connected to the gate and drain, and P
The drain of the MOS transistor Q2 and the gate of the PMOS transistor Q6 are connected.

As described above, since the output of the differential amplifier circuit 14 is switched by the output switching circuit 31, the output of the differential amplifier circuit 14 becomes "H" level, and as shown in FIG. Output voltage V3 of transistor Q6 falls from "H" level to "L" level at time t8. As a result, MOS transistor Q6 is turned off.

As described above, in the second embodiment, normally, the output of the transistor Q2 is input to the transistor Q6, and when the detection voltage VD falls below the reference voltage VR, the transistor Q6 is turned on. . Thereafter, the output of the transistor Q1 is input to the transistor Q6 by switching the switch elements 311 to 314, and the transistor Q6 is turned off, so that the detection voltage VD
Is higher than the reference voltage VR, the transistor Q6 is turned on again. Further, the output signal generation circuit 16
Using the timing at which the transistor Q6 is turned on,
An output signal indicating a result of the voltage detection is generated.

For this reason, according to the first embodiment, the binary signal output circuit 15 is provided at both timings when the detection voltage VD such as the power supply voltage falls below the reference voltage VR and when it rises above the reference voltage VR.
MOS transistor Q6 can be turned on from off. As a result, the output response time can be shortened without increasing the constant current supplied by the MOS transistor Q7 of the binary signal output circuit 15 when the detection voltage such as the power supply voltage decreases and when the detection voltage increases (when returning). .

[0074]

As described above, according to the present invention, the transistor of the binary signal output means is turned on, for example, from off to on at both the timing when the detected voltage such as the power supply voltage is lower than the reference voltage and the timing when the detected voltage is higher than the reference voltage. In addition, an output signal indicating the result of voltage detection is generated at the timing of the change.

Therefore, according to the present invention, the response time of the output can be reduced without increasing the constant current of the constant current circuit of the binary signal output means when the detection voltage such as the power supply voltage decreases and increases. Can be faster.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a configuration of a first embodiment of a voltage detection device of the present invention.

FIG. 2 is a circuit diagram showing a detailed configuration of the flip-flop circuit of FIG.

FIG. 3 is a waveform diagram illustrating an example of a signal waveform of each unit according to the first embodiment.

FIG. 4 is a circuit diagram showing a configuration of a second embodiment of the voltage detection device of the present invention.

FIG. 5 is a waveform diagram illustrating an example of a signal waveform of each unit according to the second embodiment.

FIG. 6 is a circuit diagram of a conventional device.

[Explanation of symbols]

 Reference Signs List 11 voltage detection circuit 12 reference voltage generation circuit 13 input switching circuit 14 differential amplifier circuit 15 binary signal output circuit 16 output signal generation circuit 17 inverter 18 latch circuit 19 reset circuit 23 AND gate 24 flip-flop circuit 31 output switching circuit 131-131 134 switch element 311 to 314 switch element

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5H410 BB02 CC02 DD02 EA11 EA12 EB01 FF03 FF22 GG05 LL04 5J055 AX02 AX12 AX55 AX59 BX41 BX42 CX00 DX01 EX21 EX25 EY01 EY03 EY10 EY21 EZ31 EZ12 EZ03 EZ03 EZ03 EZ03 GX01 GX04

Claims (5)

[Claims] A differential amplifier for outputting a signal corresponding to a difference between a detection voltage input to two input terminals and a reference voltage; a transistor; and a constant current circuit for supplying a constant current to the transistor. Binary signal output means for outputting a predetermined binary signal based on an output signal; output signal generation means for generating a predetermined output signal according to a detection result based on a predetermined change in the binary signal; According to the output signal generated by the signal generation means,
Input switching means for alternately inputting the detection voltage and the reference voltage to the two input terminals so that the two do not overlap with each other. 2. The input switching means includes: first selection means for selectively inputting the detection voltage to the two input terminals of the differential amplification means; and inputting the reference voltage to the differential amplification means. A second selecting means for selectively inputting to two input terminals, and an output signal generated by the output signal generating means,
2. The voltage detection device according to claim 1, further comprising: a control unit that controls each selection operation of the first selection unit and the second selection unit. 3. 3. A method according to claim 2, wherein the difference between the detected voltage and the reference voltage is equal to two.
A differential amplifying means capable of outputting two output signals, a binary signal output means comprising a transistor and a constant current circuit for supplying a constant current to the transistor, and outputting a predetermined binary signal based on the output signal; An output signal generating means for generating a predetermined output signal according to the detection result based on a predetermined change in the binary signal; and an output signal generated by the output signal generating means.
Output switching means for selectively outputting two output signals from the differential amplifying means to the binary signal output means. 4. The output switching unit includes: a selection unit that selectively outputs two output signals of the differential amplification unit to the binary signal output unit; and a control unit that controls a selection operation of the selection unit. The voltage detection device according to claim 3, comprising: 5. The differential amplifying means comprises at least a pair of MOS transistors forming a differential pair and a MOS transistor for supplying a constant current to the pair of MOS transistors. 5. The apparatus according to claim 1, wherein said MOS transistor comprises at least a MOS transistor serving as a load of said differential amplifying means and a MOS transistor for supplying a constant current to said MOS transistor. Item 7. The voltage detection device according to item 1.