JP2001337115A - Signal amplitude detection circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To use a large circuit scale. SOLUTION: This signal amplitude detection circuit for detecting the amplitude of signals inputted to a circuit comprising a plurality of amplification circuits arranged in file includes threshold generating means each corresponding to a respective one of the plurality of amplification circuits and each generating M (M is a natural number) threshold, such that the values are within the range of electric potential that can appear at a common point of connection between the pair of input differentials of the corresponding amplification circuit; and a plurality of comparison means each corresponding to a respective one of the plurality of amplification circuits and each outputting the result of comparison between electric potential that can appear at the common point of connection between the pair of input differences of the corresponding amplification circuit and each of the M (M is a natural number) threshold.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal amplitude detecting circuit used for a radio or other receiving apparatus.
Received signal strength indicator (RSSI: Receiver Signal Streng)
th Indicator) can be applied to the detection circuit.

[0002]

2. Description of the Related Art A receiving apparatus has a receiving signal strength index (an index for determining the signal strength of an input signal) in a radio or other receiving apparatus.
Some include a detection circuit for detecting a signal.

Conventionally, as a receiving apparatus provided with this kind of detecting circuit, there is a receiving apparatus having a circuit configuration shown in FIG.
25733).

[0004] This detection circuit comprises an amplifier circuit AMP 200 and an amplitude detection circuit 201. Amplifier circuit AMP2
00 is a cascade connection of N differential amplifier circuits Amp1 to AmpN.

[0005] The amplitude detecting circuit 201 includes a current generating section as a voltage / current converting circuit for converting a voltage detected from each differential amplifier circuit into a current signal, and a current generated by these N current generating sections. A common node (NODE100) as an adding means for obtaining an added total current, a current mirror circuit (P1, P2) for obtaining an output current having the same magnitude as the total current obtained as an addition result, and a bias voltage supplied to each unit. Bias circuit (D1, D2, Q100, R10
0).

More specifically, the current generating units (Ri4, Ri4)
5, Qi4: i = 1, 2,... N) correspond to the differential amplifier circuit Amp.
Potentials appearing at the common emitters P1 to PN of the transistor pair constituting i (i = 1 to N) (input signal amplitude indicating signal)
Is converted into currents IP <b> 1 to IPN of a corresponding magnitude.

The common node (NODE100) has transistors Qi4
The collector terminals (i = 1 to N) are all connected in common to generate a total current IPALL. The current mirror circuit returns the total current IPALL and outputs this as the output current IRSSI.

The reason for adopting the above configuration is that the differential amplifier circuit A
The potentials appearing at the common emitters P1 to PN of the mp1 to AmpN fluctuate up and down in accordance with the strength (amplitude) of the input signals of the differential inputs IN10 and IN11, and the sum of the currents (the output This is because the input signal strength can be detected by determining the current IRSSI.

It should be noted that the differential amplifiers Amp1 to AmpN amplify the input amplitude of each Amp by the gain. However, each Amp has a maximum amplitude that can be output. The potential of the common emitters P1 to PN in the case where the output signal amplitude of the
A phenomenon occurs in which the potential of .about.PN fluctuates up and down in accordance with the input amplitude.

.., Amp3, Amp3 for the signal amplitudes at the input terminals IN10 and IN11.
2. Since the amplitude of each output signal of the differential amplifier can be the maximum amplitude in the order of Amp1 and Amp1, the size of the IRSSI indicates which Amp among the differential amplifiers Amp1 to AmpN has the maximum amplitude output. Can be determined.

Since the output current IRSSI of the amplitude detection circuit indicates the strength (amplitude) of the received signal of the differential amplifier circuit AMP200, it is called the received signal strength indicator (RSSI) signal as described above.

[0012] The RSSI signal is transmitted from the transmitting side to determine the signal strength such as the amplitude of the signal input to the receiving side, and to receive the signal having sufficient signal strength for processing on the receiving side. Is used as a criterion for determining whether to increase or decrease the signal strength of the signal.

Incidentally, as for the IRSSI signal generated in FIG. 2, an RRSSI signal which is an analog value is expressed in a digital form (High level / Low level).
In order to convert the IRSSI signal into an SSI signal, a comparison circuit (not shown) generally compares the signal with a threshold value to determine whether or not the IRSSI signal exceeds the threshold value.

FIG. 3 shows a configuration provided with such a comparison circuit.
4 shows an example of a detection circuit. In the case of the detection circuit of FIG.
Amplification of configuration in which amplifying circuits Amp1 to AmpN are connected in cascade
The circuit AMP300 includes a differential amplifier circuit constituting each of these stages.
Flows to the common connection point of the input differential pairs of the paths Amp1 to AmpN.
Current (input signal amplitude display signal) IRSSI_OUTEach stage
Output current IRSSI_OUT1~ IRSSI_OUTNWhen
And outputs the sum, and uses the sum as the total current IRSSI.
The adder circuit 301 calculates the total current IRSSI.
Functions as a step. Here, the output current IRSSI
_OUT1~ IRSSI _OUTNIs the common emitter of FIG.
Correspond to the current components of the potentials P1 to PN.

In this detection circuit, a comparison circuit 301C compares the total current IRSSI or a signal output VRSSI obtained by converting the current value into a voltage with a threshold value. Output RSSI. This RSSI signal is used as a determination result of the received signal strength viewed from the whole of the amplifier circuit AMP300. With this, RSSI
The signal is digitally represented as a high level or a low level.

The threshold value here is, as shown in FIG. 4A, the differential input pair IN0 of the amplifier circuit AMP300.
And the signal amplitude of IN1 is the maximum amplitude (for example, the power supply potential V
IRSSI level (or VRSSI level) in the case of the same magnitude as the DD, that is, IRSSI
_max (or VRSSI _max ) and the differential input pair IN0
And the IRS when the signal amplitude of IN1 is the minimum amplitude
SI level (or VRSSI level), ie, IRS
SI _min (or VRSSI _min ).

However, as shown in FIG. 4B, the threshold value is set at every interval A from the IRSSI level (or VRSSI level) when the signal amplitude is the minimum amplitude, that is, from IRSSI _min (or VRSSI _min ). Setting is also common.

[0018]

However, in the case of the conventional circuit, the potential of the common emitter of the differential pair in each differential amplifier circuit constituting the amplifier circuit is converted into a current, and then the sum of the currents is calculated by the adder circuit. , And then the total sum of the currents is further converted to a voltage and compared with a threshold value, so that the RSSI signal of the digital signal cannot be detected.

That is, in the case of the conventional circuit, a circuit such as a voltage / current conversion circuit, an addition circuit, and a current / voltage conversion circuit is required until an RSSI signal of a digital signal is obtained, and the circuit scale cannot be increased. There was a problem of not getting.

[0020]

Means for Solving the Problems (A) In order to solve such problems, a first means having the following configuration is proposed. In a signal amplitude detection circuit that detects the amplitude of a signal input to a circuit having a configuration in which a plurality of stages of amplifier circuits are arranged in tandem, (1) each corresponds to the above-described plurality of stages of amplifier circuits, and each of them corresponds to Threshold generation means for generating M (M is a natural number) thresholds so as to be included in the range of potentials that can appear at the common connection point of the input differential pair of the amplifier circuit, Individual comparison results of the potential appearing at the common connection point in the input differential pair of the corresponding amplifier circuit corresponding to the plurality of stages of amplifier circuits and the M thresholds (M is a natural number) And a plurality of comparison means for outputting the same.

In the first means, for each of the plurality of amplifying circuits, the magnitude of the signal amplitude inputted to each input differential pair is individually compared by comparing a potential appearing at the common connection point with a threshold value. Ask for. For example, if the input amplitude is large, the potential appearing at the common connection point of the input differential pair becomes high, while if the input amplitude is small, the potential appearing at the common connection point of the input differential pair becomes low. Therefore, if the magnitude relationship between the potential and the threshold value appearing at the common connection point in the input differential pair of each amplifier circuit is given to the subsequent processing circuit, the signal input to the circuit having a configuration in which a plurality of amplifier circuits are arranged in cascade is provided. Can be estimated in what state the amplitude is.

Incidentally, in the signal amplitude detection circuit of this configuration, the potential appearing at the common connection point of the input differential pair of each amplifier circuit is directly compared with the threshold value. The current addition circuit and the current / voltage conversion circuit are unnecessary, and the number of circuit elements can be reduced accordingly.

Further, since the threshold value generating means can generate M (M is a natural number) threshold values, it can be used to increase the amplification of the corresponding amplifier circuit and determine the amplitude of the input signal. If a plurality of thresholds are set, the number of stages of the amplifier circuits constituting the circuit can be reduced, and the circuit scale can be reduced accordingly.

Further, since the output of the signal amplitude detection circuit is a digital output (because it is a set of comparison results of the comparison means), the analog / digital conversion circuit is again used when the output is digitally processed by a subsequent circuit. Is not necessary, and the circuit scale can be small.

(B) In order to solve this problem, a second means having the following configuration is proposed. First
It is proposed that M thresholds (M is a natural number) generated by the threshold generator in the above means are given at logarithmically equal intervals with respect to a reference potential corresponding to the corresponding amplifier circuit.

As described above, by giving the threshold values logarithmically at equal intervals, it is possible to make a decision reflecting the amplification characteristics of each amplifier circuit more.

(C) In order to solve this problem, a third means having the following configuration is proposed. First
Alternatively, in the signal amplitude detection circuit according to the second means, it is proposed that the circuit having a configuration in which the plurality of stages of amplifier circuits are arranged in cascade is a circuit in which a filter circuit and an amplifier circuit are arranged in cascade.

Like the third means, the first or second means can be applied to a circuit having a filter circuit in addition to the amplifier circuit.

(D) In order to solve this problem, a fourth means having the following configuration is proposed. In the signal amplitude detection circuit of the first, second or third means, the plurality of comparison outputs outputted from the plurality of comparison means are converted into serial signals and identified at the beginning and / or end of the signal sequence. There is proposed a device further provided with a parallel / serial conversion means for adding and outputting a signal.

By converting the comparison results obtained by the plurality of comparison means into a serial signal as in the fourth means,
The number of wires required for connection to the subsequent circuit can be reduced, that is, the number of wires can be reduced to one.

Further, by adding an identification code to the beginning and / or end of a series of signal sequences, it is possible to reliably extract the series of signal sequences. In addition, asynchronous transfer to a subsequent circuit can be realized.

[0032]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a signal amplitude detection circuit according to the present invention will be described below. Note that the detection circuit is
The present invention is applicable regardless of whether the transmission path of the received signal is wireless or not (that is, applicable to the case of a wired path). It is suitable for application to a wireless communication device of a system (closed loop control type) that performs control based on sensitivity. Needless to say, the application is not limited to this, and the present invention can be applied to a case where it is used for other control on the transmitting device side and a case where it is used for control in the receiving device.

(A) First Embodiment (A-1) Configuration of Signal Amplitude Detection Circuit (1) Overall Configuration FIG. 1 shows a functional block configuration of a signal amplitude detection circuit according to a first embodiment. As shown in FIG. 1, the signal amplitude detection circuit includes an amplification circuit AMP100 including N differential amplification circuits Amp1 to AmpN, and a comparison circuit unit CMP1.
00.

The detailed configuration of the amplifier circuit AMP100 will be described later.
Voltages VRSSI _{OUT1 to} VRSSI _OUTN appearing at a common node of each differential amplifier circuit constituting MP100;
A configuration is adopted in which comparisons with the corresponding thresholds are individually executed.

On the other hand, the comparison circuit section CMP100 has N comparison sections Cmp1 to CmpN corresponding to the respective differential amplifier circuits constituting the amplifier circuit AMP100. Each comparison unit is provided with one threshold value generation unit and one comparison circuit.

The threshold generator generates M (M is a natural number, two in FIG. 1) thresholds. Incidentally, the threshold value is set between the maximum amplitude and the minimum amplitude that the corresponding differential amplifier circuit can take. A method for setting the threshold will be described later.

The comparison circuit compares the corresponding input signal amplitude indication signal VRSSI _OUT with the threshold value generated by the threshold value generation unit, and outputs a magnitude relationship between each threshold value and the input signal. is there.

(2) Configuration of Amplifier Circuit FIG. 5 shows a configuration example of the amplifier circuit AMP100. As shown in FIG. 5, the amplifier circuit AMP100 is formed by cascade connection of N differential amplifier circuits Amp1 to AmpN. Each of the differential amplifier circuits Amp1 to AmpN includes transistors Qi1 and Qi2 (i = 1 to N) forming a transistor pair,
It consists of load resistors Ri1 and Ri2 (i = 1 to N), a transistor Qi3 (i = 1 to N) and a resistor Ri3 (i = 1 to N) constituting a constant current source.

The input signal amplitude indicating signal V of each differential amplifier circuit
As the RSSI _OUTi (i = 1 to N), the common connection point (common emitter section in FIG. 5) P of the differential pair of each differential amplifier circuit
The potential appearing at i (i = 1 to N) is output.

(A-2) Signal strength detection operation The signal amplitude detection circuit having such a configuration performs the following detection operation.

(1) Basic Operation For the sake of explanation, each of the differential amplifier circuits Amp1 to Amp
Each of N is α [dB] (= 10 ^{(α / 20)} times)
It has a degree of amplification of

When the amplitude of each input signal of the differential inputs IN0 and IN1 (the difference between the differential inputs IN0 and IN1) is H [V], the amplifier circuit AMP100 amplifies the input amplitude by the number of stages (that is, α × N [dB]) and the amplitude is H × 1
0 ^{(αN / 20)} [V] signal is output.

At this time, each of the differential amplifier circuits Amp1 to Am
From each of the pNs, a potential appearing at the common connection point (common emitter portion in FIG. 5) of the input differential pair of each Amp that fluctuates according to the input signal amplitude of each Amp is output as an input signal amplitude display signal.

These input signal amplitude indicating signals are input to the comparing circuits 1 to N of the corresponding comparing sections Cmp1 to CmpN, respectively.

In the threshold value generating units 1 to N, as shown in FIG.
_The threshold value is determined based on the maximum amplitude and the minimum amplitude of each of the differential amplifier circuits Amp1 to AmpN that output _OUT . Here, it is set between VRSSI _OUTmax when the corresponding differential amplifier circuit has the maximum amplitude and VRSSI _OUTmin when the corresponding RSSI _OUT has the minimum amplitude.

Thus, the differential amplifier circuits Amp1 to Amp
N is output to the comparison unit Cm in the comparison circuit unit CMP100.
In p1 to CmpN, each threshold value is compared, and the comparison result is output as an RSSI signal.

(2) Setting of Threshold As described above, VRSS output from each differential amplifier circuit
Since I _OUT is a potential appearing at the common emitter portion of the input differential pair, it has a waveform obtained by full-wave rectification of the balanced input signal as shown in FIG. Therefore, half of the maximum output amplitude of the used amplifier circuit is the maximum amplitude of the VRSSI _OUT .

Now, the maximum potential at the maximum amplitude of the RSSI _OUT is represented by VRSSI _OUTmax , and the minimum potential is represented by VRSSI OUT.
_OUTmin, and the amplitude at that time (VRSSI
_OUTmax- VRSSI _OUTmin )
_amp , the RSSI detection resolution of the applied system is B [d
B], it is desirable to set the threshold value as follows.

In the following description, threshold 1 is defined as the smaller value of the thresholds generated by each threshold generator, and threshold 2 is defined as the larger value. Shall be referred to. At this time, thresholds 1 and 2 are determined as follows.

Threshold value 1 = VRSSI _OUTmin + VRSSI
_amp × 10 ^{(−B / 20)} [V] threshold value 2 = threshold value 1+ (VRSSI _OUTmax −threshold value 1) × 10 ^{(−B / 20 )} [V] Further, amplification of the differential amplifier circuit If the degree α is given by α = 2 × B, as shown in FIG. 8, the signal intensity can be detected at the input terminal of the amplifier in B [dB] steps. FIG.
In the case of, the VRSSIO of the fourth and fifth stage differential amplifier circuits
The UT has the maximum amplitude, and the VRSSI of the third stage amplifier circuit
_OUT is detected between threshold 1 and threshold 2.

An example of the operation of the comparison units Cmp1 to CmpN will be described with reference to FIG. FIG. 9 shows a differential amplifier circuit Am
The differential amplifier circuit A located at the fifth stage among p1 to AmpN
mp5 input signal amplitude display signal VRSSI _OUT5 ;
Threshold 5 generated by threshold generator 5 corresponding to this
1 and 52 are given.

In the case of FIG. 9, the input signal amplitude indicating signal VRSSI _{OUT 5} of the differential amplifier circuit Amp5 is
VRSSI _OUT5max side (upper), and
It is on the VRSSI _OUT 5 _min side (below) from the threshold value 52.

Here, the comparison circuit constituting each of the ratios Cmp1 to CmpN _determines that the RSSI _OUT5 is higher than the threshold value (V
In the case of the RSSI _OUTmax side, a high-level comparison result RSSI signal is output, and is output below the threshold (VRS
_Assuming that a low-level comparison result RSSI signal is output in the case of SI _OUTmin side), the comparison circuit 5
The result of comparing the threshold value 51 is Hig as the RSSI 51 signal.
h level is output, and the comparison result of the threshold 52 is RSSI5
A low level is output as two signals.

(A-3) Effects of the First Embodiment As described above, according to the first embodiment, the voltage / current conversion circuit, the addition circuit, and the current / voltage conversion circuit as in the conventional device are used. Since the signal amplitude can be detected without the need, the number of circuit elements can be significantly reduced. This effect can be obtained even when the number of thresholds generated by the threshold generator is one.

Further, the amplification degree of each stage (differential amplifier circuit) constituting the amplifier circuit is increased, and the number of thresholds generated by the threshold generator in the corresponding comparison circuit section is increased. In the above-described embodiment, the number is two, but if the number is three or more), the number of stages of the entire amplifier circuit can be reduced, and the circuit size can be further reduced.

Further, according to the signal amplitude detection circuit of this embodiment, the RSSI signal output from the comparison circuit unit 100 is a binary signal itself. There is no need to prepare a converter.

(B) Second Embodiment Next, a second embodiment, which is an extended configuration example of the first embodiment, will be described.

(B-1) Configuration of Signal Amplitude Detection Circuit FIG. 10 shows a functional block configuration of a signal amplitude detection circuit according to the second embodiment. The difference from the first embodiment is that a 2 × N RSSI signal output in parallel from the signal amplitude detection circuit described in the first embodiment is converted to a serial output (serial / serial). This is the point that a serial conversion and a header / footer addition circuit) are newly provided.

Here, the parallel / serial conversion and header / footer addition circuit has two functional units. 1
One is a parallel / serial conversion function unit that inputs a plurality of RSSI signals and converts them into a serial signal. One is
The header / footer signal addition function unit adds a header signal to the head of the RSSI signal and adds a footer signal to the tail of the RSSI signal when outputting the serial signal.

(B-2) Processing Operation Since the operation of the circuit portion described in the first embodiment has already been described, only the operation unique to this embodiment will be described here.

The parallel / serial conversion function unit is 2 × N
RSSI signals (RSSI11, RSSI12,... R
SSIN1, RSSIN2) at a timing synchronized with the parallel side clock, for example, the threshold value becomes higher in the stage corresponding to the preceding stage of the differential amplifier circuit constituting the amplifier circuit, and between those corresponding to the same differential amplifier circuit. The arrangement of signals is converted so that the larger the signal, the closer to the head. In the case of this embodiment, the serial signal is converted with the RSSI 11 at the top.

For example, when the signal levels of 2 × N RSSI signals are as follows, RSSI11 = 0 (Low level), RSSI12 = 0 (Low level), RSSI2
1 = 0 (Low level), RSSI22 = 1 (High)
Level), RSSI31 = 1 (High level), RS
SI32 = 1 (High level) ..., RSSIN1 = 1
(High level), RSSIN2 = 1 (High level), and the parallel / serial conversion function unit reads “00011
1 ... 11 "are output in an order synchronized with the serial clock.

At this time, the header / footer signal addition function unit adds the header signal to the head of the serial signal output and adds the footer signal to the end of the serial signal when outputting the serial signal.

For example, if the header signal is “0101” and the footer signal is “1111”, the RSSI signal output is converted to “01010011111... 111111” and output.

Here, the header signal and the footer signal are represented by R
When the reference signal is used to identify the SSI signal (the signal sandwiched between the header signal and the footer signal is recognized as an RSSI signal), 01 corresponding to the header signal is included in the serial signal.
01, then there is a fixed number of signals (R
(The number of signals of SSI11 to RSSIN2), and finally, 1111 corresponding to the footer signal is detected.
11 is the content of the RSSI signal (RSSI 11 to RSSI 11).
RSSIN2).

In this case, the detection of the RSSI signal is triggered by the detection of the header / footer signal.
An RSSI signal can be asynchronously transmitted to a circuit that receives the signal.

(B-3) Effects of the Second Embodiment As described above, according to the second embodiment, the following effects can be obtained in addition to the effects of the first embodiment.

That is, in this embodiment, a plurality of RSS
In order to adopt a configuration in which an I signal is converted into a serial signal and transmitted, the number of connection lines with a circuit that receives an RSSI signal is reduced as compared with the first embodiment (the number of RSSI signal lines is one).
can do.

Also, when outputting this serial signal, the present embodiment employs a form in which a header / footer signal is added to the head and tail of each RSSI output unit and transmitted, so that the RSSI signal is output. Can be transmitted asynchronously to the circuit that receives the.

(C) Third Embodiment Next, a description will be given of another embodiment in which the signal amplitude detection circuits according to the first and second embodiments are provided in a part of the circuit configuration.

(C-1) Configuration of Signal Amplitude Detection Circuit (1) Overall Configuration FIG. 11 shows a functional block configuration of a signal amplitude detection circuit according to the third embodiment. In the third embodiment, when a filter circuit with an amplifying function is arranged before the amplifier circuit (constituted by N stages of differential amplifier circuits) described in the first embodiment, This enables detection of the signal amplitude intensity in each of the amplification stage of the filter circuit and the amplification stage of the subsequent amplification circuit.

That is, the signal amplitude detection circuit according to this embodiment comprises a filter circuit F200 and a comparison circuit unit CMP2 for detecting the signal amplitude of the amplifier circuit of each stage constituting the filter circuit F200.
00 and the circuit configuration described in the first embodiment (FIG. 1)
And a parallel / serial conversion and header / footer addition circuit PS2 for integrating each of the detection output of the amplifier circuit and the detection output of the filter circuit into a serial signal.
00.

(2) Configuration of Filter Circuit In FIG. 11, it is assumed that a filter circuit having an amplification function has the following configuration. Of course, this configuration is an example, and it is not necessary for all filter circuits with an amplification function to adopt such a configuration.

Here, it is assumed that the filter circuit is constituted by cascade connection of N stages of filters 1 to N for passing a signal of a predetermined band, and a differential amplifier circuit Amp 1 to 1 having a gain α [dB] is provided between the filters. It is assumed that one AmpN-1 is arranged.

The configuration of each of the differential amplifier circuits Amp1 to AmpN-1 is the same as the configuration of FIG. 5 described in the first embodiment. That is, these N-1 stages of differential amplifiers Amp
From 1~AmpN-1, the potential appearing at the common connection point of the differential pair, the input signal amplitude indicating signal _{VRSSI OUTi} (i
= 1 to N-1).

(3) Configuration of the Comparison Circuit Unit The configuration of the comparison circuit unit CMP200 is the same as the configuration of the comparison circuit unit CMP100 of the first embodiment. However, in this case, since the output of the N-1 stage differential amplifier circuit constituting the filter circuit is to be detected, the number of the comparison units Cmp is N-1 corresponding to the differential amplifier circuit.

Each comparison section is provided with one threshold generation section and one comparison circuit, and the number of threshold generation sections is M (M
Is a natural number, two in the case of FIG. 11, and the comparison circuit outputs the magnitude relationship between each threshold value and the input signal in the same manner as in the first embodiment.

(4) Configuration of parallel / serial conversion and header / footer addition circuit Even in this parallel / serial conversion / header / footer addition circuit PS200, the parallel / serial conversion function unit and the header / footer signal addition function unit are provided. The point that two functional units are provided is the same as in the first embodiment.

The difference is that the number of parallel signal input lines is 2 ×
There are many points of (N-1) + 2 × N lines, and a point that an input parallel signal is a detection result of two different circuits.

The addition of the header and the footer by the header / footer signal addition function unit is performed by detecting the signal amplitude obtained from the filter circuit with the amplification function and the signal obtained from the amplification circuit (the configuration of the first embodiment). It may be added separately to the amplitude detection result (two sets of headers and footers are added), and one set of header and footer is added to two types of detection results. May be.

(C-2) Processing Operation Here, it is assumed that the filter circuit F200 has a gain (α × (N−1)) [dB] as a whole.
That is, each of the differential amplifier circuits Amp1 to AmpN-1
It has an amplification degree of α [dB] (= 10 ^{(α (N−1) / 20)} times). It is assumed that each filter stage of the filter circuit F200 has bandpass characteristics and the like.
Incidentally, it is not always necessary to unify all filter stages with the same characteristics.

In this case, the comparison circuit unit CMP200 prepared for the filter circuit corresponds to the common connection point potential of the input differential pair given from each of the differential amplifier circuits Amp1 to AmpN-1 constituting the filter circuit. And compares them with the respective thresholds.

The method of setting the threshold value is the same as that of the first embodiment. The difference between VRSSI _{max at} the maximum amplitude of each differential amplifier circuit Amp1 to AmpN-1 and VRSSI _min at the minimum amplitude is obtained. Is set at intervals of B [dB] from VRSSI _OUTmin .

Accordingly, an RSSI signal output for each of the differential amplifier circuits constituting the filter circuit F200 having an amplification function can be obtained from the comparison circuit section CMP200.

Then, the 2 × (N-1) RSSs
IF output and 2 × N RSs from the circuit of the first embodiment.
The SIF output is converted into a serial signal together with a header and a footer, and output from the parallel / serial conversion and header / footer adding circuit PS200.

(C-3) Effect of Third Embodiment As described above, according to the third embodiment, even when a plurality of (two in this case) amplification circuit groups to be detected exist. Thus, it is possible to realize a signal amplitude detection circuit having a small number of elements and a small circuit scale.

Further, the circuit arrangement (including the design and layout) can be given a degree of freedom.

(D) Other Embodiments In the above-described first to third embodiments, two threshold values are given to each comparison circuit. However, the input signal amplitude of the corresponding amplifier circuit is the maximum amplitude. Output VRS when adopting
The threshold value is set to a decibel [d] between the SI level and the output VRSSI level when the input signal amplitude takes the minimum amplitude.
B] Any number of thresholds may be set as long as they are set at equal intervals in units (ie, logarithmically).

In the above embodiment, the case where the threshold value is set with reference to the minimum potential appearing at the common connection point of the input differential pair has been described, but the threshold value may be set with reference to the maximum potential. Further, a value obtained by giving a predetermined offset potential to the minimum potential or the maximum potential may be used as a reference potential, and the threshold may be set logarithmically at equal intervals from the reference potential.

Further, even if the order of the threshold signals in the above-described embodiment is changed or encoded, the present invention can be applied similarly to the embodiment.

In the first to third embodiments, the configuration of the amplifier circuit has been described using a bipolar transistor. However, when an amplifier circuit having another structure, for example, a transistor element having another structure such as CMOS or MES is used. Is similarly applicable.

In the first and second embodiments, the detection target of the signal amplitude is described as an amplifier circuit composed of N differential amplifier circuits. However, the amplification function as described in the third embodiment is used. The present invention can also be applied to a case where a filter circuit with a mark is targeted.

In the second and third embodiments, RS
Although it has been described that both the header signal and the footer signal are added to the SI signal output, the same effect can be obtained by adding only one of them.

In the third embodiment, an example in which the amplification factor is secured by inserting an amplification circuit between filters arranged in tandem has been described. However, the transconductance (L)
A similar effect can be obtained when the amplification factor is secured by impedance conversion inside a filter composed of a capacitor and a capacitor (C).

In the third embodiment, the case where the filter circuit with the amplifying function is located at the preceding stage and the amplifying circuit according to the first embodiment is located at the subsequent stage has been described. The reverse is also acceptable.

[0096]

(A) As described above, according to the first aspect of the present invention, signal amplitude detection for detecting the amplitude of a signal input to a circuit having a configuration in which a plurality of stages of amplifier circuits are arranged in cascade. M circuits (M is a natural number) such that each of the circuits corresponds to the plurality of stages of amplifier circuits, and each of the circuits includes a range of potentials that can appear at a common connection point in the input differential pair of the corresponding amplifier circuit. ), Each of which corresponds to the plurality of stages of amplifier circuits,
Each of the plurality of comparing means for outputting the individual comparison result between the potential appearing at the common connection point in the input differential pair of the corresponding amplifier circuit and the M thresholds (M is a natural number). With such a configuration, a voltage / current conversion circuit, a current addition circuit, and a current / voltage conversion circuit as in a conventional circuit can be omitted, and the number of circuit elements can be reduced accordingly.

Further, since the threshold value generating means can generate M (M is a natural number) threshold values, it can be used to increase the amplification of the corresponding amplifier circuit and determine the amplitude of the input signal. If a plurality of thresholds are set, the number of stages of the amplifier circuits constituting the circuit can be reduced, and the circuit scale can be reduced accordingly.

Further, since the output of the signal amplitude detection circuit is a digital output (because it is a set of comparison results of the comparison means), the analog / digital conversion circuit is used again when the output is digitally processed by a subsequent circuit. Need not be provided, and the circuit scale can be reduced.

(B) As described above, according to the second aspect of the present invention, M thresholds (M is a natural number) generated by the threshold value generating means in the first aspect of the present invention are: By giving logarithmically at equal intervals to a reference potential corresponding to the corresponding amplifier circuit, it is possible to make a determination that more reflects the amplification characteristics of each amplifier circuit.

(C) As described above, according to the third aspect of the present invention, in the signal amplitude detecting circuit according to the first or second aspect, a circuit having a configuration in which the plurality of stages of amplifier circuits are arranged in cascade. Is a circuit having a configuration in which a filter circuit and an amplifier circuit are arranged in tandem, so that the invention described in claim 1 or 2 can be applied to a circuit having a filter circuit in addition to the amplifier circuit.

(D) According to the fourth aspect of the present invention, in the signal amplitude detecting circuit according to the first, second or third aspect of the present invention, a plurality of signals output from the plurality of comparing means are output. A parallel / serial conversion means for converting the comparison outputs into serial signals and adding an identification signal to the beginning and / or end of the signal sequence and outputting the signals, thereby providing wiring necessary for connection to a subsequent circuit The number can be reduced.

Further, by adding an identification code to the beginning and / or end of a series of signal sequences, it is possible to reliably extract the series of signal sequences. In addition, asynchronous transfer to a subsequent circuit can be realized.

[Brief description of the drawings]

FIG. 1 is a functional block diagram illustrating a first embodiment.

FIG. 2 is a diagram showing a conventional configuration example (part 1).

FIG. 3 is a diagram showing an example of a conventional configuration (part 2).

FIG. 4 is a diagram showing a conventional threshold value setting method.

FIG. 5 is a diagram illustrating a configuration of an amplifier circuit.

FIG. 6 is a diagram illustrating a threshold setting method in the embodiment.

FIG. 7 is a diagram showing a relationship between a balanced input and an output potential appearing at a common emitter.

FIG. 8 is a diagram showing a relationship between an output potential appearing at a common emitter and an entire threshold.

FIG. 9 is a diagram showing a relationship between an output potential appearing at a common emitter and individual threshold values.

FIG. 10 is a functional block diagram showing a second embodiment.

FIG. 11 is a functional block diagram showing a third embodiment.

[Explanation of symbols]

AMP100, AMP200, AMP300 ... amplifier circuit, 201 ... amplitude detection circuit, CMP, CMP100, C
MP200: comparison circuit section, F200: filter circuit, P
S200: Parallel / serial conversion and header / footer addition circuit

Claims (4)

[Claims] 1. A signal amplitude detection circuit for detecting the amplitude of a signal input to a circuit having a configuration in which a plurality of stages of amplifier circuits are arranged in tandem, each of which corresponds to the plurality of stages of amplifier circuits. Threshold generation means for generating M (M is a natural number) thresholds so that the thresholds fall within the range of potentials that can appear at the common connection point of the input differential pair of the corresponding amplifier circuit. The individual comparison results of the potential appearing at the common connection point in the input differential pair of the corresponding amplifier circuit corresponding to a plurality of stages of amplifier circuits and the M thresholds (M is a natural number) A signal amplitude detection circuit comprising: a plurality of comparing means for outputting. 2. The signal amplitude detection circuit according to claim 1, wherein said M threshold values (M is a natural number) generated by said threshold value generation means are set with respect to a reference potential corresponding to a corresponding amplifier circuit. A signal amplitude detection circuit characterized by being given logarithmically at equal intervals. 3. The signal amplitude detection circuit according to claim 1, wherein the circuit in which the plurality of stages of amplifier circuits are arranged in cascade is a circuit in which filter circuits and amplifier circuits are arranged in cascade. A signal amplitude detection circuit. 4. The signal amplitude detection circuit according to claim 1, wherein a plurality of comparison outputs output from the plurality of comparison means are converted into a serial signal, and a serial signal is output. Alternatively, a signal amplitude detection circuit further comprising a parallel / serial converter for adding an identification signal to the end and outputting the signal.