JP2001334009A - Time counting system for contest - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a system which enables transmission of more time counting signals to another one or a plurality of other points after the inputting thereof from an arbitrary point with only one cable. SOLUTION: A synchronous signal generation circuit is connected to one bus line, further, a plurality of input/output circuits are connected thereto and a time counting device for contest is connected to the input/output circuits. The input/output circuits are so arranged as to allow receiving of outputs from any other ones thereof. Synchronous signals to be outputted from the synchronous signal generation circuit are confined to two types and a signal requiring a higher time resolving power is transmitted by the synchronous signal with a fast cycle while a signal requiring no higher time resolving power done by the synchronous signal with a slow cycle thereby enabling transmission of more signals within one cycle.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a timekeeping system for athletics and other various sports.

[0002]

2. Description of the Related Art Conventionally, in a timekeeping system, signals such as start and finish are generally transmitted by laying cables individually. Japanese Patent Publication No. Sho 61-8957 is known as a touch panel system for a swim timer. This system uses one shielded cable as an address bus line to send echo pulses from the printing pulse, which is the timing pulse generator, to the touch board through the address bus line, and from the touch board to the touch board through the address bus line. An echo pulse is generated by giving a delay time according to the course to the plate.

[0003]

In the conventional method of separately laying cables, the number of cables increases in proportion to the equipment used. Furthermore, since the distance between the devices is several hundred meters, and sometimes the pipes pass underground, laying requires a lot of labor and cost. Further, in the touch panel system of the swimming time keeping device disclosed in Japanese Patent Publication No. 61-8957, the echo pulse is sent to a printing timer which is a timing pulse generator, so that the propagation delay time of the timing pulse and the propagation delay of the echo pulse. There is a problem that a signal can be sent from only one place during the round trip delay time, and the information that can be transmitted is limited to tens of bits when the timing pulse is set to 0.1 mS at 300 m. there were.

[0004]

In order to solve the above-mentioned problems, the present invention connects a synchronous signal generating circuit to one bus line, and further connects a plurality of input / output circuits to the bus line. A competition timing device was connected to the circuit. The input / output circuit can receive any output of other input / output circuits, and outputs a plurality of pieces of information continuously to the bus line. The synchronization signal output from the synchronization signal generation circuit has two types with different periods, and a signal requiring high time resolution is transmitted by a synchronization signal having a fast period, and a signal not requiring high time resolution is transmitted by a synchronization signal having a slow period. .

[0005]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The competition timekeeping system of the present invention has a configuration in which a synchronization signal generating circuit and a plurality of input / output circuits are connected to one bus line, and a timekeeping device is connected to the input / output circuit. The input / output circuit can be built in the clocking device. The power supply for the input / output circuit can be obtained from wiring provided integrally with the bus line, or can be obtained from a DC voltage superimposed on the bus line. The timing device can be adapted to various competitions by connecting a device according to the type of competition.

For a serial signal such as RS-232, a synchronous conversion circuit is built in the input / output circuit, and the received RS-232 data is output in synchronization with the bus line. Alternatively, data received from the bus line can be converted to RS-232 and transmitted. Input / output circuit is AD conversion circuit, DA
A built-in conversion circuit continuously converts the audio signal by the income and outputs the audio data to the bus line. Further, since one or more of the plurality of audio data on the bus line are continuously received, D / A converted, and output, a plurality of audio data on the bus line can be selected and heard.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings. In FIG. 1, 1 is a bus line, 2, 3, and 4 are input / output circuits connected to the bus line, 5 is a synchronization signal generation circuit connected to the bus line, 6 is a start signal generation means for the input / output circuit 2, Reference numeral 7 denotes a light emitter, and 8 denotes a light receiver for the light emitter 7, which is connected to the input / output circuit 3. 9 is a timing means connected to the input / output circuit 3, and 10 is an indicator light connected to the input / output circuit 2. Reference numeral 11 denotes an indicator light setting device for controlling the indicator lamp 10, which is connected to the input / output circuit 4. Reference numeral 12 denotes a display panel having a built-in input / output circuit, which is connected to the bus line 1.

With such a configuration, the indicator lamp 10 displays blue when the start is possible, and displays red when the start is not possible. When the timer 9 can measure time, the display setting device 11 is operated to turn the indicator light blue. In the case of an athletics, for example, a player starts with a start signal, and then passes between the light emitter 7 and the light receiver 8 provided on the finish line. The start signal is sent to the input / output circuit 2 and output to the bus line 1. The input / output circuit 4 receives the start signal and outputs it to the timing means 9. The light receiver 8 detects the passage of a player, that is, a goal, by blocking the light of the light projector 7, and outputs the signal to the bus line 1 via the input / output circuit 3 as a goal signal. The input / output circuit 4 receives the goal signal and outputs the signal to the timer 9. The timer 9 starts the timer with the start signal output from the input / output circuit 4, and records the timer information when the goal signal output from the input / output circuit 4 is input to measure the time of the player. The timer 9 outputs the recorded player's time information to the input / output circuit 4, and the input / output circuit 4 outputs the time information to the bus line 1. A display panel 12 having a built-in input / output circuit receives and displays the time information on the bus line 1.

FIG. 2 is an explanatory diagram showing the operation of the bus line 1. The synchronization signal S1 is output from the synchronization signal generation circuit 5 to the bus line 1. The synchronization signal S2 is output to the bus line 1 at a cycle faster than the synchronization signal S1. T1 is the synchronization signal S
T1 is the period of the synchronization signal S2. U1 to Un are data output sections output from the input / output circuits to the bus lines, respectively.

FIG. 3 is an explanatory diagram showing the operation of the bus line 1. Data a, data b,. . . The data m is a data array output for each of the data output sections U1 to Un. Data a is a sequence of data bits a1, a2, a3, a4
And the data b includes data bits b1, b2, b3, b
4 and data m includes data bits m1, m2, m3,
m4. In the embodiment, T1 = 1 mS, T2 =
0.1 mS. Further, n was set to 10 and m was set to 8. With such a data array, data a, data b,. . . Data m is transmitted and received for each of U1 to Un and is 0.1m
32 bits can be transmitted for each S. Or data a, data b,. . . By transmitting and receiving data m only at U1, only at U2, or only at Un, 320 bits can be transmitted every 1 mS. In the embodiment, data a to data f are used for signals requiring high time resolution such as time measurement.
Data g and data h are transmitted and received every 1 mS for signals that do not require high time resolution, such as an indicator light, every 24 ms / 0.1 mS, 80 bits / 1
mS can be transmitted simultaneously.

The start signal is transmitted to the timer 9 at 1 ms using the data bit a1 to start the timer instantly. Similarly, the goal signal of the light receiver 8 is transmitted to the timer 9 at 0.1 ms using the data bit b1. The information of the display setting device is sent to the indicator every 1 ms using the low-speed data bit g1. In the time information recorded by the timer 9, data h of U1 to U10 are individually transmitted and transmitted in 40 bits.

[0012]

As described above, according to the present invention, it is possible to connect a plurality of competition timekeeping devices having different required time resolutions with a single cable when the devices are several hundred meters apart or through underground piping. Even in this case, the cable can be laid easily. In addition, even when the timekeeping system is changed, for example, by adding a timekeeping device, there is an effect that connection can be made without pulling a new cable of several hundred meters.

[Brief description of the drawings]

FIG. 1 is a diagram showing a competition timing system according to the present invention.

FIG. 2 is a diagram for explaining the operation of the competition timing system according to the present invention.

FIG. 3 is a diagram for explaining the operation of the competition timing system according to the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Bus line 2, 3, 4 I / O circuit 5 Synchronous signal generation circuit 6 Start signal generation means 7 Emitter 8 Receiver 9 Timekeeping means 10 Indicator light 11 Indicator light setting device 12 Display panel

Claims (7)

[Claims] 1. A competition timing system, comprising: a bus line composed of a single cable; a synchronization signal generation circuit connected to the bus line for outputting a synchronization signal serving as a reference for system operation to the bus line; A competition timing system comprising: a plurality of input / output circuits connected to a plurality of lines and inputting / outputting arbitrary signals to / from each other via the bus line in synchronization with the synchronization signal. 2. The competition timing system according to claim 1, wherein the synchronization signal generating circuit outputs two or more synchronization signals having different periods. 3. The competition timing system according to claim 1, wherein said input / output circuit outputs a plurality of signals continuously. 4. The input / output circuit includes a synchronous conversion circuit, receives an RS-232C serial signal, outputs the serial signal to a bus line in synchronization with the synchronous signal, and outputs a signal input from the bus line. 2. The competition timekeeping system according to claim 1, wherein the system converts the serial signal into an RS-232C serial signal and transmits the signal. 5. The input / output circuit includes an AD conversion circuit, which continuously converts an audio signal into an A / D signal, and outputs the A / D converted data to a bus line in synchronization with the synchronization signal. 2. The competition timekeeping system according to claim 1, further comprising a circuit, converting the data input from the bus line into a digital signal and outputting the data as an audio signal. 6. The competition timekeeping system according to claim 1, wherein the input / output circuit obtains power from wiring provided integrally with a bus line. 7. The competition timing system according to claim 1, wherein the input / output circuit obtains power from a DC voltage superimposed on a bus line.