JP2001333119A - Phase synchronization circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a phase synchronization circuit that can realize a phase locked loop with a wide correction range of a phase deviation without a limit of a phase shift correction range due to a limit of an oscillated frequency of a VCO. SOLUTION: The phase synchronization circuit that detects and corrects a phase shift from a received signal having the phase shift in a delay discrimination feedback sequence estimate unit 17 is provided with a correlation device 12 that detects a phase shift between the received signal (burst signal (a) and a replica and with a complex arithmetic circuit 13 that applies complex arithmetic operation to the received signal to rotate the phase on the basis of phase shift information from the correlation device 12.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase synchronization circuit of a delay decision feedback type sequence estimator, and more particularly, to a delay decision feedback type sequence in a communication system for equalizing a received signal by a narrow band modulation method such as GMSK modulation. The present invention relates to a phase synchronization circuit of an estimator.

[0002]

2. Description of the Related Art Conventionally, in a phase locked loop using a delay decision feedback type sequence estimator, a VCO (voltage
The phase rotator rotates the phase of the received signal according to the output signal of the controlled oscillator.

FIG. 7 is a block diagram showing a conventional phase locked loop. As shown in FIG. 7, the preamble correlator 2 receiving the burst signal from the receiver 1 synchronizes with the preamplifier, obtains an impulse response by the preamble, and sends the impulse response to the tap coefficient setting circuit 3.

[0004] The tap coefficient setting circuit 3 sets the number of taps of the delay decision feedback type sequence estimator 4 based on the impulse response received from the preamble correlator 2. After initial setting of the number of taps, the delay determination feedback type sequence estimator 4 estimates and determines the data signal up to the end of the burst, and the estimated and determined data becomes demodulated data as it is.

[0005] A replica generator 5 generates a replica based on the estimated decision data output from the delay decision feedback type sequence estimator 4. The phase detector 6 compares the replica from the signal from the phase rotator 7 with the filter 8a and the VCO
A loop for controlling the phase rotator 7 through 8b to correct the phase error is formed.

[0006]

However, according to the conventional phase-locked loop, the range that can be corrected for the phase fluctuation largely depends on the limitation of the oscillating frequency range of the VCO 8b, and cannot be handled depending on the width of the phase shift. Would.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a phase locked loop circuit capable of realizing a phase locked loop having a wide range of phase shift correction without limitation of the phase shift correction range due to the limitation of the oscillation frequency of the VCO. .

[0008]

In order to achieve the above object, a phase locked loop circuit according to the present invention comprises a phase determining circuit for detecting and correcting a phase shift from a phase shifted received signal in a delay decision feedback type sequence estimator. The synchronization circuit includes a correlator that detects a phase shift between a received signal and a replica signal, and a complex operation circuit that performs a complex number operation on the received signal and performs phase rotation based on the phase shift information from the correlator. It is characterized by:

With the above configuration, the correlator can
The complex arithmetic circuit detects the phase shift between the received signal and the replica signal, and performs a complex operation on the received signal based on the phase shift information from the correlator to rotate the phase. Correct the misalignment. As a result, the VCO becomes unnecessary, and there is no limitation on the phase shift correction range due to the limitation of the oscillation frequency of the VCO, and a phase locked loop having a wide phase shift correction range can be realized.

[0010]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing a configuration of a phase locked loop circuit according to an embodiment of the present invention. FIG. 2 is an explanatory diagram of a reception signal received by the receiver in FIG.

As shown in FIG. 1, the phase synchronization circuit 10
The correlator 12 is used in the delay decision feedback signal estimator 11.
And a complex operation circuit 13. The delay decision feedback signal estimator 11 includes a phase synchronization circuit 10, a preamble correlator 15, a tap coefficient setting circuit 16, a delay decision feedback sequence estimator 17, a replica generator 18, and an adaptive control circuit 19. ing.

The receiver 14 includes a band-pass filter for extracting a signal of a required band from the received signal, a mixer for performing quadrature modulation, a 0/90 degree phase generator, an oscillator, and an A / D converter for converting the quadrature-demodulated signal into an A signal. / D (analog digita)
l) An A / D converter for conversion is provided and outputs a real part amplitude value signal and an imaginary part amplitude value signal.

As shown in FIG. 2, a received signal output from the receiver 14, ie, a burst signal a, is subjected to carrier detection,
It consists of an AGC setting, an AFC setting, a tap coefficient setting, a preamble burst composed of synchronization bits, and a data burst composed of data.

The preamble correlator 15 receives the burst signal a from the receiver 14, synchronizes with the preamplifier during the burst period, estimates the impulse response by the preamble, and converts the impulse response into a tap coefficient setting circuit 16
Send to

The tap coefficient setting circuit 16 sets an initial value of the number of taps of the delay decision feedback type sequence estimator 17 based on the impulse response received from the preamble correlator 15.

After initial setting of the number of taps, the delay determination feedback type sequence estimator 17 estimates and determines the data signal up to the end of the burst, and the estimated and determined data becomes demodulated data as it is.

The replica generator 18 generates a replica signal based on the impulse response value and information from the delay decision feedback type sequence estimator 17.

The correlator 12 compares the phase of the replica signal b from the replica generator 18 with the phase of the signal received from the receiver 14, and outputs the obtained phase difference information c to the complex operation circuit 13.

FIG. 3 is a block diagram showing the configuration of the correlator shown in FIG. As shown in FIG. 3, the correlator 12 complex-conjugates the received signal (burst signal a) from the receiver 14, performs complex multiplication with the replica signal b from the replica generator 18, and averages the multiplication result. Later, the phase difference information c is output.

The complex operation circuit 13 performs complex multiplication for rotating the phase of the signal received from the receiver 14 based on the phase difference information c from the correlator 12.

The adaptive control circuit 19 changes the number of taps of the delay decision feedback type sequence estimator 17 even during the burst period from the input data of the delay decision feedback type sequence estimator 17 and the replica signal b from the replica generator 18. And control is performed to obtain optimal estimation data.

Here, the phase difference between the received signal a and the replica signal b is 2πΔft, and the received signal a is r (t) e ^j2 πΔ
^{If ft} and the replica signal b are r ′ (t), r (t) e ^−j2 πΔ ^ft when the received signal a is complex-conjugated, and then r (t) when complex multiplication with the replica signal b is performed. e
^{-j2πΔ ft} · r ′ (t) = r (t) r ′ (t) e ^-j2 πΔ
^ft . When the amplitude is normalized, it becomes e ^-j2 πΔ ^ft , and the phase difference information c becomes e ^-j2 πΔ ^ft .

In the complex operation circuit 13, the received signal a and the phase
Complex multiply the difference information c, and r (t) e ^j2πΔ^fte^-j2πΔ
^ft= R (t). r (t) is a delay decision feedback type sequence
The replica signal is obtained by the estimator 17 and the replica generator 18.
b is r '(t). This allows the phase synchronization loop
To form a loop.

That is, the delay decision feedback type signal estimator 11 having the above-described configuration determines the phase shift between the replica signal from the replica generator 18 and the received signal from the receiver 14 by the correlator 12. , And sends out a phase shift signal. The complex operation circuit 13 corrects the phase shift by rotating the phase of the received signal by complex multiplication performed according to the phase shift signal.

In this way, when the correlator 12 is used in place of the phase detector and the filter, the received signal is obtained by using the complex multiplication circuit 13 without using the VCO and the phase rotator as in the related art. Can be corrected, there is no limit on the phase shift correction range due to the limitation of the oscillation frequency of the VCO, and a phase locked loop with a wide phase shift correction range can be realized.

Accordingly, the delay decision feedback signal estimator 1
1 is GMSK (gaussianfiltered)
A phase-locked loop for detecting and correcting a phase shift from a phase-shifted received signal in a communication system that obtains transmission path characteristics during a preamble period and equalizes the received signal by a narrow band modulation method such as minimum shift keying modulation. When correcting the phase shift of the received signal, the correlator 12 and the complex multiplication circuit 13 do not use a phase detector, a filter, a VCO and a phase rotator.
Is used, the correction range of the phase shift is widened.

FIG. 4 is a block diagram showing a configuration of a signal estimator using a maximum likelihood sequence estimator according to another embodiment of the present invention. As shown in FIG. 4, a signal estimator 20 using a maximum likelihood sequence estimator uses a maximum likelihood sequence estimator 21 instead of the delay decision feedback type sequence estimator 17. in this case,
Only the estimation of the decision data is changed to the maximum likelihood sequence estimator 21, and the operation of the synchronous loop is the same as that of the delay decision feedback signal estimator 11 (see FIG. 1).

FIG. 5 is a block diagram showing a configuration of a delay decision feedback type signal estimator according to still another embodiment of the present invention. FIG. 6 is a delay decision feedback with provisional decision data output terminal of FIG. FIG. 3 is a block diagram illustrating a type sequence estimator.

As shown in FIG. 5, the delay decision feedback type signal estimator 25 generates a replica using the temporary estimation data instead of using the estimation data. Instead, a delay decision feedback type sequence estimator 26 with a provisional decision data output terminal capable of outputting provisional decision data is used.

As shown in FIG. 6, the delay decision feedback type sequence estimator 26 with the provisional decision data output terminal has a maximum likelihood sequence estimator 27 and a decision feedback type equalizer 28. The estimation result of the detector 27 is output as the temporary judgment data d.
The replica generator 18 generates a replica based on the temporary determination data d.

The correlator 12 compares the phase of the replica signal b from the replica generator 18 with the phase of the received signal (burst signal a) from the receiver 14, and outputs phase difference information c to the complex operation circuit 13.

By doing so, it is possible to obtain the phase difference information c and correct the phase shift without waiting for the determination result of the decision feedback equalizer 28. As a result, a phase-locked loop with good responsiveness can be realized.

Therefore, as shown in the above embodiments,
A phase locked loop circuit 10 according to the present invention includes a correlator 12 for detecting a phase shift between a received signal and a replica, and a complex operation for performing a complex number operation on the received signal to perform phase rotation based on phase shift information from the correlator 12. With the circuit 13, it is possible to correct the phase shift, and it is possible to correct for a wider range of phase shift than in the case of the conventional phase locked loop.

[0035]

As described above, according to the present invention, the correlator detects the phase shift between the received signal and the replica, and the complex operation circuit detects the received signal based on the phase shift information from the correlator. The complex number operation is performed to rotate the phase, and the phase shift is corrected from the phase-shifted received signal.
CO is unnecessary, and there is no limitation on the phase shift correction range due to the limitation of the oscillation frequency of the VCO, so that a phase locked loop with a wide phase shift correction range can be realized.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a phase locked loop circuit according to an embodiment of the present invention.

FIG. 2 is an explanatory diagram of a reception signal received by the receiver of FIG.

FIG. 3 is a block diagram illustrating a configuration of a correlator in FIG. 1;

FIG. 4 is a block diagram showing a configuration of a signal estimator using a maximum likelihood sequence estimator according to another embodiment of the present invention.

FIG. 5 is a block diagram showing a configuration of a delayed decision feedback signal estimator according to still another embodiment of the present invention.

FIG. 6 is a block diagram illustrating a delay decision feedback type sequence estimator with a provisional decision data output terminal in FIG. 5;

FIG. 7 is a block diagram showing a conventional phase locked loop.

[Explanation of symbols]

Reference Signs List 10 phase synchronization circuit 11, 25 delay decision feedback signal estimator 12 correlator 13 complex operation circuit 14 receiver 15 preamble correlator 16 tap coefficient setting circuit 17 delay decision feedback sequence estimator 18 replica generator 19 adaptive control circuit 20 Signal Estimator Using Maximum Likelihood Sequence Estimator 21 Maximum Likelihood Sequence Estimator 26 Delay Decision Feedback Type Estimator with Temporary Decision Data Output Terminal 27 Maximum Likelihood Sequence Estimator 28 Decision Feedback Equalizer a Burst Signal b Replica Signal c Phase difference information d Temporary judgment data

Claims (6)

[Claims] 1. A phase synchronization circuit for detecting and correcting a phase shift from a phase-shifted received signal in a delay decision feedback type sequence estimator, a correlator for detecting a phase shift between a received signal and a replica signal, A complex operation circuit for performing a complex operation on the received signal based on the phase shift information from the correlator to rotate the phase. 2. A preamble correlator receiving a reception signal output from a receiver, synchronizing with a preamplifier during a burst period, estimating an impulse response by a preamble, and sending the impulse response to a tap coefficient setting circuit; After the initial setting of the number, a delay decision feedback sequence estimator for estimating and determining the data signal up to the end of the burst, and an impulse response received from the preamble correlator, the number of taps of the delay decision feedback sequence estimator A tap coefficient setting circuit for setting an initial value of, a replica generator for generating a replica signal based on an impulse response value and information from the delay decision feedback type sequence estimator, and input data of the delay decision feedback type sequence estimator and From the replica signal, the number of taps of the delay decision feedback type sequence estimator even during a burst period 2. The phase-locked loop according to claim 1, further comprising: an adaptive control circuit configured to control the phase change so as to obtain optimal estimation data. 3. The correlator complex-conjugates a received signal from the receiver, multiplies the replica signal from the replica generator by a complex number, averages the multiplication result, and outputs phase difference information. The phase-locked loop circuit according to claim 2, wherein: 4. The phase according to claim 2, wherein a maximum likelihood sequence estimator is used in place of the delay decision feedback type sequence estimator, and the decision data is estimated by the maximum likelihood sequence estimator. Synchronous circuit. 5. A delay decision feedback sequence estimator having a provisional decision data output terminal capable of outputting provisional decision data, instead of the delay decision feedback sequence estimator. Or the phase-locked loop circuit according to 3. 6. A GMSK (gaussian filter)
6. A communication system for performing equalization of a received signal by obtaining transmission path characteristics during a preamble period by a narrow-band modulation method such as red minimum keying modulation. Phase synchronization circuit.