JP2001332461A - Revised information output circuit for semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve the problem in the conventional that often revised steps among process steps of manufacturing semiconductor devices need to be set previously, and the number of revision could not be counted, if a step which is not yet set was revised, resulting in no revised version information being able to be outputted. SOLUTION: The circuit contained in a semiconductor device counts the number of revision and outputs the count result to outside the semiconductor device as a revised version information signal. The counting uses digital signals obtained by timely switching on an off a power line connected electrically to a power source and/or a ground line connected electrically to a ground potential feed source disposed in the semiconductor device, every time a step for manufacturing of the semiconductor device is revised.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to revision information of a semiconductor device which can easily manage the revision when the revision is made by electrically outputting the number of revisions in the manufacturing process of the semiconductor device as revision version information. It relates to an output circuit.

[0002]

2. Description of the Related Art In general, defects found in inspections and the like during the manufacture of semiconductor devices are appropriately corrected by revising the manufacturing process. For example, the pattern of a mask used in a film forming process or an etching process for forming a semiconductor device is revised in accordance with the above-mentioned problem.

Further, when it is required to eliminate the above-mentioned problems promptly in order to maintain the productivity as in a mass production factory for semiconductor devices, the devices before and after the revision may be produced in parallel.

However, when the manufacturing process is revised,
Inspection programs may be changed accordingly,
The management of semiconductor devices manufactured by revising the manufacturing process has become complicated.

There is a semiconductor device having a revision information output circuit for outputting data corresponding to the revision when the revision is made in the production process in order to facilitate the management accompanying the revision of the production process. . FIG. 5 is a circuit diagram showing a configuration of a revision information output circuit in a conventional semiconductor device as described above. In the figure, 5 is a DC power supply V _DD
Power supply, _{V SS} supply source is a source of ground potential is 6, 17
23 to 23 are chip IDs which are output circuits of revision information for outputting data corresponding to revisions in a semiconductor device manufacturing process.
An inverter for outputting an output permission signal from each of the chip ID circuits 17 to 23 to each of the ports 1 to 7;
a, a ', b, b' are wirings formed in a twice-stacking step (hereinafter abbreviated as "two aluminum steps") of an aluminum thin film, which is frequently revised in the semiconductor device manufacturing process. _Are electrically connected to the _VDD power supply 5, and the wirings a ′ and b ′ are electrically connected to the _VSS supply source 6. c,
c ′, d and d ′ are wirings formed in a single lamination step (hereinafter abbreviated as “1 aluminum step”) of an aluminum thin film, which is frequently revised in the semiconductor device manufacturing process. _It is electrically connected to the _DD power supply 5, and the wiring c ′,
d ′ is electrically connected to the _VSS supply source 6. e, e ',
f, f ′ are wirings formed in a through-hole forming step (hereinafter abbreviated as “through-hole step”), which is frequently revised in the semiconductor device manufacturing process.
_DD power to 5 and electrically connected, wiring e ', f' is _{V SS}
It is electrically connected to the supply source 6. g and g ′ are wirings formed in a gate electrode forming step (hereinafter abbreviated as a gate step) that is frequently revised in the semiconductor device manufacturing process. The wiring g is electrically connected to the _VDD power supply 5. , Wiring g '
_Are electrically connected to the _VSS supply source 6.

Next, the operation will be described. First, in the initially designed mask pattern, as shown in FIG.
Wirings a ', b', c ', d', e ', f', g 'are formed, and wirings a, b, c, d, e, f, g are formed so as to be in an open state. No Thus, there is no problem in the specification of design time, if the semiconductor device is manufactured, a data value 0 since none output of the chip ID circuit 17-23 to V _SS supply 6 the same potential . in this way,
When manufactured according to the specifications at the time of design, each of the chip ID circuits 17 to
23 is 0000000 7-bit data (no revision)
Are output to ports 1 to 7.

At this time, if a defect is found in the manufactured semiconductor device and, for example, a revision is made to the 2-aluminum process, the chip ID circuit 17 corresponding to the 2-aluminum process is also changed and the 2-aluminum process is changed. Enable to output a signal to notify that the revision has been made. Specifically, the wiring a ′ of the chip ID circuit 17 is cut off from the revised mask, and a pattern for forming the wiring a is added. Here, wiring a '
The disconnection does not involve mechanical disconnection. For example, a pattern that forms a circuit in which the ground potential is not output to the inverter 24 from the _VSS supply source 6 via the wiring a ′ corresponds to a 2-aluminum process. This is performed by adding to the mask pattern. As a result, the chip ID circuit 17 of the semiconductor device manufactured through the revised two aluminum process
Is that the wiring a is formed and the wiring a ′ is cut off (that is, a circuit for preventing the output of the wiring a ′ to the inverter 24 is formed), and the data of the value 1 is supplied from the _VDD power supply 5 to the inverter 24. Is output. Other chip ID circuits 18-2
3, the wirings b ', c', d ', and
Since e ′, f ′, and g ′ are formed, data having a value of 0 is output to the inverter 24. Therefore, if the 2 aluminum process is revised, each of the chip ID circuits 17 to 23 becomes 000
7-bit data of 0001 is output to ports 1-7.

Here, if there is a second revision in the second aluminum process, first, the chip ID circuit 17 is added to the revised mask.
Is formed, the wiring a is separated, the wiring b 'of the chip ID circuit 18 is separated, and a pattern for forming the wiring a is added. Thereby, each chip ID circuit 17-2
3 is port 7 to 7-bit data of 0000010
Output to Similarly, when there is a third revision in the second aluminum process, the wiring a 'of the chip ID circuit 17 is separated from the revised mask, and a wiring a is formed.
By separating the wiring b ′ of No. 8 and adding a pattern for forming the wiring a, each of the chip ID circuits 17 to 23 becomes 0
The 7-bit data of 000011 is output to ports 1-7.

Considering the case where the first aluminum process has been revised after the above three aluminum processes have been revised, the chip ID circuit 19 corresponding to one aluminum process has been revised.
Then, the wiring c ′ is separated from the revised mask, and a pattern for forming the wiring c is added. As a result, each of the chip ID circuits 17 to 23 outputs 7-bit data of 0000111 to the ports 1 to 7.

As described above, each chip ID circuit 17
23 can output up to three revisions in binary notation as revision version information for each manufacturing process of 1 aluminum process, 2 aluminum process, and through hole process, and update up to 2 times in the gate process. It can be output as revision version information. In other words, the revision information output circuit in the conventional semiconductor integrated circuit device, when a revision is made to a preset manufacturing process, outputs the revised production process and the number of revisions as revision version information. can do.

[0011]

Since the conventional revision information output circuit of a semiconductor device is configured as described above, it is necessary to set in advance the semiconductor device manufacturing process in which the revision occurs frequently. However, even if there is a revision in the process that has not been set, if the set process that does not need to be revised is not revised, the number of revisions cannot be counted and the revision version information cannot be output. was there. In other words, if the revised process is not the preset process, in order to count the revision, disconnect the wiring corresponding to the preset process that does not need to be revised,
Alternatively, it is necessary to make a connection, which causes an increase in the cost of the mask.

In addition, since a circuit for counting the number of revisions is provided in the semiconductor device for each preset manufacturing process, there is a problem that counting cannot be performed if there are many revisions. More specifically, a complicated circuit that counts a large number of times requires a relatively large installation area, and the number of newly added circuits increases in order to provide such a circuit for each manufacturing process. For this reason, considering that there is a limitation in the circuit installation space due to the miniaturization of the semiconductor device and the like, the circuit installation area allowed for each manufacturing process is naturally reduced, and a complicated circuit that counts many times is manufactured. It was difficult to provide each time.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problem, and utilizes the existing power supply wiring and grounding wiring in a semiconductor device to determine the number of revisions to the manufacturing process of the semiconductor device as revision version information. It is an object of the present invention to obtain a revision information output circuit of a semiconductor device which can easily manage when a revision is made by electrically outputting the revision information.

[0014]

SUMMARY OF THE INVENTION A revision information output circuit for a semiconductor device according to the present invention is a circuit built in the semiconductor device, and is provided in the semiconductor device every time the semiconductor device manufacturing process is revised. The number of revisions made using digital signals obtained by appropriately opening and closing the power supply wiring electrically connected to the power supply and / or the ground wiring electrically connected to the ground potential supply source. The counting is performed, and the counting result is output to the outside of the semiconductor device as a revised version information signal.

A revision information output circuit of a semiconductor device according to the present invention includes an output circuit for outputting a revision version information signal based on an output permission signal input from outside the circuit.

The revision information output circuit for a semiconductor device according to the present invention receives a mode switching signal indicating an operation mode of the semiconductor device from outside the circuit, and operates the semiconductor device based on the mode switching signal without using an existing input / output terminal. If it is determined that the mode is the mode, an output circuit for outputting a revised version information signal from an existing input / output terminal is provided.

A revision information output circuit of a semiconductor device according to the present invention includes an output circuit for sequentially outputting a revision version information signal via a single input / output terminal.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below. Embodiment 1 FIG. FIG. 1 is a circuit diagram showing a configuration of a revision information output circuit of a semiconductor device according to a first embodiment of the present invention. In the figure, reference numerals 1 to 4 denote chip ID circuits (revision information output circuits). Each of the chip ID circuits 1 to 4 corresponds to each bit of a 4-bit binary value representing the number of revisions. Reference numeral 5 denotes a _VDD power supply (power supply) for supplying a power supply potential to the semiconductor device, and a power supply potential from an existing power supply wiring 5a in the semiconductor device and wirings a1 to a4, b1 to b4, c1 to c4, and d1 to d4. The data is supplied to the chip ID circuits 1 to 4 via the CPU. Reference numeral 5a denotes an existing power supply line for supplying a power supply potential from the _VDD power supply 5 into the semiconductor device. 6 is V for supplying a ground potential to the semiconductor device.
_{An SS} supply source (supply source of the ground potential) applies the ground potential from the existing ground wire 6a in the semiconductor device to the wires a'0 to a '.
4, b'0 to b'4, c'0 to c'4, d'0 to d'4
To the chip ID circuits 1-4. 6a is an existing ground line supplying the ground potential from V _SS supply source 6 in the semiconductor device. Reference numeral 7 denotes an inverter which outputs an output permission signal from each of the chip ID circuits 1 to 4 to each of the ports 1 to 4.

A1 to a4, a'0 to a'4 are power supply wires 5
a and a ground line 6a are supplied to the chip ID circuits 1 to 4 as appropriate, a digital signal used for counting the number of revisions in the manufacturing process is input, and a line for outputting to the inverter 7 is provided. is there. Here, the wiring a
1 to a4 and the wirings a'0 to a'4 are connected or disconnected when, for example, a two-layer lamination process of aluminum thin films (hereinafter abbreviated as a two-aluminum process) is revised in the semiconductor device manufacturing process. Shall be. Also, wires a1 to a
4 are electrically connected to the power supply wiring 5a, and the wirings a'0 to a '
4 is electrically connected to the ground wiring 6a.

B1 to b4 and b'0 to b'4 are connected to the power supply wiring 5 through the wirings a1 to a4 and the wirings a'0 to a'4, respectively.
a and a ground line 6a are supplied to the chip ID circuits 1 to 4 as appropriate, a digital signal used for counting the number of revisions in the manufacturing process is input, and a line for outputting to the inverter 7 is provided. is there. Here, wiring b
The semiconductor devices 1 to b4 and the wirings b'0 to b'4 are connected or disconnected when, for example, there is a revision in a through-hole forming process (hereinafter abbreviated as a through-hole process) in the semiconductor device manufacturing process. . Wirings b1 to b4 are electrically connected to power supply wiring 5a via wirings a1 to a4, and wirings b'0 to b'4 are electrically connected to ground wiring 6a via wirings a'0 to a'4. Connect to

C1 to c4, c'0 to c'4 are wirings a1 to a4, b1 to b4 and wirings a'0 to a'4, b ', respectively.
The power supply potential and the ground potential from the power supply wiring 5a and the ground wiring 6a are appropriately supplied to the chip ID circuits 1 to 4 via 0 to b'4, and a digital signal used for counting the number of revisions of the manufacturing process is input. , And wiring for outputting to the inverter 7. Here, the wirings c1 to c4 and the wiring c'0
-C'4 shall be connected or disconnected if, for example, there is a revision in the single lamination process of aluminum thin film (hereinafter abbreviated as 1 aluminum process) in the manufacturing process of the semiconductor device. Also, the wirings c1 to c4 are the wirings a1 to a4, b1
To the power supply wiring 5a through the wirings c'0 to c'4 and the wirings a'0 to a'4, b'0 to b'4
Is electrically connected to ground wiring 6a through

D1 to d4, d'0 to d'4 are wirings a1 to a4, b1 to b4, c1 to c4, and wirings a'0 to
The power supply potential and the ground potential from the power supply wiring 5a and the ground wiring 6a are appropriately supplied to the chip ID circuits 1 to 4 via a'4, b'0 to b'4, c'0 to c'4, Input the digital signal used to count the number of revisions of
This is a wiring for outputting to the inverter 7. here,
The wirings d1 to d4 and the wirings d'0 to d'4 are formed, for example, in a gate electrode forming step (hereinafter, referred to as a gate electrode forming step) in the semiconductor device manufacturing process.
If there is a revision in the gate process), it will be connected or disconnected. Also, the wirings d1 to d4 are wiring a
Power supply wiring 5 through 1 to a4, b1 to b4, c1 to c4
a'0, and the wirings d'0 to d'4 are connected to the wiring a'0.
To a'4, b'0 to b'4, c'0 to c'4, and is electrically connected to the ground wiring 6a.

Next, the operation will be described. First, in the mask pattern of the original design, as shown in FIG.
Wirings a'0, b'0, c'0, d'0 are formed. As a result, when there is no defect in the specification at the time of design and the semiconductor device is manufactured, all the outputs of the chip ID circuits 1 to 4 have the same potential as that of the _VSS supply source 6 and thus have data of value 0. . As described above, when manufactured according to the specification at the time of design, each of the chip ID circuits 1 to 4 outputs 0000 4-bit data (no revision) to the ports 1 to 4.

When a defect is found in the manufactured semiconductor device and, for example, the second aluminum process is revised for the first time, the wiring a'0 in the chip ID circuit 1 is separated from the revised mask, and the wiring is removed. A pattern forming a1 is added. Here, disconnection of the wiring a'0 instead of performing a mechanical disconnect, as described in the prior art, for example, V _SS supply output from the 6 to the inverter 7 is ground potential via the wire a'0 The pattern that forms the circuit
This is performed by adding to a mask pattern corresponding to the aluminum process. As a result, in the chip ID circuit 1 of the semiconductor device manufactured through the revised two-aluminum process, the wiring a1 is connected and the wiring a'0 is disconnected (that is, the output of the wiring a'0 to the inverter 7). circuitry for blocking is form a), V _D from _D power supply 5 data value 1 is the inverter 7
Is output to In the other chip ID circuits 2 to 4, the wirings a'0, b'0, c'0, and d'0 are connected as they are at the time of design, so that data of value 0 is stored in the chip ID circuits 2 to 4. Is output to each inverter 7. Therefore, when the two aluminum process is revised, each of the chip ID circuits 1 to 4 outputs 4-bit data of 0001 to the ports 1 to 4.

Next, if the second revision is in the 1 aluminum process, the revised mask is used to connect the wiring a1 of the chip ID circuit 1
And a wiring c'3 is formed, a wiring c'0 of the chip ID circuit 2 is separated, and a pattern for forming the wiring c3 is added. As a result, each of the chip ID circuits 1 to 4 becomes 00
10-bit (2 in decimal) 4-bit data
Output to

Further, when the through hole process is revised for the third time, the wiring c'3 of the chip ID circuit 1 is cut off and the pattern for forming the wiring b2 is added to the revised mask. As a result, each of the chip ID circuits 1 to 4 becomes 001
It outputs 4-bit data of 1 (3 in decimal) to ports 1-4.

Similarly, after a fourth revision of the gate process, the wiring b2 of the chip ID circuit 1 is cut off on the revised mask to form a wiring d'4, and the chip ID
The wiring c3 of the circuit 2 is separated, the wiring d'4 is formed, the wiring d'0 of the chip ID circuit 3 is separated, and a pattern for forming the wiring d4 is added. By this, each chip ID
The circuits 1 to 4 output 4-bit data of 0100 (4 in decimal) to the ports 1 to 4.

As described above, by cutting and connecting the wiring in the chip ID circuits 1 to 4 in accordance with each manufacturing process,
The number of revisions can be output as revision version information, and it corresponds to each bit of a 4-bit binary number representing the number of revisions (when the circuit of the present invention is equivalent to 4 bits) regardless of which manufacturing process is revised. , The number of revisions is 0000, 0001, 0
010, 0011 to 1111 can be sequentially counted 15 times.

In the above embodiment, one aluminum process,
(2) The wiring to be cut and connected was determined according to the aluminum process, the through hole process, and the gate process. However, the present invention is not limited to the above process, and there is a revision in any manufacturing process using a mask. In this case, wiring to be cut and connected may be appropriately arranged.

As described above, according to the first embodiment, each time the semiconductor device manufacturing process is revised, the power supply wiring 5a provided in the semiconductor device and electrically connected to the _VDD power supply 5 is provided. and / or the ground wire 6a for connecting V _SS supply 6 electrically, counts the number of times the revision has been performed using the digital signal obtained by opening and closing appropriate, revised version information signal the count results Is output outside the semiconductor device, the setting of the manufacturing process for counting the number of revisions is omitted, and the number of revisions that can be counted can be increased as compared with the related art. Also, no matter which manufacturing process is revised at the time of revision, the number of revisions can be sequentially output as a revision version information signal. It is not necessary to disconnect or connect the wiring corresponding to the above, and the cost of the mask is not increased.

Embodiment 2 The second embodiment includes an output circuit that outputs a revision version information signal based on an output permission signal input from outside the circuit.

FIG. 2 is a circuit diagram showing a configuration of a revision information output circuit of a semiconductor device according to a second embodiment of the present invention.
In the figure, reference numerals 8 to 11 denote n-type transistors (output circuits) which output revision version information signals output from chip ID circuits 1 to 4 to ports 1 to 4 based on an output permission signal input from outside the circuit. 8 to 11, except when outputting the revised version information signal.
4 is used as a normal port. The same components as those in FIG. 1 are denoted by the same reference numerals, and duplicate description will be omitted.

Next, the operation will be described. The operation of counting the number of revisions in the manufacturing process of the semiconductor device is the same as that of the first embodiment, and therefore, a duplicate description will be omitted. Here, the operation of outputting the counted number of revisions as revision version information to the outside of the device will be described. explain. The setting of the output permission signal may be appropriately performed by a user from outside using, for example, an external input / output terminal provided in the semiconductor device. If the semiconductor device has a CPU, the output permission signal may be set. The setting may be made by causing the CPU to process a program for outputting a signal.

As described above, when the output permission signal (H level signal of value 1 in the illustrated example) is set, the output permission signal is input to the gate electrodes of the transistors 8 to 11 and each chip Revised version information signals from the inverters 7 in the ID circuits 1 to 4 are guided to the respective ports 1 to 4 and output outside the device.

As described above, according to the second embodiment, transistors 8 to 11 for outputting a revision version information signal based on an output permission signal input from outside the circuit.
Therefore, the ports 1 to 4 for outputting the revision version information signal to the outside of the device can be used as normal ports of the semiconductor device when the output permission signal is not received. Thus, since existing terminals can be used, it is not necessary to provide new external input / output terminals, and the cost of the semiconductor device can be reduced.

Embodiment 3 FIG. In the third embodiment, a mode switching signal indicating the operation mode of the semiconductor device is input from outside the circuit, and if it is determined from the mode switching signal that the semiconductor device is in an operation mode that does not use an existing input / output terminal, And an output circuit for outputting a revised version information signal from the input / output terminal of the second embodiment.

FIG. 3 is a circuit diagram showing a configuration of a revision information output circuit of a semiconductor device according to a third embodiment of the present invention.
In the figure, reference numerals 12 to 15 denote n-type transistors (output circuits) which output revision version information signals output from the chip ID circuits 1 to 4 to ports 1 to 4 based on a mode switching signal input from outside the circuit. Ports 1 to 4 are used as normal ports except when the revision version information signal is output according to 12 to 15. FIG.
The same components as those described above are denoted by the same reference numerals, and redundant description will be omitted.

Next, the operation will be described. The operation of counting the number of revisions in the manufacturing process of the semiconductor device is the same as that of the first embodiment, and therefore, a duplicate description will be omitted. Here, the operation of outputting the counted number of revisions as revision version information to the outside of the device will be described. explain. The setting of the mode switching signal may be appropriately performed by a user from outside using, for example, an external input / output terminal provided in the semiconductor device. If the semiconductor device has a CPU,
The program for outputting the mode switching signal is stored in the CP
You may set by making U process.

As described above, when the mode switching signal (H level signal of value 1 in the illustrated example) is set, this mode switching signal is input to the gate electrodes of the transistors 12 to 15 and Inverter 7 in ID circuits 1-4
Is output to each of the ports 1 to 4 and output to the outside of the apparatus.

As described above, according to the third embodiment, the mode switching signal indicating the operation mode of the semiconductor device is input from the outside of the chip ID circuits 1 to 4, and the semiconductor device is connected to the existing port based on the mode switching signal. If it is determined that the operation mode does not use any of the transistors 1 to 4, the transistors 12 to 15 output the revision version information signal from the ports 1 to 4.
Therefore, when the semiconductor device is not in the operation mode using the ports 1 to 4 based on the mode switching signal, these can be used as the normal ports of the semiconductor device. Thus, since existing terminals can be used, it is not necessary to provide new external input / output terminals, and the cost of the semiconductor device can be reduced.

Embodiment 4 FIG. The fourth embodiment has an output circuit for sequentially outputting a revision version information signal via a single input / output terminal.

FIG. 4 is a circuit diagram showing a configuration of a revision information output circuit of a semiconductor device according to a fourth embodiment of the present invention.
In the figure, reference numeral 16 denotes a serial output for sequentially outputting a revision version information signal output from the chip ID circuits 1 to 4 via an existing port (one input / output terminal) in synchronization with a transfer clock signal input from the semiconductor device. The circuits (output circuits) 16a to 16d internally synchronize the signal output from the inverter 7 in each of the chip ID circuits 1 to 4 with the transfer clock signal via the clock supply line 17 and sequentially output the signals in units of transfer bits. A circuit (output circuit) 17 is a clock supply line (output circuit) that supplies a transfer clock signal from the semiconductor device to the internal circuits 16a to 16d. The same components as those in FIG. 1 are denoted by the same reference numerals, and duplicate description will be omitted.

Next, the operation will be described. The operation of counting the number of revisions in the manufacturing process of the semiconductor device is the same as that of the first embodiment, and therefore, a duplicate description will be omitted. Here, the operation of outputting the counted number of revisions as revision version information to the outside of the device will be described. explain. Internal circuit 16a of serial output circuit 16 via clock supply line 17
-16d are supplied with a transfer clock signal from the semiconductor device, and each chip I
Revised version information signals from the inverters 7 in the D circuits 1 to 4 are sequentially output to the outside of the device from a single port for each transfer bit unit.

As described above, according to the fourth embodiment, the output circuit for sequentially outputting the revision version information signal via the single input / output terminal is provided. Since the number of terminals used can be minimized, the cost of the semiconductor device can be reduced. Further, terminals of the semiconductor device can be effectively used for other processing.

[0045]

As described above, according to the present invention, a power supply and an electric circuit provided in a semiconductor device each time a manufacturing process of the semiconductor device is revised. The number of revisions is made using a digital signal obtained by appropriately opening and closing a power supply line that is electrically connected and / or a ground line that is electrically connected to a ground potential supply source. Is output to the outside of the semiconductor device as a revision version information signal, so that setting of a manufacturing process for counting the number of revisions is omitted, and the number of revisions that can be counted can be increased as compared with the related art. Also, no matter which manufacturing process is revised at the time of revision, the number of revisions can be sequentially output as a revision version information signal,
Unlike the related art, in order to count revisions, it is not necessary to disconnect or connect wiring corresponding to a preset process that does not require revision, and the cost of the mask does not increase.

In addition, since the existing configuration is used in the semiconductor device, the revision information output circuit can be realized with a minimum number of additional circuits, so that the area occupied in the semiconductor device can be reduced. is there.

According to the present invention, since the output circuit for outputting the revision version information signal based on the output permission signal input from outside the circuit is provided, the input / output terminal for outputting the revision version information signal outside the device is connected to the output terminal. When the permission signal is not received, it can be used as a normal input / output terminal of the semiconductor device. As a result, since existing terminals can be used, there is no need to provide new external input / output terminals, and the cost of the semiconductor device can be reduced.

According to the present invention, the mode switching signal indicating the operation mode of the semiconductor device is input from outside the circuit, and it is determined from the mode switching signal that the semiconductor device is in the operation mode in which the existing input / output terminal is not used. And an output circuit for outputting a revised version information signal from an existing input / output terminal. Therefore, when the semiconductor device is not in the operation mode using the external input / output terminal from the mode switching signal, these are output to the external device in the normal state of the semiconductor device. It can be used as an input / output terminal. As a result, since existing terminals can be used, there is no need to provide new external input / output terminals, and the cost of the semiconductor device can be reduced.

According to the present invention, since the output circuit for sequentially outputting the revision version information signal via the single input / output terminal is provided, the number of terminals used for outputting the revision version information signal is minimized. Since this can be suppressed, there is an effect that the cost of the semiconductor device can be reduced. Further, there is an effect that terminals of the semiconductor device can be effectively used for other processing.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a configuration of a revision information output circuit of a semiconductor device according to a first embodiment of the present invention;

FIG. 2 is a circuit diagram showing a configuration of a revision information output circuit of a semiconductor device according to a second embodiment of the present invention;

FIG. 3 is a circuit diagram showing a configuration of a revision information output circuit of a semiconductor device according to a third embodiment of the present invention;

FIG. 4 is a circuit diagram showing a configuration of a revision information output circuit of a semiconductor device according to a fourth embodiment of the present invention.

FIG. 5 is a circuit diagram showing a configuration of a revision information output circuit in a conventional semiconductor device.

[Explanation of symbols]

1-4 Chip ID circuit (revision information output circuit), 5 V
_DD power supply (power supply), 5a power supply wiring, 6 V _SS supply source (supply source of ground potential), 6a ground wiring, 7 inverters, 8 to 11 n-type transistors (output circuits), 12 to
15 n-type transistor (output circuit), 16 serial output circuit (output circuit), 16a to 16d internal circuit (output circuit), 17 clock supply line (output circuit), a1 to a
4, a'0 to a'4 wiring, b1 to b4, b'0 to b '
4 wiring, c1-c4, c'0-c'4 wiring, d1-
d4, d'0 to d'4 wiring.

Claims (4)

[Claims] 1. A circuit built in a semiconductor device,
Each time the manufacturing process of the semiconductor device is revised, a power supply line electrically connected to a power supply and / or a ground line electrically connected to a ground potential supply source provided in the semiconductor device are provided. A revision information output circuit for a semiconductor device, which counts the number of times the revision is performed using a digital signal obtained by appropriately opening and closing, and outputs the counted result as a revision version information signal outside the semiconductor device. 2. The revision information output circuit for a semiconductor device according to claim 1, further comprising an output circuit for outputting a revision version information signal based on an output permission signal input from outside the circuit. 3. A mode switching signal indicating an operation mode of the semiconductor device is input from outside the circuit, and when it is determined from the mode switching signal that the semiconductor device is in an operation mode that does not use an existing input / output terminal, 2. The revision information output circuit for a semiconductor device according to claim 1, further comprising an output circuit for outputting a revision version information signal from an existing input / output terminal. 4. The revision information output circuit according to claim 1, further comprising an output circuit for sequentially outputting revision version information signals via a single input / output terminal.