JP2001332202A - Chip-on-glass fluorescent display tube - Google Patents

Chip-on-glass fluorescent display tube

Info

Publication number
JP2001332202A
JP2001332202A JP2000152534A JP2000152534A JP2001332202A JP 2001332202 A JP2001332202 A JP 2001332202A JP 2000152534 A JP2000152534 A JP 2000152534A JP 2000152534 A JP2000152534 A JP 2000152534A JP 2001332202 A JP2001332202 A JP 2001332202A
Authority
JP
Japan
Prior art keywords
substrate
semiconductor element
display tube
fluorescent display
bump
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2000152534A
Other languages
Japanese (ja)
Inventor
Hiroshi Yamaguchi
博 山口
Kazue Noguchi
和重 野口
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Futaba Corp
Original Assignee
Futaba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Futaba Corp filed Critical Futaba Corp
Priority to JP2000152534A priority Critical patent/JP2001332202A/en
Publication of JP2001332202A publication Critical patent/JP2001332202A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector

Landscapes

  • Wire Bonding (AREA)
  • Cathode-Ray Tubes And Fluorescent Screens For Display (AREA)

Abstract

PROBLEM TO BE SOLVED: To confirm the state of conductive connection between terminal portions of semiconductor elements for driving and a wiring on a substrate through observing from exterior of the substrate. SOLUTION: The COG fluorescent display tube is subjected to conductive connection in exterior of an airtight envelope 11 on a translucent substrate 1, forming a part of the airtight envelope 11 by means of anisotropic conductive materials 13, dispersed uniformly with electroconductive particles in an adhesive between wiring conductors 4 wired, by extending outward from the airtight envelope 11 and a semiconductor element 12 having a metal vamp 12a at the bottom face. Formed on the semiconductor element 12 is a dummy bump 12b, facing which frame-shaped window-cut patterns 15 are formed on the substrate 1. After connecting with the anisotropic conductive materials 13, state of conductive connection between each metal bump 12a of the semiconductor elements 12 and the wiring conductors 4 is confirmed by observing collapsed state of electroconductive particles 13b of the anisotropic conductive materials 13 through its window portion from exterior of the substrate 1.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、気密外囲器の一部
をなす透光性を有する基板上に気密外囲器内から外部に
延出して形成された配線に対して駆動用の半導体素子
(ICチップ)が気密外囲器外で導通接続されたチップ
オングラス蛍光表示管に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor for driving a wiring formed on a light-transmitting substrate forming a part of a hermetic envelope and extending from the inside of the hermetic envelope to the outside. The present invention relates to a chip-on-glass fluorescent display tube in which an element (IC chip) is electrically connected outside the hermetic envelope.

【0002】[0002]

【従来の技術】蛍光表示管において、高密度な表示が要
求される中で、蛍光表示管へ通電するための配線をでき
るだけ簡略化し、配線の引き回しを容易にするため、蛍
光表示管の外囲器の一部を構成する基板上に駆動用の半
導体素子を外囲器外で実装して配線接続するチップオン
グラス(Chip On Glass)蛍光表示管(以下、COG蛍光
表示管と略称する)と称するものが知られている。
2. Description of the Related Art As high-density display is required in a fluorescent display tube, wiring for supplying electricity to the fluorescent display tube is simplified as much as possible, and the outer periphery of the fluorescent display tube is simplified in order to facilitate wiring. A chip-on-glass (CIP) fluorescent display tube (hereinafter abbreviated as a COG fluorescent display tube) in which a driving semiconductor element is mounted on a substrate constituting a part of the device outside the envelope and connected by wiring. What is known is known.

【0003】この種のCOG蛍光表示管では、駆動回路
を納めたICチップからなる半導体素子を基板上に位置
決め配置し、この半導体素子の端子部(金属バンプ)
と、外囲器内から外部に延出して基板上に形成された配
線との間を接続する方法として、半導体素子の端子部を
基板に対向させた状態で実装するフェースダウン方式を
採用している。
In this type of COG fluorescent display tube, a semiconductor element composed of an IC chip containing a driving circuit is positioned and arranged on a substrate, and a terminal portion (metal bump) of the semiconductor element is provided.
As a method of connecting between the wiring extending from the inside of the envelope to the outside and formed on the substrate, a face-down method of mounting the semiconductor device with the terminal portion of the semiconductor element facing the substrate is adopted. I have.

【0004】このフェースダウン方式としては、導電性
接着材を用いるもの、異方性導電材を用いるもの、Au
バンプ等によるダイレクト接続するものなどが知られて
いるが、ここでは、本発明に直接関わる異方性導電材を
用いたフェースダウン方式について説明する。
As the face-down method, there are a method using a conductive adhesive, a method using an anisotropic conductive material, and a method using Au.
Although a direct connection using a bump or the like is known, a face-down method using an anisotropic conductive material directly related to the present invention will be described here.

【0005】図4は異方性導電材を用いて基板の配線と
半導体素子の端子部を接続した従来のCOG蛍光表示管
の一例を示す側断面図、図5は図4の構成における基板
の配線と半導体素子の端子部との間の接続部分の拡大図
である。
FIG. 4 is a side sectional view showing an example of a conventional COG fluorescent display tube in which the wiring of the substrate and the terminal of the semiconductor element are connected by using an anisotropic conductive material, and FIG. FIG. 3 is an enlarged view of a connection portion between a wiring and a terminal portion of a semiconductor element.

【0006】図4に示すCOG蛍光表示管は、ガラス等
の絶縁性及び透光性を有する基板1を基部としている。
基板1の内面には所定パタン形状の陽極導体2が形成さ
れ、陽極導体2上には蛍光体層3が所望パタン形状に被
着形成されている。また、図5に示すように、基板1の
内面には、陽極導体2や他の電極に通電するための配線
導体4が形成され、配線導体4を覆うように絶縁層5が
形成されている。
The COG fluorescent display tube shown in FIG. 4 is based on an insulating and translucent substrate 1 made of glass or the like.
An anode conductor 2 having a predetermined pattern is formed on the inner surface of the substrate 1, and a phosphor layer 3 is formed on the anode conductor 2 in a desired pattern. As shown in FIG. 5, a wiring conductor 4 for supplying electricity to the anode conductor 2 and other electrodes is formed on the inner surface of the substrate 1, and an insulating layer 5 is formed so as to cover the wiring conductor 4. .

【0007】図4に示すように、基板1上方には、電子
源となるフィラメント状の陰極6が張架配設されてい
る。陰極6と蛍光体層3との間には、陰極6から放出さ
れる電子を蛍光体層3に向けて加速制御する制御電極7
が設けられている。そして、上記基板1と枠状の側面板
8及び平板状の蓋板9を低融点フリットガラスなどの封
着材10を介して一体化され、気密外囲器11を有する
蛍光光表示管部分が構成される。
[0007] As shown in FIG. 4, a filament-shaped cathode 6 serving as an electron source is stretched over the substrate 1. A control electrode 7 is provided between the cathode 6 and the phosphor layer 3 for controlling acceleration of electrons emitted from the cathode 6 toward the phosphor layer 3.
Is provided. Then, the substrate 1, the frame-shaped side plate 8 and the flat cover plate 9 are integrated via a sealing material 10 such as low-melting frit glass, and a fluorescent light display tube portion having an airtight envelope 11 is formed. Be composed.

【0008】図4に示すように、前記基板1は、蛍光表
示管部分とは別体にその一部が気密外囲器11外に延長
して突出しており、半導体素子12が取り付けられる載
置部1aを形成している。載置部1aには、気密外囲器
11の内部から配線導体4が延出して形成されている。
As shown in FIG. 4, a part of the substrate 1 is protruded separately from the fluorescent display tube portion and extends outside the hermetic envelope 11, and the substrate 1 on which the semiconductor element 12 is mounted is mounted. The portion 1a is formed. The wiring conductor 4 extends from the inside of the hermetic envelope 11 on the mounting portion 1a.

【0009】配線導体4は、通常、基板1上に微小なピ
ッチで多数本配設されている場合が多く、その幅も小さ
く高い抵抗値を示すことが多い。このため、ITO(Ind
iumTin Oxide)等の高抵抗の導電材料を用いて配線導体
4を形成するのが困難であり、一般的には低抵抗のAl
膜によって配線導体4が形成されることになる。
Usually, many wiring conductors 4 are arranged on the substrate 1 at a fine pitch in many cases, and the width thereof is often small and shows a high resistance value. For this reason, ITO (Ind
It is difficult to form the wiring conductor 4 using a high-resistance conductive material such as iumTin Oxide).
The wiring conductor 4 is formed by the film.

【0010】図4及び図5に示すように、半導体素子1
2は、Au,Ag,Ni,Cu,はんだ等からなる金属
バンプ12aを有している。金属バンプ12aは、矩形
状をなす半導体素子12本体の底面部の両側に所定間隔
をおいて複数対向配設される。各金属バンプ12aは、
異方性導電材13を介して配線導体4と電気的に導通接
続される。
As shown in FIG. 4 and FIG.
2 has a metal bump 12a made of Au, Ag, Ni, Cu, solder or the like. A plurality of metal bumps 12a are arranged on both sides of the bottom surface of the semiconductor element 12 having a rectangular shape at predetermined intervals to face each other. Each metal bump 12a
It is electrically connected to the wiring conductor 4 via the anisotropic conductive material 13.

【0011】異方性導電材13は、エポキシ系等の熱硬
化性の接着材13a中に導電粒子(例えば粒径5μm程
度のAuボール)13bを均一に分散させたシート状フ
ィルムからなる。そして、基板1の配線導体4と半導体
素子12の金属バンプ12aとの間を導通接続する場合
には、シート状の異方性導電材13を基板1の配線導体
4の上に載せ、その上から半導体素子12を位置決め配
置し、半導体素子12上から熱圧着を行う。
The anisotropic conductive material 13 is a sheet-like film in which conductive particles (for example, Au balls having a particle size of about 5 μm) 13b are uniformly dispersed in a thermosetting adhesive 13a such as an epoxy resin. In the case where the wiring conductor 4 of the substrate 1 is electrically connected to the metal bump 12a of the semiconductor element 12, a sheet-shaped anisotropic conductive material 13 is placed on the wiring conductor 4 of the substrate 1, and Then, the semiconductor element 12 is positioned and arranged, and thermocompression bonding is performed from above the semiconductor element 12.

【0012】これにより、異方性導電材13は、加熱と
加圧によって接着材13aが溶融し、接着材13a中に
均一に分散された導電粒子13bが対向する配線導体4
と金属バンプ12aの間に捕捉されることにより厚さ方
向に高い導電性が得られる。また、面方向については、
導電粒子13bが互いに接触しない程度に均一に分散さ
れているとともに接着材13aが非導電材料からなるの
で、高い絶縁性が得られる。その結果、半導体素子12
の各金属バンプ12aは、機械的にも固定された状態で
対応する基板1上の配線導体4とのみ導通接続される。
As a result, the anisotropic conductive material 13 is heated and pressed to melt the adhesive 13a, and the conductive particles 13b uniformly dispersed in the adhesive 13a face the wiring conductor 4 facing the conductive material 13b.
By being trapped between the metal bumps 12a, high conductivity is obtained in the thickness direction. Also, regarding the surface direction,
Since the conductive particles 13b are uniformly dispersed to the extent that they do not contact each other and the adhesive 13a is made of a non-conductive material, high insulation properties can be obtained. As a result, the semiconductor device 12
Each metal bump 12a is electrically connected only to the corresponding wiring conductor 4 on the substrate 1 while being mechanically fixed.

【0013】ところで、上記のように、基板1の配線導
体(配線の端子部4a)4と半導体素子12の金属バン
プ(端子部)12aの接続に異方性導電材13を用いた
場合、その接着材13a中の導電粒子(Auボール)1
3bのつぶれ具合を光学顕微鏡で観察して導通状態を確
認するが、この導電粒子13bのつぶれ具合が導通状態
を確認する上で重要な要素となっている。すなわち、接
着材13a中の導電粒子13aが全くつぶれていない状
態では、半導体素子12の金属バンプ12aと基板1上
の配線導体4との間の導通が不完全となり、導通不良を
招くおそれがある。また、導電粒子13bがつぶれ過ぎ
ている場合でも、温度変化が生じた場合に導電粒子13
bが復帰しなくなり、半導体素子12の金属バンプ12
aと基板1上の配線導体4との間に導通不良を招くおそ
れがある。このため、半導体素子12の金属バンプ12
aと基板1上の配線導体4との間においては、つぶれた
導電粒子13bが数個存在する程度が好ましい。
As described above, when the anisotropic conductive material 13 is used to connect the wiring conductors (terminals 4a of the wiring) 4 of the substrate 1 and the metal bumps (terminals) 12a of the semiconductor element 12, as shown in FIG. Conductive particles (Au ball) 1 in adhesive 13a
The conduction state is confirmed by observing the degree of collapse of 3b with an optical microscope. The degree of collapse of the conductive particles 13b is an important factor in confirming the conduction state. That is, when the conductive particles 13a in the adhesive 13a are not crushed at all, conduction between the metal bumps 12a of the semiconductor element 12 and the wiring conductors 4 on the substrate 1 becomes incomplete, which may lead to poor conduction. . Further, even when the conductive particles 13b are excessively crushed, when the temperature changes, the conductive particles 13b
b does not return, and the metal bump 12
a and the wiring conductor 4 on the substrate 1 may cause poor conduction. For this reason, the metal bump 12 of the semiconductor element 12
It is preferable that several crushed conductive particles 13b are present between a and the wiring conductor 4 on the substrate 1.

【0014】[0014]

【発明が解決しようとする課題】しかしながら、上述し
た従来のCOG蛍光表示管では、コンパクトな構成で配
線が多数ある場合、ITO等の比抵抗の高い透明導電膜
を用いず、低抵抗のAl膜によって配線導体4が基板1
上に形成される。そして、配線導体4をAl膜で形成
し、この配線導体4と半導体素子12の金属バンプ12
aとの間の接続に異方性導電材13を用いるので、非透
明なAl膜による配線導体4が邪魔して基板1の外側か
ら異方性導電材13の導電粒子(Auボール)13bの
つぶれ具合を観察することができなかった。
However, in the above-mentioned conventional COG fluorescent display tube, when there are many wirings in a compact configuration, a transparent conductive film having a high specific resistance such as ITO is not used, and a low-resistance Al film is used. The wiring conductor 4 is
Formed on top. Then, the wiring conductor 4 is formed of an Al film, and the wiring conductor 4 and the metal bump 12 of the semiconductor element 12 are formed.
Since the anisotropic conductive material 13 is used for the connection between the conductive particles 13a and the conductive particles (Au balls) 13b of the anisotropic conductive material 13 from outside the substrate 1, The degree of collapse could not be observed.

【0015】このため、基板1上の配線導体4と半導体
素子12の各金属バンプ12aとの間の導通接続を確認
するには、半導体素子12の各金属バンプ12a毎に配
線導体4との間の導通検査を行うといった面倒な作業が
必要不可欠であった。
Therefore, in order to check the continuity connection between the wiring conductor 4 on the substrate 1 and each metal bump 12a of the semiconductor element 12, the connection between the wiring conductor 4 and each metal bump 12a of the semiconductor element 12 must be determined. A tedious operation such as conducting a continuity test of the device was indispensable.

【0016】そこで、本発明は、上記問題点に鑑みてな
されたものであり、駆動用の半導体素子の端子部と基板
上の配線との間の接続状態を基板の外側から観察するこ
とができ、また、接続後の合せの位置確認が容易に行
え、工程管理しやすいCOG蛍光表示管を提供すること
を目的としている。
Therefore, the present invention has been made in view of the above problems, and a connection state between a terminal portion of a driving semiconductor element and a wiring on a substrate can be observed from outside the substrate. It is another object of the present invention to provide a COG fluorescent display tube in which alignment can be easily confirmed after connection and process management is easy.

【0017】[0017]

【課題を解決するための手段】上記目的を達成するた
め、請求項1の発明は、気密外囲器の一部をなす透光性
を有する基板上に前記気密外囲器内から外部に延出して
配線された配線導体と、底面部に金属バンプを有する駆
動用の半導体素子との間が、接着材中に導電粒子が均一
に分散された異方性導電材により前記気密外囲器外で導
通接続されたチップオングラス蛍光表示管において、前
記半導体素子には該半導体素子の駆動に寄与しない金属
材料によるダミーバンプが形成されており、該ダミーバ
ンプと対向して前記基板上には金属材料による枠状の窓
抜きパタンが形成されており、前記基板の外から前記窓
抜きパタンの窓抜き部分を通して前記異方性導電材の導
電粒子のつぶれ具合が観察可能とされていることを特徴
とする。
In order to achieve the above object, the invention according to claim 1 is to extend from inside of the hermetic envelope to outside on a light-transmitting substrate forming a part of the hermetic envelope. The space between the wiring conductor that has been output and wired and the driving semiconductor element having a metal bump on the bottom surface is formed outside the hermetic envelope by an anisotropic conductive material in which conductive particles are uniformly dispersed in an adhesive. In the chip-on-glass fluorescent display tube conductively connected with the above, a dummy bump made of a metal material that does not contribute to driving of the semiconductor element is formed on the semiconductor element, and a metal bump is formed on the substrate facing the dummy bump. A frame-shaped window cutout pattern is formed, and the degree of collapse of the conductive particles of the anisotropic conductive material can be observed from outside the substrate through a window cutout portion of the window cutout pattern. .

【0018】請求項2の発明は、請求項1のCOG蛍光
表示管において、前記ダミーバンプは前記半導体素子の
底面部の四隅に形成されており、前記窓抜きパターンは
前記ダミーバンプのそれぞれに対向して前記ガラス基板
上に形成されていることを特徴とする。
According to a second aspect of the present invention, in the COG fluorescent display tube according to the first aspect, the dummy bumps are formed at four corners of a bottom portion of the semiconductor element, and the window-opening patterns face each of the dummy bumps. It is characterized by being formed on the glass substrate.

【0019】請求項3の発明は、請求項1又は2のCO
G蛍光表示管において、前記ダミーバンプは前記金属バ
ンプの外形と略同一形状に形成され、前記窓抜きパター
ンの窓抜き部分は前記ダミーバンプの外形と略同一形状
に形成されていることを特徴とする。
The third aspect of the present invention is the first aspect of the present invention,
In the G fluorescent display tube, the dummy bumps are formed to have substantially the same shape as the outer shape of the metal bumps, and the window cutout portion of the window cutout pattern is formed to have the same shape as the outer shape of the dummy bumps.

【0020】[0020]

【発明の実施の形態】図1は本発明によるCOG蛍光表
示管の実施の形態を示す側断面図、図2は図1の構成に
おける配線導体と窓抜きパタンの部分拡大平面図であ
る。
FIG. 1 is a side sectional view showing an embodiment of a COG fluorescent display tube according to the present invention, and FIG. 2 is a partially enlarged plan view of a wiring conductor and a windowed pattern in the configuration of FIG.

【0021】なお、本例のCOG蛍光表示管は、以下に
説明する構成以外は図4及び図5に示すCOG蛍光表示
管と同一構成なので、その説明を省略している。
The COG fluorescent display tube of this embodiment has the same configuration as the COG fluorescent display tube shown in FIGS. 4 and 5 except for the configuration described below, and a description thereof will be omitted.

【0022】本例のCOG蛍光表示管において、半導体
素子12の底面部には、図1に示すように、金属バンプ
12aとは別に、半導体素子12の駆動に寄与しないダ
ミーバンプ12bが設けられている。ダミーバンプ12
bは、半導体素子12の底面部に対し、金属バンプ12
aの配列に平行して金属バンプ12aの外側に設けられ
る。ダミーバンプ12bは、金属バンプ12aの外形と
略同一形状(例えば50×80μm、100×100μ
mの矩形状)で形成されるのが好ましい。このダミーバ
ンプ12bは、半導体素子12の底面部の少なくとも1
箇所に設けられる。但し、基板1の配線導体4と半導体
素子12の各金属バンプ12aとの間の導通接続状態を
より確実にモニタする場合には、半導体素子12の底面
部の四隅、好ましくは両側に所定ピッチで配置される複
数の金属バンプ12aの配列に平行して半導体素子12
の底面部の四隅に上記ダミーバンプ12bを設ける。
In the COG fluorescent display tube of the present embodiment, as shown in FIG. 1, a dummy bump 12b which does not contribute to driving of the semiconductor element 12 is provided on the bottom of the semiconductor element 12, as shown in FIG. . Dummy bump 12
b indicates that the metal bump 12
It is provided outside the metal bumps 12a in parallel with the arrangement of "a". The dummy bump 12b has substantially the same shape as the outer shape of the metal bump 12a (for example, 50 × 80 μm, 100 × 100 μm).
m). The dummy bumps 12b are formed on at least one of the bottom surfaces of the semiconductor element 12.
Provided at the location. However, in order to more reliably monitor the conductive connection state between the wiring conductor 4 of the substrate 1 and each of the metal bumps 12a of the semiconductor element 12, four corners of the bottom surface of the semiconductor element 12, preferably at both sides, at a predetermined pitch. The semiconductor element 12 is arranged in parallel with the arrangement of the plurality of metal bumps 12a to be arranged.
The dummy bumps 12b are provided at the four corners of the bottom surface of the dummy bump 12b.

【0023】基板1上には、ダミーバンプ12bと対向
して金属材料からなる枠状の窓抜きパタン15が形成さ
れている。なお、ダミーバンプ12bが半導体素子12
の底面部の四隅に設けられた場合には、各ダミーバンプ
12bに対向して基板1上に窓抜きパタン15が形成さ
れる。窓抜きパタン15の窓抜き部分は、ダミーバンプ
12bの表面の外形(端子部に相当する半導体素子12
の金属バンプ12aの表面の外形)と略同一形状に形成
されるのが好ましい。また、窓抜きパタン15は、基板
1上の配線導体4と同一金属材料により同じ工程で形成
するのが好ましい。例えば厚さ1.0μm程度のAl薄
膜で枠状に窓抜きパタン15を配線導体4と同時に形成
することができる。
On the substrate 1, a frame-shaped window opening pattern 15 made of a metal material is formed so as to face the dummy bump 12b. Note that the dummy bumps 12b are
In the case of being provided at the four corners of the bottom surface of the above, a window opening pattern 15 is formed on the substrate 1 so as to face each dummy bump 12b. The window opening portion of the window opening pattern 15 corresponds to the outer shape of the surface of the dummy bump 12b (the semiconductor element 12 corresponding to the terminal portion).
Of the metal bump 12a). Further, it is preferable that the window opening pattern 15 is formed in the same step with the same metal material as the wiring conductor 4 on the substrate 1. For example, the window opening pattern 15 can be formed simultaneously with the wiring conductor 4 in a frame shape with an Al thin film having a thickness of about 1.0 μm.

【0024】そして、上記構成によるCOG蛍光表示管
が完成されると、半導体素子12の各金属バンプ12a
と、各金属バンプ12aと対応する基板1の配線導体4
との間の導通状態が観察される。この導通状態は、透光
性を有する基板1の外から窓抜きパタン15内に見える
異方性導電材13の接着材13a中に分散される導電粒
子(Auボール)13bを観察し、この導電粒子13b
のつぶれ具合から導通接続状態の良否を判断する。
When the COG fluorescent display tube having the above structure is completed, each metal bump 12a of the semiconductor element 12 is formed.
And the wiring conductor 4 of the substrate 1 corresponding to each metal bump 12a
Is observed. This conductive state is observed by observing conductive particles (Au balls) 13b dispersed in the adhesive 13a of the anisotropic conductive material 13 which can be seen in the window opening pattern 15 from the outside of the substrate 1 having translucency. Particle 13b
Is determined based on the degree of collapse.

【0025】このように、本例のCOG蛍光表示管によ
れば、半導体素子12の駆動に寄与しないダミーバンプ
12bを半導体素子12の底面部に設け、このダミーバ
ンプ12bに対向して透光性を有する基板1上に窓抜き
パタン15を形成した構成なので、基板1の外から窓抜
きパタン15の窓抜き部分を光学顕微鏡で覗くことによ
り、異方性導電材13の接着材13a中に均一に分散さ
れる導電粒子(Auボール)13bのつぶれ具合を観察
することができる。
As described above, according to the COG fluorescent display tube of this embodiment, the dummy bumps 12b which do not contribute to the driving of the semiconductor element 12 are provided on the bottom surface of the semiconductor element 12, and have a light-transmitting property facing the dummy bumps 12b. Since the window opening pattern 15 is formed on the substrate 1, the window opening portion of the window opening pattern 15 can be uniformly dispersed in the adhesive 13 a of the anisotropic conductive material 13 by looking through the window opening portion of the window opening pattern 15 from outside the substrate 1 with an optical microscope. The degree of crushing of the conductive particles (Au ball) 13b to be performed can be observed.

【0026】また、上記ダミーバンプ12bと金属バン
プ12aの外形と略同一形状とし、窓抜きパタン15を
ダミーバンプ12bの表面の外形と略同一形状とすれ
ば、ダミーバンプ12bと窓抜きパタン15の間は、金
属バンプ12aと配線導体4の間と略同等の条件で異方
性導電材により圧着されるので、窓抜きパタン15の窓
抜き部分に見える異方性導電材13の導電粒子13bの
つぶれ具合を代表して観察することにより、半導体素子
12の各金属バンプ12aと基板1の配線導体4との間
の導通接続状態を確認することができる。
When the dummy bumps 12b and the metal bumps 12a have substantially the same shape as the outer shapes of the dummy bumps 12b and the window bumps 15b, the outer shape of the dummy bumps 12b is substantially the same as the outer shape of the dummy bumps 12b. Since the pressure is applied by the anisotropic conductive material under substantially the same conditions as between the metal bumps 12a and the wiring conductors 4, the conductive particles 13b of the anisotropic conductive material 13 visible in the window opening portion of the window opening pattern 15 are crushed. By conducting the representative observation, it is possible to confirm the conductive connection state between each metal bump 12a of the semiconductor element 12 and the wiring conductor 4 of the substrate 1.

【0027】さらに、上記構成に加え、半導体素子12
の金属バンプ12aを囲むように半導体素子12の底面
部の四隅にダミーバンプ12bを設け、これらダミーバ
ンプ12bに対向して基板1上に窓抜きパタン15を形
成する構成とすれば、基板1に対して半導体素子12が
傾いて取り付けられた場合でも、半導体素子12の全て
の金属バンプ12aの配線導体4に対する導通接続状態
を4つの窓抜きパタン15の窓抜き部分から異方性導電
材13の導電粒子13bのつぶれ具合を観察することで
確認することができる。しかも、ダミーバンプ12bと
窓抜きパタン15が金属バンプ12aの外形と略同一形
状なので、各ダミーバンプ12bの外形が各窓抜きパタ
ン15の外形と一致するように半導体素子12を基板1
上に位置決めすることにより、半導体素子12を基板1
上の正確な位置に位置合せすることができる。また、異
方性導電材13を用いた接続後に、基板1の配線導体4
と半導体素子12の各金属バンプ12aとの間が正しい
位置で接続されたか否かの確認を行うことができる。そ
して、上記のように、異方性導電材13の導電粒子13
bのつぶれ具合を基板1の外から窓抜きパタン15の窓
抜き部分を通してモニタできるので、工程管理しやすい
というメリットもある。
Further, in addition to the above configuration, the semiconductor device 12
Dummy bumps 12b are provided at the four corners of the bottom surface of the semiconductor element 12 so as to surround the metal bumps 12a, and a window pattern 15 is formed on the substrate 1 so as to face the dummy bumps 12b. Even when the semiconductor element 12 is mounted obliquely, the conductive connection state of all the metal bumps 12a of the semiconductor element 12 to the wiring conductor 4 is changed from the windowed portions of the four windowed patterns 15 to the conductive particles of the anisotropic conductive material 13. It can be confirmed by observing the degree of collapse of 13b. Moreover, since the dummy bumps 12b and the window-forming patterns 15 have substantially the same shape as the outer shape of the metal bumps 12a, the semiconductor element 12 is mounted on the substrate 1 so that the outer shape of each dummy bump 12b matches the outer shape of each of the window-opening patterns 15.
The semiconductor element 12 is positioned above the substrate 1.
It can be aligned to the exact position above. After the connection using the anisotropic conductive material 13, the wiring conductor 4
It can be confirmed whether or not the connection between the semiconductor device 12 and each metal bump 12a is made at a correct position. Then, as described above, the conductive particles 13 of the anisotropic conductive material 13
Since the degree of collapse of b can be monitored from the outside of the substrate 1 through the window opening portion of the window opening pattern 15, there is also an advantage that process control is easy.

【0028】ところで、上記のように構成されるCOG
蛍光表示管では、半導体素子12の実装前に基板1上に
形成された各配線導体4の導通検査が行われる。この導
通検査は、金属バンプ12a直下の配線導体4の端子部
4aに検査ピンを当てることにより行われるので、半導
体素子12の金属バンプ12aと導通接続される配線導
体4の端子部4aが検査ピンによって傷付けられたり、
削られたりして接続不良を発生させるおそれがある。
By the way, the COG constructed as described above
In the fluorescent display tube, a continuity test of each wiring conductor 4 formed on the substrate 1 is performed before the semiconductor element 12 is mounted. This continuity test is performed by applying a test pin to the terminal portion 4a of the wiring conductor 4 immediately below the metal bump 12a, so that the terminal portion 4a of the wiring conductor 4 conductively connected to the metal bump 12a of the semiconductor element 12 is connected to the test pin. Being hurt by
There is a possibility that a connection failure may occur due to chipping.

【0029】そこで、本例のCOG蛍光表示管では、各
配線導体4毎に検査用端子部4bが一体形成されてい
る。具体的には、図3に示すように、検査用端子部4b
は、半導体素子12の各金属バンプ12aと対向する各
配線導体4の端子部4aの先端から半導体素子12の内
側方向に延出して一体に導出形成される。なお、検査用
端子部4bは、検査ピンが接触して検査が行える程度の
面積を有していればよく、その形状は問わない。
Therefore, in the COG fluorescent display tube of the present embodiment, the inspection terminal portion 4b is integrally formed for each wiring conductor 4. Specifically, as shown in FIG.
Are extended inwardly of the semiconductor element 12 from the front ends of the terminal portions 4a of the wiring conductors 4 facing the metal bumps 12a of the semiconductor element 12, and are integrally formed. Note that the inspection terminal portion 4b only needs to have an area large enough to allow inspection by contact with the inspection pin, and its shape is not limited.

【0030】そして、半導体素子12の実装前の検査工
程で各配線導体4の検査を行う場合には、各配線導体4
の検査用端子部4bに検査ピンを当てて検査を行う。こ
れにより、半導体素子12の金属バンプ12aと異方性
導電材13を介して導通接続される各配線導体4の端子
部4aの表面を検査ピンにより傷付けることもなく、配
線導体4の端子部4aの表面を平滑面に保つことがで
き、各配線導体4の接続不良を無くすことができる。
When the inspection of each wiring conductor 4 is performed in the inspection step before the mounting of the semiconductor element 12, each wiring conductor 4
The inspection is performed by applying an inspection pin to the inspection terminal portion 4b. Thus, the surface of the terminal portion 4a of each wiring conductor 4 electrically connected to the metal bump 12a of the semiconductor element 12 via the anisotropic conductive material 13 is not damaged by the inspection pin, and the terminal portion 4a of the wiring conductor 4 is not damaged. Can be kept smooth, and connection failure of each wiring conductor 4 can be eliminated.

【0031】[0031]

【発明の効果】以上の説明で明らかなように、本発明の
COG蛍光表示管は、ダミーバンプを半導体素子の底面
部に設け、このダミーバンプに対向して透光性を有する
基板上に窓抜きパタンを形成した構成なので、基板の外
から窓抜きパタンの窓抜き部分を光学顕微鏡で覗き、異
方性導電材の接着材中に均一に分散される導電粒子のつ
ぶれ具合を観察することにより、半導体素子の各金属バ
ンプと基板の配線導体との間の導通接続状態を確認する
ことができる。
As is apparent from the above description, in the COG fluorescent display tube of the present invention, a dummy bump is provided on the bottom of a semiconductor element, and a window opening pattern is formed on a light-transmitting substrate facing the dummy bump. Because of the configuration, the semiconductor device is observed from the outside of the substrate by observing the window opening portion of the window opening pattern with an optical microscope and observing the degree of collapse of the conductive particles uniformly dispersed in the adhesive of the anisotropic conductive material. The conductive connection state between each metal bump of the element and the wiring conductor of the substrate can be confirmed.

【0032】ダミーバンプと金属バンプの外形を略同一
形状とし、窓抜きパタンをダミーバンプの表面の外形と
略同一形状に形成すれば、ダミーバンプと窓抜きパタン
の間は、金属バンプと配線導体の間と略同等の条件で異
方性導電材により圧着されるので、窓抜きパタンの窓抜
き部分に見える異方性導電材の導電粒子のつぶれ具合を
代表して観察することにより、半導体素子の各金属バン
プと基板の配線導体との間の導通接続状態を確認するこ
とができる。
If the dummy bumps and the metal bumps have substantially the same outer shape and the window cutout pattern is formed to have substantially the same shape as the outer shape of the surface of the dummy bumps, the space between the dummy bump and the window cutout is the same as that between the metal bump and the wiring conductor. Since it is compressed by the anisotropic conductive material under substantially the same conditions, by observing the degree of crushing of the conductive particles of the anisotropic conductive material which can be seen in the window opening portion of the window opening pattern, each metal of the semiconductor element can be observed. The conductive connection state between the bump and the wiring conductor of the substrate can be confirmed.

【0033】上記構成に加え、半導体素子の金属バンプ
を囲むように半導体素子の底面部の四隅にダミーバンプ
を設け、これらダミーバンプに対向して基板上に窓抜き
パタンを形成する構成とすれば、半導体素子の全ての金
属バンプの配線導体に対する導通接続状態を4つの窓抜
きパタンの窓抜き部分から異方性導電材の導電粒子のつ
ぶれ具合を観察して確認することができる。しかも、ダ
ミーバンプと窓抜きパタンが金属バンプの外形と略同一
形状なので、各ダミーバンプの外形が各窓抜きパタンの
外形と一致するように半導体素子を基板上に配置するこ
とにより、半導体素子を基板上の正確な位置に位置合せ
することができる。また、異方性導電材を用いた接続後
に、基板の配線導体と半導体素子の各金属バンプとの間
が正しい位置で接続されたか否かの確認を行うことがで
きる。そして、上記のように、異方性導電材の導電粒子
のつぶれ具合を基板の外から窓抜きパタンを通してモニ
タできるので、工程管理しやすいというメリットもあ
る。
In addition to the above structure, if dummy bumps are provided at four corners of the bottom surface of the semiconductor element so as to surround the metal bumps of the semiconductor element, and a window pattern is formed on the substrate so as to face these dummy bumps, The conductive connection state of all the metal bumps of the element to the wiring conductor can be confirmed by observing the degree of collapse of the conductive particles of the anisotropic conductive material from the windowed portions of the four windowed patterns. In addition, since the dummy bumps and the window-opening pattern have substantially the same shape as the outer shape of the metal bumps, the semiconductor elements are arranged on the substrate such that the outer shape of each dummy bump matches the outer shape of each window-out pattern. Can be aligned to the exact position of Further, after the connection using the anisotropic conductive material, it is possible to confirm whether or not the connection between the wiring conductor of the substrate and each metal bump of the semiconductor element is made at a correct position. Further, as described above, the degree of crushing of the conductive particles of the anisotropic conductive material can be monitored from the outside of the substrate through the window opening pattern.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明によるCOG蛍光表示管の実施の形態を
示す側断面図
FIG. 1 is a side sectional view showing an embodiment of a COG fluorescent display tube according to the present invention.

【図2】図1の構成における配線導体と窓抜きパタンの
部分拡大平面図
FIG. 2 is a partially enlarged plan view of a wiring conductor and a windowless pattern in the configuration of FIG. 1;

【図3】本発明によるCOG蛍光表示管の他の実施の形
態を示す側断面図
FIG. 3 is a side sectional view showing another embodiment of the COG fluorescent display tube according to the present invention.

【図4】異方性導電材を用いて基板の配線と半導体素子
の端子部を接続した従来のCOG蛍光表示管の一例を示
す側断面図
FIG. 4 is a side sectional view showing an example of a conventional COG fluorescent display tube in which wiring of a substrate and terminal portions of a semiconductor element are connected using an anisotropic conductive material.

【図5】図4の構成における基板の配線と半導体素子の
端子部との間の接続部分の拡大図
5 is an enlarged view of a connection portion between a wiring on a substrate and a terminal portion of a semiconductor element in the configuration of FIG. 4;

【符号の説明】[Explanation of symbols]

1…基板、4…配線導体、4a…端子部、4b…検査用
端子部、11…気密外囲器、12…半導体素子、12a
…金属バンプ(端子部)、12b…ダミーバンプ、13
…異方性導電材、13a…接着材、13b…導電粒子、
15…窓抜きパタン。
DESCRIPTION OF SYMBOLS 1 ... Substrate, 4 ... Wiring conductor, 4a ... Terminal part, 4b ... Inspection terminal part, 11 ... Hermetic enclosure, 12 ... Semiconductor element, 12a
... metal bumps (terminals), 12b ... dummy bumps, 13
... anisotropic conductive material, 13a ... adhesive, 13b ... conductive particles,
15 ... Pattern without window.

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】 気密外囲器の一部をなす透光性を有する
基板上に前記気密外囲器内から外部に延出して配線され
た配線導体と、底面部に金属バンプを有する駆動用の半
導体素子との間が、接着材中に導電粒子が均一に分散さ
れた異方性導電材により前記気密外囲器外で導通接続さ
れたチップオングラス蛍光表示管において、 前記半導体素子には該半導体素子の駆動に寄与しない金
属材料によるダミーバンプが形成されており、該ダミー
バンプと対向して前記基板上には金属材料による枠状の
窓抜きパタンが形成されており、 前記基板の外から前記窓抜きパタンの窓抜き部分を通し
て前記異方性導電材の導電粒子のつぶれ具合が観察可能
とされていることを特徴とするチップオングラス蛍光表
示管。
1. A driving device having a wiring conductor extending from the inside of the hermetic envelope to the outside and wired on a light-transmitting substrate forming a part of the hermetic envelope, and a metal bump on a bottom surface portion. A chip-on-glass fluorescent display tube electrically connected between the semiconductor element and the outside of the hermetic envelope by an anisotropic conductive material in which conductive particles are uniformly dispersed in an adhesive material; A dummy bump made of a metal material that does not contribute to driving of the semiconductor element is formed, and a frame-shaped window-opening pattern made of a metal material is formed on the substrate facing the dummy bump. A chip-on-glass fluorescent display tube, wherein the degree of crushing of the conductive particles of the anisotropic conductive material can be observed through a window portion of the window pattern.
【請求項2】 前記ダミーバンプは前記半導体素子の底
面部の四隅に形成されており、前記窓抜きパターンは前
記ダミーバンプのそれぞれに対向して前記ガラス基板上
に形成されていることを特徴とする請求項1記載のチッ
プオングラス蛍光表示管。
2. The semiconductor device according to claim 1, wherein the dummy bumps are formed at four corners of a bottom surface of the semiconductor element, and the window-opening pattern is formed on the glass substrate so as to face each of the dummy bumps. Item 7. A chip-on-glass fluorescent display tube according to item 1.
【請求項3】 前記ダミーバンプは前記金属バンプの外
形と略同一形状に形成され、前記窓抜きパターンの窓抜
き部分は前記ダミーバンプの外形と略同一形状に形成さ
れていることを特徴とする請求項1又は2記載のチップ
オングラス蛍光表示管。
3. The dummy bump is formed to have substantially the same shape as the outer shape of the metal bump, and the window cutout portion of the window cutout pattern is formed to have substantially the same shape as the outer shape of the dummy bump. 3. The chip-on-glass fluorescent display tube according to 1 or 2.
JP2000152534A 2000-05-24 2000-05-24 Chip-on-glass fluorescent display tube Pending JP2001332202A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2000152534A JP2001332202A (en) 2000-05-24 2000-05-24 Chip-on-glass fluorescent display tube

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2000152534A JP2001332202A (en) 2000-05-24 2000-05-24 Chip-on-glass fluorescent display tube

Publications (1)

Publication Number Publication Date
JP2001332202A true JP2001332202A (en) 2001-11-30

Family

ID=18657949

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2000152534A Pending JP2001332202A (en) 2000-05-24 2000-05-24 Chip-on-glass fluorescent display tube

Country Status (1)

Country Link
JP (1) JP2001332202A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2019168293A (en) * 2018-03-22 2019-10-03 芝浦メカトロニクス株式会社 Inspection device and inspection method

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2019168293A (en) * 2018-03-22 2019-10-03 芝浦メカトロニクス株式会社 Inspection device and inspection method
JP7012575B2 (en) 2018-03-22 2022-01-28 芝浦メカトロニクス株式会社 Inspection equipment and inspection method

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A02 Decision of refusal

Effective date: 20040309

Free format text: JAPANESE INTERMEDIATE CODE: A02