JP2001331546A - Output load verifying device, output load verification method for hardware marco, and recording medium with recorded thereon output load verifying program - Google Patents

Abstract

PROBLEM TO BE SOLVED: To secure logic simulation precision by previously detecting a decrease in delay verification information due to an increase in delay due to waveform rounding and malfunction of a hardware macro under the influence of an output load when an output signal is fed back to the inside of the hardware macro itself. SOLUTION: Through maximum load capacity calculation processing 21 based upon waveform rounding, a 1st maximum load capacity value Cmax is calculated from a predetermined limit waveform rounding degree Wc and through maximum load capacity calculation processing 22 based upon feedback delay, a 2nd maximum load capacity value CDmax is calculated from a permissible output delay time To where malfunction due to the delay of a feedback signal is not caused. Through output load verification processing 23 for the waveform rounding, the load capacity Cl of an output part of the hardware macro is extracted and when it is larger than Cmax, an error is decided. Through output load verification processing 24 for feedback delay, an error is decided when it is larger than the output CDmax.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an output load verification device and a method for verifying an output load of a hard macro.
The present invention relates to an output load verification device, an output load verification method for a hard macro, and a recording medium on which an output load verification program is recorded in advance to ensure the accuracy of a logic / delay simulation executed after layout of an LSI.

[0002]

2. Description of the Related Art In recent LSI design, a layout-designed macro cell called a hard macro is used as a method for avoiding the complexity of the design due to the enlargement of the LSI and the diversification of functions, and the prolongation of the design period. The method of designing by utilizing is widely adopted. At the same time, with the speeding up of the LSI, it is needless to say that the delay accuracy must be improved in the logic / delay verification after the layout, and that the hard macro also needs to have the improved delay accuracy.

However, in a hard macro,
If the output unit has a fixed load driving force, and there are a large number of logic cells driven by the output unit, or if the wiring to be driven is long, in addition to the delay value obtained from the delay characteristics registered in the macro cell library, The rising edge of the output waveform,
The first problem is that the accuracy of the delay verification is reduced because an increase in the delay is caused by the falling edge.

FIG. 8 is an explanatory diagram of a first conventional example for preventing a decrease in delay accuracy due to waveform dulling. Referring to the flow chart of the first conventional example in FIG.
After completion of Step 1, the layout data is stored in the layout data file 3.

On the other hand, as shown in FIG. 8B, a critical output delay time Tc which is a critical value which increases in advance from a range in which the output delay time is out of a range proportional to the waveform dullness due to the output load capacitance, and a corresponding value. A critical waveform dullness Wc indicating the waveform dullness is obtained in advance. In a macro cell designed under the same design rule, the critical waveform dullness Wc
Can be regarded as a constant value irrespective of the function of the macro cell in practical use. Therefore, in the maximum load capacity calculation processing 82 based on waveform blunting, the output drive characteristic of the output part of the hard macro, that is, the output waveform blunting characteristic with respect to the load capacity, An output load capacitance value at which the waveform dullness reaches a predetermined limit waveform dullness degree Wc is calculated, and registered in the macro cell library 4 as a maximum output load capacitance Cmax that can guarantee delay accuracy.

After the layout design 81 is completed, in the output load verification processing 83, the load capacity of the output terminal of each hard macro is calculated based on the layout data file 3 and the circuit data file 2, and the maximum output load capacity C is calculated.
max. If the load capacitance of the output terminal of the hard macro is smaller than Cmax, the flow proceeds to the next logic simulation 84 after layout design to verify the delay and logic.
If it is larger than max, an error is determined on the assumption that delay accuracy in the logic simulation 84 after layout design cannot be guaranteed.

In the first conventional example, if the load capacity cannot guarantee the delay accuracy, it can be detected. However, it is determined whether the hard macro exceeds the output load capacity for guaranteeing the delay accuracy between cells. Just verify. When the output signal of the hard macro is configured to feed back to the inside of the hard macro itself, the output load capacitance value becomes Cm.
Even if it is equal to or less than ax, the hard macro itself may malfunction due to the effect of the load connected to the output terminal of the hard macro, but this has not been detected.

FIG. 9 shows a second embodiment for solving this second problem.
It is a block diagram of the conventional example of FIG. In the second conventional example, the output latch circuit 9 including the output section of the original hard macro 90 is provided.
A buffer 94 having a sufficient driving force with respect to the load capacity is inserted in advance between the output terminal 1 and the output terminal 92 to form a hard macro 95 to which a buffer is added. As a result, the wiring from the output latch 91 to the feedback input circuit 93 is disconnected from the output terminal 92, so that malfunction of the hard macro due to the influence of the load capacitance of the output terminal 92 can be prevented.

However, since the hard macro including the buffer 94 is used, the internal delay of the hard macro itself increases, which is a factor that limits the operation speed of the LSI. That is, in the second conventional example, even if the output load capacity is such that the original hard macro 90 is directly driven and no malfunction occurs, and the hard macro 90 operates faster when driven directly, The third problem is that the use of the hard macro 95 with the addition of a buffer causes a loss of design freedom for high-speed operation by adding a structural constraint of adding a buffer.

[0010]

As described above,
The first problem is that the delay verification accuracy is reduced due to an increase in delay due to waveform dulling. In the case of a circuit in which an output signal is fed back to the inside of the hard macro itself, the load connected to the output terminal of the hard macro is reduced. In contrast to the second problem that the hard macro itself may malfunction due to the influence, the first conventional example solves the first problem but cannot solve the second problem. The conventional example solves the first and second problems. However, a third problem arises in that the design freedom for high-speed operation is lost by adding a structural constraint to the hard macro.

An object of the present invention is to provide an output load verification device and a hardware macro output load verification method that can satisfy all of the first, second, and third problems.

[0012]

According to a first aspect of the present invention, there is provided an output load verifying apparatus for determining a first maximum load capacity value from an output drive characteristic of an output unit and a predetermined limit waveform dullness for a hard macro. Means for calculating maximum load capacity based on the calculated waveform bluntness, and when the hard macro has an output / feedback input terminal, from the start of output in an output latch circuit for defining output timing to an output section and the output / feedback input terminal Calculating an allowable output delay time, which is a maximum value allowed from the maximum operating frequency of the LSI in an output delay time until an output signal input via the circuit reaches the circuit threshold of the feedback input circuit, and calculates the allowable output delay time and A maximum load capacity calculating means based on a feedback delay for calculating a second maximum load capacity value based on an output drive characteristic of the output unit; By comparing the circuit data and the layout data, a capacitance element serving as a load of the output unit of the hard macro is extracted to calculate an output load capacitance value, and the output load capacitance value is the first maximum load capacitance value or the second maximum load capacitance value. And output load verification means for determining an error when the load capacity value is larger than the maximum load capacity value.

According to a second aspect of the present invention, there is provided a method for verifying an output load of a hard macro, comprising: calculating a first maximum load capacitance value from an output drive characteristic of an output unit and a predetermined limit waveform dullness for a hard macro; Maximum load capacity calculation processing based on waveform dullness to be registered, and when the hard macro has an output / feedback input terminal, from the start of output in an output latch circuit that defines output timing to an output section and the output / feedback input terminal. Calculating an allowable output delay time, which is a maximum value allowed from the maximum operating frequency of the LSI in an output delay time until an output signal input via the circuit reaches the circuit threshold of the feedback input circuit, and calculates the allowable output delay time and A second maximum load capacitance value is calculated based on the output drive characteristics of the output unit and stored in the macro cell library. The maximum load capacity calculation process based on the feedback delay to record, LS from the circuit data file
Reading out the circuit data of I, reading out the layout data of the LSI from the layout data file, comparing the both, extracting the capacitance element which becomes the load of the output section of the hard macro, calculating the output load capacitance value, and calculating the first maximum value. A hard macro having the output / feedback input terminal and an output load verification process for waveform blunting which determines an error when the output load capacitance value is larger than the first maximum load capacitance value, as compared with a load capacitance value. An output load verification process for a feedback delay extracted and determined to be an error when the output load capacitance value is larger than the second maximum load capacitance value.

According to a third aspect of the present invention, there is provided an output load verifying device for calculating a first maximum load capacitance value from a drive drive characteristic of an output unit and a predetermined limit waveform dullness for a hard macro. Calculating means, and when the hard macro has an output / feedback input terminal, an output signal to be input via an output unit and the output / feedback input terminal from the start of output in an output latch circuit that defines output timing. In the output delay time until the feedback input circuit reaches the circuit threshold, an allowable output delay time, which is the maximum value allowed from the maximum operating frequency of the LSI, is calculated based on the allowable output delay time and the output drive characteristics of the output unit. Means for calculating a maximum load capacity based on a feedback delay for calculating a second maximum load capacity value, and the first maximum load capacity Library load maximum load capacitance selecting means for comparing the maximum load capacitance value with the second maximum load capacitance value and selecting a smaller capacitance value as a registered capacitance value in the macro cell library; Output load verification means for extracting a capacitance element serving as a load on the output unit of the macro, calculating an output load capacitance value, and determining an error when the output load capacitance value is larger than the registered capacitance value.

According to a fourth aspect of the present invention, there is provided a method for verifying an output load of a hard macro, comprising calculating a first maximum load capacitance value from an output drive characteristic of an output section of the hard macro and a predetermined limit waveform dullness and registering the value in a macro cell library. The maximum load capacity calculation processing based on the waveform dulling, and when the hard macro has an output / feedback input terminal, the output unit and the output / feedback input terminal are started from the output start in the output latch circuit that defines the output timing. Calculating an allowable output delay time, which is a maximum value allowed from the maximum operating frequency of the LSI, in an output delay time until an output signal input via the output input circuit reaches a circuit threshold value of the feedback input circuit; A second maximum load capacitance value is calculated based on the output drive characteristics of the section and registered in the macro cell library. A maximum load capacity calculation process based on a feedback delay to be performed, and a library that compares the first maximum load capacity value with the second maximum load capacity value and selects a smaller capacity value as a registered capacity value in the macro cell library. The maximum load capacity selection process for registration, reading the circuit data of the LSI from the circuit data file, extracting the capacity element serving as the load of the output part of the hard macro from the layout data file, calculating the output load capacity value, An output load verification process for comparing with a maximum load capacity value and determining an error when the output load capacity value is larger than the registered capacity value.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS According to the present invention, a hard macro having a circuit configuration in which an output signal for propagating from a hard macro internal circuit to the outside is output to the outside through an output terminal and at the same time is fed back to the inside of the hard macro. The maximum load capacitance value based on the feedback delay, which is the upper limit output load capacitance value at which the hard macro normally operates without being affected by the load connected to the output terminal, is calculated in advance. After the layout, the output load capacitance of the hard macro is extracted, and in addition to the comparison test with the maximum load capacitance value based on the waveform bluntness similar to the first conventional example, the comparison test with the maximum load capacitance value based on the feedback delay is performed. I do. As a result, the operation can be guaranteed even in a hard macro having a circuit configuration in which an output signal is fed back to an internal circuit.

FIG. 1 is a configuration diagram of an entire system including an output load verification device according to an embodiment of the present invention. The system is used for an output load verification device 1, a circuit data file 2 storing circuit connection data of a verification target LSI, a layout data file 3 storing layout data of a verification target LSI, and a verification target LSI. Macro cell library 4 in which library data such as internal circuits, delay characteristics, and cell outlines are registered, and an input / output display device through which a designer controls an output load verification device and displays execution results. And 5.

The output load verification device 1 includes a maximum load capacity calculation unit 11 based on waveform blunting, a maximum load capacity calculation unit 12 based on feedback delay, and an output load verification unit 1.
3 is provided.

Maximum load capacity calculating means 1 based on waveform dulling
1 calculates a first maximum load capacitance value Cmax based on waveform blunting from a hard macro included in an LSI to be verified, based on an output drive characteristic of an output unit thereof and a predetermined limit waveform blunting degree Wc. Register with.

When the hard macro has an output / feedback input terminal, the maximum load capacity calculation means 12 outputs the output section and the output / feedback input terminal from the start of output in the output latch circuit which defines the output timing. Is calculated from the maximum operating frequency F of the LSI in the output delay time until the output signal input via the circuit reaches the circuit threshold of the feedback input circuit, and the allowable output delay time is calculated. Based on To and the output drive characteristics of the output unit, a second maximum load capacitance value CDmax based on the feedback delay is calculated and registered in the macro cell library 4.

The output load verifying means 13 outputs the circuit connection data of the circuit data file 2 and the layout data file 3
, The output load capacitance value Cl is calculated by extracting a capacitance element serving as a load of the output unit of the hard macro, and the output load capacitance value Cl is set to the first maximum load capacitance value C.
When it is larger than max or the second maximum load capacity value CDmax, an error is determined and an error message is displayed on the input / output display device 5.

FIG. 2 is a flow chart of the output load verification of the hard macro by the output load verification device 1. The output load verification device 1 does not necessarily need to be a dedicated device, and may be configured by a general-purpose computer and a program that executes the processing of FIG.

The output load verification flow of FIG. 2 will be described with reference to FIG. 5A which is a schematic block diagram of a hard macro.

First, in the maximum load capacity calculation process 21 based on waveform blunting, the terminal 52
The first maximum load capacitance value Cmax based on the waveform blunt delay is calculated from the output drive characteristics of the output unit that drives the output load connected to and the predetermined limit waveform bluntness Wc, and registered in the macro cell library 4.

Next, in the maximum load capacity calculation processing 22 based on the feedback delay, the terminal 52 of the hard macro
Is an output / feedback input terminal, the output signal input from the output section and the output / feedback input terminal 52 through the output section and the output / feedback input terminal 52 from the start of output in the output latch circuit 51 for defining the output timing.
LS in the output delay time until the circuit threshold of 3 is reached
An allowable output delay time To which is an allowable maximum value is calculated from the maximum operating frequency of I, and a second maximum load capacitance value CDmax based on the feedback delay based on the allowable output delay time To and the output drive characteristics of the output unit. Is calculated and registered in the macro cell library 4.

In FIG. 5A, the output of the output latch circuit 51 is directly connected to the output / feedback input terminal 52 for simplification of the drawing. When the circuit 51 and the output circuit as an output unit for driving the output load are provided separately, the maximum load capacity calculation processing 21 based on the waveform dullness and the maximum load capacity calculation processing 22 based on the feedback delay require the output The output drive characteristics of the output circuit may be used as the output drive characteristics of the unit.

Next, in an output load verification process 23 for waveform dulling, the circuit connection data of the LSI is read from the circuit data file 2 and the layout data is read from the layout data file 3. The output load capacitance Cl of the terminal 52 is calculated and compared with the first maximum load capacitance Cmax, and the output load capacitance is extracted. An error is determined when the value Cl is greater than the first maximum load capacity value Cmax.

Next, in an output load verification process 24 for feedback delay, a hard macro having an output / feedback input terminal is extracted, and an output load capacitance Cl
Is larger than the second maximum load capacitance value CDmax, an error is determined.

Output load verification processing 23 for waveform dullness and output load verification processing 24 for feedback delay
If there is no hard macro for which an error is determined in the above, it is determined that there is no problem in the delay accuracy and no malfunction due to the feedback delay occurs, and the next verification is performed in the same manner as in FIG. Since the logic / delay simulation, which is a process, is executed, it is apparent that the first and second problems of the prior art are solved. Further, when there is no error determination, a buffer circuit or the like that generates an extra delay unlike the second conventional example is not added, so that the third problem is also solved.

If an error is determined in any of the processes, a buffer having an appropriate input capacity, internal delay, and drive capacity balance is provided to the output terminal (or output / feedback input terminal) of the hard macro in which the error has occurred. The error is eliminated by taking measures such as selecting and adding a circuit. Also in this case, since an appropriate buffer circuit can be selected, the degree of freedom for design for a high-speed operation is much higher than in the second conventional example in which the buffer performance is fixed.

It should be noted that, in the flowchart of FIG.
4, the order of the maximum load capacity calculation processing 21 based on the waveform blunting and the maximum load capacity calculation processing 22 based on the feedback delay may be reversed. And the output load verification processing 24 for the feedback delay may be reversed.
Further, a maximum load capacity calculation processing 21 based on waveform dullness and a maximum load capacity calculation processing 2 based on feedback delay
2 is executed at the time of creating the hard macro, and the output load verification process 23 for waveform dulling and the output load verification process 24 for feedback delay are executed after the layout of the LSI is completed. There is no problem even if the process is executed with a time interval between the processes.

FIG. 3 is a detailed flow chart of the maximum load capacity calculation processing 21 based on the waveform blunting of FIG. 2, and the maximum load capacity calculating processing 8 based on the waveform blunting in the conventional example 1 of FIG.
Same as 2.

When the process is started, first, in step 31
Then, the limit waveform dullness Wc is read. Critical waveform dullness W
Practically, a predetermined value registered for each design rule is used as c. Next, in step 32, one of the hard macros to be verified is selected, and the library data is read from the macro cell library 4.

Next, at step 33, the critical waveform dullness W
Based on c and the drive capability of the output unit of the hard macro, the maximum load capacity Cmax based on the waveform dullness is calculated. Next, at step 34, the maximum load capacity C based on the waveform blunting is calculated.
The max is registered in the macro cell library 4.

Next, in step 35, it is determined whether or not the calculation of the maximum load capacity Cmax based on the waveform blunt has been completed for all the hard macros of the target LSI. When the maximum load capacity calculation processing 21 based on the waveform blunting ends, and there is a hard macro for which the calculation of Cmax has not been completed, the process returns to step 32 to continue the processing.

FIG. 4 is a detailed flowchart of the maximum load capacity calculation processing 22 based on the feedback delay of FIG.
FIG. 5 is an explanatory diagram of a procedure for calculating the allowable output delay time To. Hereinafter, the flowchart of FIG. 4 will be described with reference to FIG.

First, in step 41, the LSI to be designed is
Clock cycle (1 / F) corresponding to the maximum operating frequency F of
Is calculated as the maximum delay time Tt. Maximum delay time Tt
5A corresponds to the time from the time when the output latch circuit 51 starts the output timing to the time when the reading of the input latch circuit 55 is completed by the end of the output timing in FIG.

Next, at step 42, one of the hard macros to be verified is selected, and at step 43, the selected hard macro 50 outputs an output signal to the outside and uses the output signal as a feedback signal to output the hard macro 50.
It is checked whether or not it has an output / feedback terminal to be input to the terminal.

When it is determined in step 43 that the output / feedback terminal is provided, the process proceeds to step 44, where the output latch circuit 51 for defining the start of the output timing of the terminal 52, which is the output / feedback terminal in the hard macro 50, is connected to the terminal. The path to the input latch circuit 55 to be latched by the end of the output timing via the feedback input circuit 53 connected to 52 is extracted. When the functional block 54 is inserted between the feedback input circuit 53 and the input latch circuit 55, the input latch circuit 55 to which the signal of the functional block 54 that changes due to the change of the feedback signal is input should be extracted. Consider as a route.

Next, at step 45, the hard macro 50
A feedback signal is supplied to the feedback input circuit 53 based on the internal delay information registered in the macro cell library 4 of FIG.
The feedback time Tf from the time when the circuit threshold value is reached to the time when the input latch circuit 55 latches is calculated.

Next, at step 46, the maximum delay time Tt
Is subtracted from the feedback time Tf to calculate the allowable output delay time To. FIG. 5B shows the relationship between the maximum delay time Tt, the feedback time Tf, and the allowable output delay time To.

Next, at step 47, the second maximum load capacitance value C based on the feedback delay based on the allowable output delay time To and the output drive characteristics of the output section of the hard macro 50.
Calculate Dmax. From the relationship between the typical output delay time and the load capacitance value in FIG. 5C, the second maximum load capacitance value CDmax based on the feedback delay corresponding to the allowable output delay time To can be easily calculated. In step 48,
The second maximum load capacitance value CDmax is registered in the macro cell library 4.

After the completion of step 48, or when it is determined in step 43 that there is no output / feedback terminal, the flow advances to step 49 to determine whether there is any unprocessed hard macro. If there is any unprocessed one, the process returns to step 42. If there is no unprocessed one, the maximum load capacity calculation processing 22 based on the feedback delay is performed.
To end.

Next, a second embodiment of the present invention will be described with reference to the drawings. FIG. 6 is a configuration diagram of a system including the output load verification device 1a according to the second embodiment of this invention. The output load verification device 1a includes a library registration maximum load capacity selection unit 14 in addition to the output load verification device 1 of FIG.

Maximum load capacity calculating means 1 based on waveform blunting
1 calculates a first maximum load capacitance value Cmax based on waveform blunting from a hard macro included in an LSI to be verified, based on output drive characteristics of an output unit and a predetermined limit waveform bluntness Wc.

When the hard macro has an output / feedback input terminal, the maximum load capacity calculating means 12 based on the feedback delay outputs the output section and the output / feedback input terminal from the start of output in the output latch circuit which defines the output timing. Is calculated from the maximum operating frequency F of the LSI in the output delay time until the output signal input via the circuit reaches the circuit threshold of the feedback input circuit, and the allowable output delay time is calculated. A second maximum load capacitance value CDmax based on the feedback delay is calculated based on To and the output drive characteristics of the output unit.

Maximum load capacity selecting means 1 for library registration
4 compares the first maximum load capacitance value Cmax with the second maximum load capacitance value CDmax, selects the smaller one as the registered capacitance value Clmax, and selects the macro cell library 4
Register to

The output load verifying means 13 outputs the circuit connection data of the circuit data file 2 and the layout data file 3
The output load capacity value Cl is calculated by extracting a capacity element serving as a load of the output unit of the hard macro by comparing the layout data of the hard macro with the layout data, and an error determination is made when the output load capacity value Cl is larger than the registered capacity value Clmax Then, an error message is displayed on the input / output display device 5.

FIG. 7 is a flowchart of the output load verification of the hard macro by the output load verification device 1a.

Maximum load capacity calculation processing 7 based on waveform dulling
In FIG. 1, as in the maximum load capacity calculation process 21 based on waveform blunting in FIG. 2, the waveform is obtained from the output drive characteristics of the output unit that drives the output load connected to the terminal of the hard macro and the predetermined limit waveform bluntness Wc. A first maximum load capacitance value Cmax based on the dull delay is calculated.

In the maximum load capacity calculation processing 72 based on the feedback delay, as in the case of the maximum load capacity calculation processing 22 based on the feedback delay in FIG. In the output delay time from the start of the output in the output latch circuit to the time when the output signal input through the output section and the output / feedback input terminal reaches the circuit threshold of the feedback input circuit.
The maximum allowable output delay time To which is an allowable maximum value is calculated from the maximum operation frequency of the second output load, and the second maximum load capacitance value CDmax based on the feedback delay is calculated based on the allowable output delay time To and the output drive characteristics of the output unit. calculate.

In the next library registration maximum load capacity selection process 73, the first maximum load capacity value Cmax is compared with the second maximum load capacity value CDmax, and the smaller capacity value is selected as the registered capacity value Clmax. Then, it is registered in the macro cell library 4.

In the output load verification processing 74, the circuit connection data of the circuit data file 2 is compared with the layout data of the layout data file 3, and a capacitance element serving as a load of the output section of the hard macro is extracted to obtain an output load capacitance value. Cl
Is calculated, and the output load capacity value Cl becomes the registered capacity value Clmax.
If it is larger, an error is determined, and an error message is displayed on the input / output display device 5.

Maximum load capacity calculation processing based on waveform dulling 7
The detailed flow of 1 overlaps with the detailed flow described with reference to FIG. 3 and the detailed flow of the maximum load capacity calculation processing 72 based on the feedback delay also overlaps with the detailed flow described with reference to FIG. .

It is clear that the output load verification device 1a of the second embodiment of FIG. 6 has the same effect as that of the first embodiment, but in addition, the output load verification process is performed once. From the maximum load capacity calculation processing 71 based on the waveform dullness to the output load verification processing 7
The time required for the entire process up to 4 can be reduced.

The order of the maximum load capacity calculation processing 71 based on waveform blunting and the maximum load capacity calculation processing 72 based on feedback delay may be reversed. Between the maximum load capacity selection processing 73 for library registration and the output load verification processing 74, such that the processing up to the maximum load capacity selection processing 73 is executed when the hard macro is created, and the output load verification processing 74 is executed after the layout of the LSI is completed. There is no problem even if the program is executed with a time interval. Further, the output load verification device 1a does not necessarily need to be a dedicated device, and may be configured by a general-purpose computer and a program for executing the processing of FIG.

[0057]

As described above, by applying the present invention, as in the first conventional example, a delay due to an increase in delay due to waveform dulling that may occur during logic / delay simulation after layout design. The first problem of a decrease in verification accuracy can be avoided beforehand, and a hard macro that may occur when the output signal is a circuit that feeds back to the inside of the hard macro itself as in the second conventional example. In addition to avoiding the second problem of the malfunction of the hard macro itself due to the effect of the load connected to the output terminal of the first embodiment, the structural constraint on the hard macro caused in the second conventional example can be avoided. An effect is obtained that the third problem of loss of design freedom for high-speed operation due to addition can be solved.

In the second embodiment, since the output load verification processing can be reduced to one processing, the time required for the entire processing can be reduced in addition to the above effects.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of an entire system including an output load verification device 1 according to a first embodiment of the present invention.

FIG. 2 is a flowchart of an output load verification of a hard macro by the output load verification device according to the first embodiment.

FIG. 3 is a detailed flowchart of a maximum load capacity calculation process based on waveform dulling;

FIG. 4 is a detailed flowchart of a maximum load capacity calculation process based on a feedback delay;

FIG. 5 is an explanatory diagram of a calculation procedure of an allowable output delay time To.

FIG. 6 is a configuration diagram of a system including an output load verification device 1a according to a second embodiment.

FIG. 7 is a flowchart of an output load verification of a hard macro by the output load verification device according to the second embodiment.

FIG. 8 is a diagram illustrating a first example of preventing a decrease in delay accuracy due to waveform dulling.
It is explanatory drawing of the prior art example.

FIG. 9 is a block diagram of a second conventional example for solving a malfunction of the hard macro itself due to an influence of a load connected to an output terminal of the hard macro.

[Explanation of symbols]

1, 1a Output load verification device 2 Circuit data file 3 Layout data file 4 Macro cell library 5 Input / output display device 11 Maximum load capacitance calculation unit based on waveform dullness 12 Maximum load capacitance calculation unit based on feedback delay 13 Output load verification unit 14 Library Maximum load capacity selection means for registration 21, 71, 82 Maximum load capacity calculation processing based on waveform dulling 22, 72 Maximum load capacity calculation processing based on feedback delay 23 Output load verification processing for waveform dulling 24 Output load verification processing for feedback delay 50 Hard macro 51 Output latch circuit 52 Terminal 53 Feedback input circuit 55 Input latch circuit 73 Maximum load capacity selection processing for library registration 74, 83 Output load verification processing 90 Original hard macro 94 Buffer 95 Hard macro with buffer

Claims (8)

[Claims] 1. A maximum load capacity calculating means for calculating a first maximum load capacity value from an output drive characteristic of an output unit and a predetermined limit waveform dullness for a hard macro, and an output to the hard macro. When there is also a feedback input terminal, from the start of output in the output latch circuit that defines the output timing until the output signal input via the output section and the output / feedback input terminal reaches the circuit threshold of the feedback input circuit Calculating an allowable output delay time, which is a maximum value allowed from the maximum operating frequency of the LSI at the output delay time, and calculating a second maximum load capacitance value based on the allowable output delay time and the output drive characteristic of the output unit. Means for calculating the maximum load capacity based on the calculated feedback delay, and comparing the circuit data and the layout data with each other. The output load capacitance value is calculated by extracting a capacitance element serving as a load of the output unit of the output unit. When the output load capacitance value is larger than the first maximum load capacitance value or the second maximum load capacitance value, An output load verification device comprising: an output load verification unit that determines an error. 2. A process for calculating a first maximum load capacitance value from an output drive characteristic of an output portion and a predetermined limit waveform dullness for a hard macro, and a maximum load capacitance calculation process based on waveform dullness registered in a macro cell library. In the case where the hard macro has an output / feedback input terminal, an output signal input from an output start in an output latch circuit for defining an output timing through an output section and the output / feedback input terminal is a feedback input circuit. In the output delay time until the circuit threshold value is reached, an allowable output delay time which is an allowable maximum value from the maximum operating frequency of the LSI is calculated, and the second output delay time is calculated based on the allowable output delay time and the output drive characteristic of the output unit. The maximum load capacity value based on the feedback delay to calculate the maximum load capacity value of the Calculation processing, reading the circuit data of the LSI from the circuit data file, reading the layout data of the LSI from the layout data file, comparing the both, extracting the capacitance element which becomes the load of the output section of the hard macro, and calculating the output load capacitance value. Calculating the output load capacity value, comparing the output load capacity value with the first maximum load capacity value, and performing an output load verification process for waveform dullness to determine an error when the output load capacity value is larger than the first maximum load capacity value; A hard macro having a feedback input terminal, and an output load verification process for a feedback delay for determining an error when the output load capacitance value is larger than the second maximum load capacitance value. Output load verification method. 3. A maximum load capacity calculating process based on the feedback delay includes: a first step of calculating a clock cycle corresponding to a maximum operating frequency of an LSI to be designed as a maximum delay time; A second step of selecting a plurality of hard macros, and an output for outputting the output signal to the selected hard macro selected in the second step and inputting the output signal as a feedback signal to the selected hard macro. 3rd inspection to determine whether it has a feedback terminal
And, when it is determined in the third step that the output / feedback terminal is provided, the output latch circuit defining the start of the output timing of the output / feedback terminal in the selected hard macro. A fourth step of extracting a path to an input latch circuit to be latched by the end of the output timing via a feedback input circuit connected to an output / feedback terminal; and A fifth step of calculating a feedback time from a time when the feedback signal reaches a circuit threshold value of the feedback input circuit to a time when the feedback signal is latched by the input latch circuit, based on the registered internal delay information; Subtract the feedback time from the time to allow the output delay A sixth step of calculating the second maximum load capacitance value based on a feedback delay based on the allowable output delay time and an output drive characteristic of the output unit of the selected hard macro. And an eighth step of registering the second maximum load capacitance value in the macro cell library. After the completion of the eighth step or in the third step, it is determined that the output / feedback terminal is not provided. When there is an unprocessed hard macro, the process returns to the second step when there is an unprocessed hard macro, and terminates the maximum load capacity calculation process based on the feedback delay when there is no unprocessed hard macro. The method for verifying output load of a hard macro according to claim 2. 4. A maximum load capacity calculating means for calculating a first maximum load capacity value from an output drive characteristic of an output unit and a predetermined limit waveform dullness for a hard macro, and an output to the hard macro. When there is also a feedback input terminal, from the start of output in the output latch circuit that defines the output timing until the output signal input via the output section and the output / feedback input terminal reaches the circuit threshold of the feedback input circuit Calculating an allowable output delay time, which is a maximum value allowed from the maximum operating frequency of the LSI at the output delay time, and calculating a second maximum load capacitance value based on the allowable output delay time and the output drive characteristic of the output unit. Maximum load capacity calculating means based on the feedback delay to be calculated; the first maximum load capacity value and the second maximum load capacity value; A library registration maximum load capacitance selecting means for selecting a comparatively small capacitance value as a registered capacitance value in the macro cell library; and a capacitance element serving as a load of an output unit of the hard macro by comparing circuit data and layout data. An output load verification unit that extracts the output load capacitance value and calculates an error when the output load capacitance value is larger than the registered capacitance value. 5. A maximum load capacitance calculation process based on waveform dullness for calculating a first maximum load capacitance value from an output drive characteristic of an output unit and a predetermined limit waveform dullness for a hard macro and registering the same in a macro cell library; When the hard macro has an output / feedback input terminal, the output signal input from the output unit and the output unit and the output / feedback input terminal via the output / feedback input terminal from the start of output in the output latch circuit that defines output timing is the feedback input circuit. An output delay time which is an allowable maximum value from the maximum operating frequency of the LSI in the output delay time until the circuit threshold is reached is calculated based on the allowable output delay time and the output drive characteristic of the output unit. Maximum load capacity based on feedback delay for calculating maximum load capacity value and registering it in the macro cell library Library processing maximum load capacity selection processing for comparing the first maximum load capacity value and the second maximum load capacity value and selecting a smaller capacity value as a registered capacity value in the macro cell library. Reading the circuit data of the LSI from the circuit data file, extracting the capacitance element serving as the load of the output unit of the hard macro from the layout data file, calculating the output load capacitance value, and comparing the output load capacitance value with the first maximum load capacitance value; An output load verification process for determining an error when the output load capacitance value is larger than the registered capacitance value. 6. A first load capacity calculating process based on the feedback delay, wherein a first cycle of calculating a clock cycle corresponding to a maximum operating frequency of an LSI to be designed as a maximum delay time; A second step of selecting a plurality of hard macros, and an output for outputting the output signal to the selected hard macro selected in the second step and inputting the output signal as a feedback signal to the selected hard macro. 3rd inspection to determine whether it has a feedback terminal
And, when it is determined in the third step that the output / feedback terminal is provided, the output latch circuit defining the start of the output timing of the output / feedback terminal in the selected hard macro. A fourth step of extracting a path to an input latch circuit to be latched by the end of the output timing via a feedback input circuit connected to an output / feedback terminal; and A fifth step of calculating a feedback time from a time when the feedback signal reaches a circuit threshold value of the feedback input circuit to a time when the feedback signal is latched by the input latch circuit, based on the registered internal delay information; Subtract the feedback time from the time to allow the output delay A sixth step of calculating the second maximum load capacitance value based on a feedback delay based on the allowable output delay time and an output drive characteristic of the output unit of the selected hard macro. And an eighth step of registering the second maximum load capacitance value in the macro cell library. After the completion of the eighth step or in the third step, it is determined that the output / feedback terminal is not provided. When there is an unprocessed hard macro, the process returns to the second step when there is an unprocessed hard macro, and terminates the maximum load capacity calculation process based on the feedback delay when there is no unprocessed hard macro. The method for verifying output load of a hard macro according to claim 5. 7. A first method for calculating a first maximum load capacitance value from an output drive characteristic of an output unit and a predetermined limit waveform dullness for a hard macro and registering the calculated maximum load capacitance value in a macro cell library.
In the case where the hard macro has an output / feedback input terminal, an output signal input from an output start in an output latch circuit that defines an output timing through an output unit and the output / feedback input terminal is provided. In the output delay time until the feedback input circuit reaches the circuit threshold, an allowable output delay time, which is the maximum value allowed from the maximum operating frequency of the LSI, is calculated based on the allowable output delay time and the output drive characteristics of the output unit. A second program for calculating a second maximum load capacitance value and registering the same in the macro cell library; reading circuit data of the LSI from a circuit data file and reading layout data of the LSI from a layout data file; The capacitive element which becomes the load of the output section of the hard macro is extracted and the output A third program for calculating a capacity value, comparing the output load capacity value with the first maximum load capacity value, and determining an error when the output load capacity value is larger than the first maximum load capacity value; And a fourth program for extracting a hard macro having a feedback input terminal and determining an error when the output load capacitance value is larger than the second maximum load capacitance value. The recording medium on which it was recorded. 8. A first program for calculating a first maximum load capacitance value from an output drive characteristic of an output unit of a hard macro and a predetermined limit waveform dullness and registering the same in a macro cell library; When a feedback input terminal is provided, from the start of output in the output latch circuit that defines the output timing until the output signal input via the output unit and the output / feedback input terminal reaches the circuit threshold of the feedback input circuit. Calculating an allowable output delay time, which is a maximum value allowed from the maximum operating frequency of the LSI at the output delay time, and calculating a second maximum load capacitance value based on the allowable output delay time and the output drive characteristic of the output unit. A second program that calculates and registers the macro load in the macro cell library; the first maximum load capacitance value and the second maximum load capacity value; A third program for comparing the load capacitance value and selecting a smaller capacitance value as a registered capacitance value in the macro cell library; reading out the circuit data of the LSI from the circuit data file and reading the output data of the hard macro from the layout data file; Extracting a capacitance element serving as a load, calculating an output load capacitance value, comparing the calculated output load capacitance value with the first maximum load capacitance value, and determining an error when the output load capacitance value is larger than the registered capacitance value. A recording medium recording an output load verification program, comprising: a program;