JP2001331346A - Simulator and its method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a simulator, capable of debugging a control program as through a real machine exists, even if the real machine has not been completed yet. SOLUTION: The simulator is provided with a control CPU (113), a simulation CPU (115), a memory (114a) allowed to be read out from both the CPUs (113 and 115), and a bus (116) for connecting the CPU (113) to the memory (114). Control information is written in the memory (114) by the CPU (113), the control information written in the memory (114) is read by the CPU (115) via the bus (116), simulation based on the control information is executed, the simulation result is written in the memory (114) via the bus (116), and the simulation result written in the memory (114) is read by the CPU (113).

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a simulator and a simulation method which react as if there is a real machine in order to debug a mechanism control program without using a real machine.

[0002]

2. Description of the Related Art A mechanism control program is debugged by creating a mechanism and hardware for driving and controlling the mechanism (mechanism + hardware is called an actual machine) and actually controlling the actual machine.

[0003]

However, the technique of actually controlling the actual machine to debug the mechanism control program has a problem that full-scale debugging cannot be performed until the actual machine is completed. In addition, it is difficult to intentionally generate a rare abnormal state, and there is a problem that sufficient verification cannot be performed.

An object of the present invention is to debug a control program as if there is an actual machine even if the actual machine is not completed, and to verify the control program by arbitrarily generating various abnormal states. It is to provide a possible simulator and a simulation method.

[0005]

Means for Solving the Problems To solve the above problems and achieve the object, a simulator and a simulation method according to the present invention are configured as follows.

(1) A simulator according to the present invention includes a simulation CPU, a control CPU to which the simulator is connected, and a memory readable by one of the control CPU and the simulation CPU, and a memory readable by the other. And a means for reading the control information written in the memory from the control CPU by the simulation CPU, and a means for writing the result of executing the simulation based on the control information to the memory so as to be readable from the control CPU.

(2) In the simulation method according to the present invention, the control information is written to the first memory by the control CPU, and the control information written to the first memory by the simulation CPU is read out via the connection means. The simulation based on the control information is executed by the simulation CPU, a result of the simulation is written into a second memory via a connection unit by the simulation CPU, and the simulation CPU writes the result of the simulation into the second memory. Read the simulation result.

[0008]

Embodiments of the present invention will be described below with reference to the drawings.

Referring to FIG. 1, debugging using a real machine will be described, and in contrast, debugging (simulator) without using a real machine according to the present invention will be described with reference to FIG. FIG. 1 is a diagram schematically showing actual hardware, and FIG. 2 is a diagram schematically showing a simulator.

[0010] As shown in FIG.
An ASIC 102 (CPU side) that controls the mechanism is connected to the ASIC 102. The ASIC 102 and the ASIC 103 are connected via a serial line 104. Further, the ASIC 103 includes a motor 105, a solenoid 10
6 and the sensor 107 are connected. Control CPU
The motor 101 connected to the ASIC 103 writes control information to a register of the ASIC 102.
5, the solenoid 106, the sensor 107 and the like can be controlled.

The motor 105, the solenoid 106, the sensor 107 and the like operate in accordance with control information transmitted from the control CPU 1 through the ASIC 103, and the operation of the mechanism and the operation of the medium occur, and as a result, the ON / OFF of the sensor is performed.
The off state changes. The control CPU 101 is an ASIC1
02, the ASIC 103
The state of each sensor connected to can be detected.

On the other hand, as shown in FIG.
Simulator hardware 114 is connected to 113. The simulator hardware 114 is a control CPU
When viewed from 113, it includes a register group 114a such as a sensor information reference register, an output port control information write register, a motor control command write register, a response information reference register, and an interrupt status register.

The register group 114a includes an ASIC1
02 is a register having the same configuration as the register of the control CP.
The memory corresponds to a memory that can be read from both the U113 and the CPU 115. When the control program for the real machine is executed on the control CPU 113, the actual operation is performed while referring to a predetermined register in the register group 114a of the simulator hardware 114 and writing.

The control information written into predetermined registers in the register group 114a by the control CPU 113 is transmitted to a simulator program executed on the CPU 115 of the personal computer 111 via the PCI bus 116. The access via the PCI bus is actually performed by the driver, and the DLL function is used to connect the CPU 115 to the driver.

The simulator program refers to a predefined mechanism operation description, simulates an operation in accordance with control information from the control CPU 113, and detects a change in the sensor as a result in a predetermined register in a register group 114a of the simulator hardware 114. Write to the register. Control C
The PU 113 refers to a predetermined register in the register group 114a of the simulator hardware 114,
The simulation result written by the simulator program can be read as a sensor change, just like referring to a change in a sensor state as a result of a mechanism operation in an actual machine.

This operation will be described with reference to FIG. FIG. 3 is a diagram showing a flow of reading and writing data from and to a register group of the simulator hardware, an interrupt process, and the like.

1. Output Port The data written by the control CPU 113 to the output port is:
The data is written into the DP-RAM in the simulator hardware 114, and the simulator software can read the data by calling the GetPortStatus () function.

2. Command The data written by the control CPU 113 to the output port is:
The command is written to the DP-RAM in the simulator hardware 114, and the simulator software can read the written command by calling the GetCommand () function.

3. The sensor status data is set in the DP-RAM in the simulator hardware 114 by calling the PutSensorStatus () function from the sensor simulator software. Control C
The PU 113 can read the sensor state data by reading a predetermined address of the simulator hardware 114.

4. Response The response is set in the DP-RAM in the simulator hardware 114 by calling the PutResponse () function from the simulator software. Control CPU 113
By reading a predetermined address of the simulator hardware 114, response data can be obtained.

5. Interrupt control The program of the CPU 113 processes an interrupt from the CPU 115 as a trigger. Therefore, after completing the processing for a predetermined time (for example, 128 μsec) on the simulator software side and updating the sensor state and writing the response, the IssueCP interrupt () function is called to control the control CP.
It is necessary to prompt the U113 to perform the processing.

6. The circuit in the status simulator hardware 114 includes a control CP
The register corresponding to the status register of the ASIC is updated according to the access from the U113 side and the simulator software side. Updates are actually performed for the three bits of write buffer full, write buffer empty, and reception data.

Here, the simulation method described above will be summarized with reference to FIG. As shown in FIG.
First, the control CPU 113 writes a command (control information) into a predetermined register (first memory) in the register group 114a (ST21). The command written by the simulation CPU 115 is read (ST22). Simulation based on the command read by CPU 115 is executed (ST2).
3). Along with this simulation, a simulation result (change in sensor level) is obtained. CPU11
5, the result of the simulation is stored in the register group 114a.
(ST24). After that, it shifts to parallel processing. In one of the parallel processes, the result of the simulation written by the control CPU 113 is read (ST25). In the other of the parallel processes, an interrupt is requested to the control CPU 113 (ST26). This interrupt is counted (ST27), and data for timeout is transmitted based on the count value (ST28). Note that interrupt processing,
The timeout process will be described later in detail.

Next, the simulator program (CPU 1
15 and the control program (executed by the control CPU 113).

In the hardware of the actual device, the sensor scan is performed at a period of 100 μsec to 1 msec. However, the simulator program is software executed on a personal computer. It is difficult to execute at the same time as the cycle. Further, since the required time for the simulation varies depending on the state of the mechanism inside the simulator, it is necessary to synchronize with the control CPU 113.

To realize this, the above-mentioned interrupt is used. The simulator completes the simulation once, writes the sensor state and response to a predetermined register in the register group 14a of the simulator hardware 114, and then issues an interrupt generation request.

The structure of the control program executes the interrupt processing shown in FIG. In the interrupt process, the mechanism control process is executed by using any one of the interrupt and the sensor change as a trigger. That is, when an interrupt occurs, the response register of the ASIC (simulator hardware) is referred to,
Perform necessary processing. Reference is made to a sensor register of an ASIC (simulator hardware) to detect a sensor change and execute a corresponding process. Then, the command in the soft queue is written into the ASIC (simulator hardware), and the process ends.

In the actual system, the ASIC 10
2 generates an interrupt at the timing when a series of serial communication with the ASIC 103 is completed (the cycle is 100 μm as described above).
sec to 1 msec).

In the task processing shown in FIG. 5, the processing is performed irrespective of the interruption. However, since the motor stop command is not registered unless a change in the sensor occurs, the execution is performed without shifting the phase from the simulator side.

In the interrupt processing, the processing is performed only at the timing when the simulator issues an interrupt request. Therefore, it is necessary to perform the processing without causing problems such as overflow of command registration, double reading of response, and reading-out. Is possible.

Another problem is a timeout in task processing.

In general, the control CPU 113 measures time using an interval timer or the like. If the mechanism operation is not completed within a predetermined time, a timeout error is generated. Simulation by software is
Since the operation is slower than the operation of the actual device, a timeout error occurs in the same timeout period as the actual device.

To cope with this, it is possible to change the timeout value of the control CPU, lengthen the cycle of the reference timer, or change the timer to a timer synchronized with the simulator. However, the former two methods cannot cover variations in the simulator execution time and need to be set with a very large margin. In this case, however, the simulation execution time becomes longer than necessary, When an error is intentionally caused, there is a problem that the time at which the error occurs is difficult to predict.

Therefore, the interrupt generation request from the simulator is counted by the simulator hardware or software (DLL function or the like) on a personal computer, and a simulated timer interrupt is generated at a constant count interval.

The above-mentioned invention of the present application is summarized as follows.

1. A group of registers having the same configuration as the control system of the actual machine is mounted in the memory space of the CPU for executing the control program, and the register read / write is simulated as if a mechanism control ASIC was connected.

2. Since the simulator operated by the PC software has a regular rule as compared with the hardware of the actual machine,
The control program has a mechanism that synchronizes with this (prevents the phase from proceeding without waiting for the hardware to move). In addition, the program for operating the actual machine can be executed by the simulator without any modification.

Here, an example of the actual hardware described above will be described with reference to FIG.

As shown in FIG. 6, the main control unit 1
U2 is provided. The main control unit 1 includes the ASIC 10 described above.
2, and the CPU 2 corresponds to the control CPU 101 described above. The CPU 2 has a sensor on / off memory 3, a response memory 5, a command memory 7, a port O
The N / OFF memory 60 is connected. These sensor ON / OFF memory 3, response memory 5, command memory 7, and port ON / OFF memory 60 correspond to the above-described register group. The sensor on / off memory 3
Serial line 52 via serial-parallel converter 4
It is connected to the. The response memory 5 has a serial
It is connected to the serial line 53 via the parallel converter 6. The command memory 7 is connected to a serial line 54 via a parallel-serial converter 8.

The main controller 1 has an address synchronization signal generator 9. This address synchronization signal generator 9
Are connected to a serial line 51.

The unit control section 20 has a switch 21 as a selecting means, and the switch 21 is connected to a plurality of sensors Sa, Sb,... Sn. The unit control unit 20 corresponds to the ASIC 103 described above. Further, the switch 21 includes a sensor switching timing generation unit 40
The time-division scanning is repeated based on the timing signal supplied from the controller, and the signal of each sensor (hereinafter, referred to as a sensor signal) is sequentially selected and output.

The level of each sensor signal selected by the switch 21 is converted into digital data by the A / D converter 22. The digital data is stored as sensor level data in the sensor level memory 23 and is also supplied to the comparator 24.

The comparator 24 compares each sensor level data from the A / D converter 22 with a plurality of slice levels stored in the slice level memory 25 in advance. Then, the respective comparison results are held in the comparison result memory 26. The slice level memory 25, based on the timing signal supplied from the sensor switching timing generation unit 40, at the same timing as the scan of the switch 21,
The slice level corresponding to each sensor is sequentially output.

Each comparison result in the comparison result memory 26 is sequentially output in accordance with a timing signal (not shown) independent of the sensor scan, and is output from the parallel-serial converter 31.
Is converted to a serial signal. The serial signal thus converted is transmitted to the serial-parallel converter 4 of the main controller 1 via the serial line 52.

Each sensor level data in the sensor level memory 23 is sequentially read out according to a timing signal (not shown) independent of the sensor scan. Further, after being selected by the selector 32 in response to an instruction from the command analysis unit 36 described later, the parallel-serial converter 3
In step 3, it is converted to a serial signal. The serial signal thus converted is transmitted to the serial-parallel converter 6 of the main controller 1 via the serial line 53.

The serial-parallel converter 34 is connected from the parallel-serial converter 8 of the main controller 1 to the serial line 5.
4 is converted in parallel. The command converted in parallel in this manner is held in the command memory 35, and the held content is analyzed by the command analysis unit 36.

The command analysis unit 36 analyzes a predetermined command in the command memory 35 and gives an instruction to the selector 32 to transmit the sensor level data in the sensor level memory 23 to the main control unit 1. .

Further, the command analyzing unit 36 analyzes a plurality of slice levels from a predetermined command in the command memory 35, and stores the analysis result in the slice level memory 25.

Further, the command analysis unit 36 includes the main control unit 1
When the command transmitted from is received, the same command as received is immediately returned to the main control unit 1 via the selector 32 and the parallel-serial converter 33 (that is,
(A return command for an echo back check).

The synchronizing signal receiving section 30 includes a serial line 51
And is connected to the address synchronization signal generator 9 of the main controller 1 via the control unit 1 and receives the synchronization signal supplied from the address synchronization signal generator 9.

The port connected to the CPU 2 is turned ON / OFF.
The OFF memory 60 is connected to a serial line 62 via a parallel-serial converter 61. Further, the serial line 62 is connected to an output port circuit 64 via a serial-parallel converter 63 in the unit control unit 20. This output port 64 has a solenoid P
a, DC motor Pb, and display Pn.

The output signal of the address / synchronous signal generator 9 is connected to a serial line 51 and also to a parallel-serial converter 61. Synchronization signal SYN
When C is at a low level, the parallel-serial converter 61 outputs an address signal (A0 to A3) output from the address / synchronization signal generator 9 to the serial line 62 as an SDA signal.

On the other hand, the serial-parallel converter 63 of the unit control section 20 receives the RDA signal from the serial line 62 and outputs it to the address analysis section 99 and the output port circuit 64. The address analysis unit 99 includes the synchronization signal receiving unit 30
When the SYNC signal is at the low level in synchronization with the SYNC signal from the CPU, it is analyzed whether or not the address (A0 to A3) of the RDA signal is an address signal for its own unit control unit.

The output port circuit 64 fetches the RDA signal as output port data in synchronization with the high level of the synchronization signal SYNC when the address analysis section 99 analyzes that the address is its own.

A motor control circuit 65 is also provided in the unit control section 20, and the motor control circuit 65
Stepping motors Ma to Mn are connected.

Hereinafter, the operation of the motor control circuit 65 will be described in more detail.

The motor control circuit 65 receives the initial motor speed from the main control unit 1 via the serial line 54.
It is controlled by giving parameters such as maximum speed, acceleration rate, deceleration rate, and operation amount, and giving commands such as operation start and operation stop.

Therefore, the CPU 2 first writes parameters and commands to be transmitted to the motor control circuit 65 in the command memory 7. The parallel-serial converter 8 reads information including various parameters and commands written in the command memory 7, converts the information into a serial signal,
The signal is transmitted to the serial-parallel converter 34 via the serial line 54. This serial signal is
After being converted into a parallel signal by the parallel converter 34, it is written into the command memory 35. The contents are analyzed by the command analysis unit 36 in the same manner as the sensor circuit control command (sensor level read, slice level setting command). When the parameters and commands are to be sent to the motor control circuit 65, the parameters and commands are sent to the motor control circuit 65.
The motor control circuit 65 performs an operation according to the parameters and commands sent in this way.

When the above parameters and commands require the return of the operation result, the operation result is transmitted to the selector 32 by the motor control circuit 65. The command analysis unit 36 simultaneously controls the selector 32 and sends the operation result from the motor control circuit 65 to the parallel-serial converter 33,
The serial signal is converted by the serial converter 33 into a serial signal. This serial signal is sent to the serial-parallel converter 6 of the main controller 1 via the serial line 53, converted into a parallel signal, and stored in the response memory 5. This allows the CPU 2 to read the response of the motor control circuit 65.

Next, the operation of the output port circuit 64 will be described in detail.

The CPU 2 has a port ON / OFF memory 6
"1" is written to an address corresponding to an output port to be turned ON or OFF, and "0" is written to an address to be turned OFF. The parallel-serial converter 61 is
Serialize the contents of the port ON / OFF memory 60,
Serial-parallel converter 6 via serial line 62
Transmit to 3. Thus, the output port ON / OFF information parallelized by the serial-parallel converter 63 is read by the output port circuit 64. And
The output port circuit 64 is connected to the output port ON / OF.
The output of a predetermined port is set according to the F information.

Then, as in the case of the motor control circuit 65 described above, when the operation result needs to be returned, the operation result is transmitted to the selector 32 by the output port circuit 64. The command analysis unit 36 simultaneously controls the selector 32, sends the operation result to the parallel-serial converter 33, and converts the operation result into a serial signal by the parallel-serial converter 33. This serial signal is sent to the serial-parallel converter 6 of the main controller 1 via the serial line 53, converted into a parallel signal, and stored in the response memory 5. Thereby, the CPU 2
Can read the response of the output port circuit 84.

Here, to summarize the contents described above,
In this control system, all of the commands for the sensors Sa to Sn, the command for the output port circuit 64, and the command for the motor control circuit 65 are transmitted from the main control unit 1 to the unit control unit 20 via the same serial line 54. Sent to.

That is, under the control of the CPU 2 of the main controller 1, each command is stored in the command memory 7,
After being converted into a serial signal by the parallel-serial converter 8, the unit control unit 20
Is transmitted to the serial-to-parallel converter 34 on the side. Then, the signal is converted into a parallel signal by the serial-parallel converter 34 and stored in the command memory 35. Further, the command analysis unit 36 at the subsequent stage determines which purpose the control command relates to, and sends the control command to the corresponding unit. Then, in each unit receiving the command, a predetermined operation based on the command is performed.

If the parameters and commands sent to the respective units include contents requiring return of the operation result, the selector 32, the parallel-serial converter 33, the serial line 53, the serial-parallel converter The response of each unit is stored in the response memory 5 via the device 6. Thus, the CPU 2 can read the response of each unit.

As described above, the command for controlling the operation state of the sensors Sa to Sn, the command for controlling the operation state of the output port circuit 64, and the motor for the motor control circuit 65 are transmitted through the same serial line 54. It is possible to transmit a command for controlling the rotation start, stop, and the like. Also, regarding the response, the response from the sensors Sa to Sn, the response from the output port circuit 64,
A response from the motor control circuit 65 can be transmitted.

In this control system, the sensors Sa to
The output signals from the Sn are sequentially selected and output via the switch 21, and the A / D converter 22 receiving the output signals converts the output signals into digital signals. And the comparator 2
In step 4, the digital signal and the sensor level memory 23
Is compared with a threshold level stored in advance.
Then, after storing this comparison result in the comparison result memory 26, it is converted into a serial signal by the parallel-serial converter 31 and transmitted to the serial-parallel converter 4 of the main control unit 1 via the serial line 52. I do. Then, the signal is converted into a parallel signal by the serial-parallel converter 4 and stored in the sensor on / off memory 3.

Next, an application example of the above-described embodiment will be described. In the embodiment described above, the control CP
Since it is assumed that U and the simulator are directly connected to the same dual port RAM, a plurality of simulators, a plurality of control CPUs,
It is not suitable for a flexible configuration such as connecting the U to another device. Therefore, the following application examples will be described.

The debugging using the actual machine will be described with reference to FIG. 7, and the debugging (simulation system) without using the actual machine according to the present invention will be described with reference to FIGS. 8 and 9. FIG. 7 is a diagram showing an outline of actual hardware, and FIGS. 8 and 9 are diagrams showing an outline of a simulation system.

As shown in FIG. 7, in the actual machine, the control CPU 1
The ASICs 102a (CPU side) and 102b (CPU side) that control the mechanism are connected to 01. This ASI
The C102a and the ASICs 103-1a and 103-1b are connected via the serial line 104. Further, a motor 105, a solenoid 106, a sensor 107, and the like are connected to the ASICs 103-1a and 103-1b. The ASIC 102b and the ASIC 103
-2 a and 103-2 b are connected via the serial line 104. Further, a motor 105, a solenoid 106, a sensor 107, and the like are connected to the ASICs 103-2a and 103-2b.

The control CPU 101 writes control information into the registers of the ASICs 102a and 102b, thereby
The motor 105, the solenoid 106, the sensor 107, and the like connected to the SICs 103-1a, 103-1b, 103-2a, and 103-2b can be controlled.

The ASICs 103-1 a and 103-1 include the motor 105, the solenoid 106, and the sensor 107.
b, 103-2a, and 103-2b, which operate according to the control information from the control CPU 101, and the operation of the mechanism, the operation of the medium, and the like occur, and as a result, the on / off state of the sensor changes. The control CPU 101
By referring to the registers of the SICs 102a and 102b, the ASICs 103-1a, 103-1b, 103
-2a and 103-2b can be detected.

On the other hand, as shown in FIG. 8, in the simulation system, a plurality of simulators 111-
1, 111-2, 111-3, and 111-4 are arranged. The simulator 111-1 includes a simulator hardware 114-1 and a CPU 115-1. Simulator hardware 114-1 and CPU 115-1 are PCI
They are connected by a bus 116-1. Similarly, the simulator 111-2 includes the simulator hardware 114-2 and C
PU115-2 is provided. Simulator hardware 11
4-2 and the CPU 115-2 are connected by a PCI bus 116-2. Similarly, the simulator 111-3 includes:
Simulator hardware 114-3 and CPU 115-3 are provided. Simulator hardware 114-3 and CPU1
15-3 is connected by a PCI bus 116-3.
Similarly, the simulator 111-4 includes a simulator hardware 114-4 and a CPU 115-4. Simulator hardware 114-4 and CPU 115-4 are PC
They are connected by an I bus 116-4.

The ASIC 102a (first system) is connected to simulator hardware 114-1, 114-2, 114-3, and 114-4. Similarly, ASIC10
2b (second system) is a simulator hardware 114-1,
It is connected to 114-2, 114-3, and 114-4.

Simulator hardware 114-1, 1
14-2, 114-3, and 114-4 are ASIC1
ASIC 103-1 from the perspective of 02a and 102b
a, 103-1b, 103-2a, and 103-2b. Simulator hardware 114-1,
114-2, 114-3, 114-4 and ASIC1
02a and 102b are connected via the serial line 104,
Exchanges information in sensor memory, command memory, response memory, etc.

When the control program for the real machine is executed by the control CPU 101, the control information written from the control CPU 101 is received by the simulator, and the operation result written by the simulator is received by the control CPU 101.

The simulator program refers to a mechanism operation description defined in advance, simulates the operation according to the control information, and writes the resulting change in the sensor to the simulator hardware. The control CPU 101 can read a simulation result written by the simulator program as a sensor change, just like referring to a change in a sensor state as a result of a mechanism operation in an actual machine.

Here, FIG. 9 will be briefly described. FIG. 9 is a diagram showing C in the simulation system shown in FIG.
It shows details of the internal structure of the PU-side ASIC and the simulator 111-1.

The CPU ASIC 102a includes a sensor memory 202, a response memory 203, a command memory 2
04, port memory 205, address synchronization signal generator 2
07, serial / parallel converters 208 and 209, and parallel / serial converters 210 and 211. Sensor information (on / off) and response information from the simulator are written in the sensor memory 202 and the response memory 203. Command information and port information sent to the simulator are written in the command memory 204 and the port memory 205. Note that CP
The basic configuration of the U-side ASIC 102b is the CPU-side ASIC
The basic configuration is the same as 102a.

The simulator 111-1 includes an address synchronization signal receiving section 220, parallel / serial converters 221 and 222, a command analysis section 223, serial / parallel converters 224, 225, 226 and 227, and an address synchronization signal receiving section 228. , Serial / parallel converter 22
9, 230, 231, and 232, sensor memory 23
3, response memory 234, command memory 235,
Port memory 236, sensor monitor memory 237, response monitor memory 238, command memory 239, sensor memory 240, response memory 241, port memory 242, write counter 260, read counter 261, comparator 262, self-address holding unit 270,
An address comparison unit 271 is provided. The basic configuration of the simulators 111-2, 111-3, and 111-4 is as follows.
This is the same as the basic configuration of the simulator 111-1.

Here, the operation of the simulation system will be described with reference to the flowchart shown in FIG.

First, the control CPU 101 executes the CPU-side ASI
Write a motor start command to C102a (ST
1). The CPU-side ASIC 102a sends a motor start command to the serial line (ST2). The motor start command is input to the command memory 235 and the command analyzer 223 of the simulator 111-1 (ST3).
From here, the operation branches to a parallel operation.

First, one parallel operation will be described.
The command analysis unit 223 instructs the response memory 234 to send a response to the start command (S
T4). The response memory 234 sends a response (normal start) to the preset start command to the CPU-side ASIC 102a via a serial line (ST5). The control CPU 101 recognizes that the motor start command has been normally executed (ST6). Here, one of the parallel operations ends.

Next, the other parallel operation will be described. The simulator CPU 115-1 has a command memory 2
The start command in 35 is read to start the motor operation simulation (ST7). In the motor operation simulation, the position detection sensor is turned on (ST
8). Simulator CPU 115-1 writes position detection sensor ON information (sensor information) in sensor memory 233 (ST9). The sensor information written in the sensor memory 233 is transmitted to the CPU ASIC 10 via a serial line.
2a is written to the sensor memory 202 (ST1).
0). The control CPU 101 reads and recognizes the sensor information written in the sensor memory 202 (ST11).
It is determined that the position sensor has been turned on, and the control CPU 101
Is a motor-side ASIC 102a
(ST12). CP
The U-side ASIC 102a sends a motor stop command to the serial line (ST13). Simulator 11
1-1 Command Memory 235 and Command Analysis Unit 22
3 is written with a motor stop command (ST1).
4). From here, the process branches again to the parallel operation.

First, one parallel operation will be described.
The command analysis unit 223 instructs the response memory 234 to send a response to the stop command (S
T15). The response memory 234 stores a response to a preset stop command (normal start).
Is transmitted to the CPU-side ASIC 102a via the serial line (ST16). The control CPU 101 recognizes that the motor stop command has been normally executed (ST1).
7).

Next, the other parallel operation will be described. The simulator CPU 115-1 reads the stop command in the command memory 235 and stops the motor operation simulation (ST18).

Next, the cooperative operation of a plurality of simulators will be described.

The mechanism of the actual machine is composed of a number of elements, each of which includes an actuator such as a motor and a sensor for monitoring the operation of the actuator. The control CPU realizes the function of the entire system by operating them in cooperation. Although the motors of each mechanism are driven independently, the mechanisms may be related to each other.

For example, in the system shown in FIG.
The medium is taken out by the take-in section 301 (unit 1),
Stacking units 302 (unit 2) and 303 (unit 3)
Transported to The capture unit 301 is a unit-side ASI
It is controlled via C313. The control of the accumulation unit 302 is as follows.
It is controlled via the unit-side ASIC 314. The control of the stacking unit 303 is controlled via the unit-side ASIC 315. Therefore, when the medium exits the loading unit 301, the CPU-side ASIC related to the control is also switched.

When such a system is simulated by the simulator, the capturing unit 301 and the integrating unit 30
There is no problem if 2 and 303 are simulated by a single simulator. However, in practice, the simulator hardware provided in one simulator and the execution speed of the simulator are limited. Therefore, it is necessary to use a plurality of simulators in parallel. The system shown in FIG. 8 is just an example.

The problem in this case is timing synchronization between a plurality of simulators. In the actual device, the medium is physically operating (moving). Therefore, immediately after the medium exits the loading unit 301, it is detected by the sensor 306 at the entrance of the stacking unit 302. In the simulator,
In the simulation of the capturing unit 301, it is necessary to transmit the fact that the medium has exited the capturing unit 301 to the simulation of the accumulation unit 302, and to start the operation simulation of the medium in the simulation of the accumulation unit 302.

In the present invention, as shown in FIGS. 8 and 9, each simulator hardware is a C object to be controlled.
Hardware (reception function) for monitoring not only the serial I / F to the PU ASIC but also the serial I / F of another CPU ASIC is provided. This corresponds to the address synchronization signal receiving unit 228, the serial / parallel converters 229, 230, 231, and 2
32, a command memory 239, a sensor memory 240, a response memory 241, and a port memory 242.

Next, with reference to FIGS. 11 and 12, a method for realizing synchronization between simulators by the reception function will be described.

First, with reference to FIG. 11, a control flow in the actual machine will be described. Media capture control and capture unit 3
The transport control up to the exit No. 01 is performed by the CPU-side ASIC 317.
And the control CPU 3 via the unit-side ASIC 313
16. First, the feeder 310 is controlled by the control program executed by the control CPU 316, the medium is sent out to the transport path, and the sensor 304 and the sensor 305 monitor the passage of the medium. When the medium passage is detected by the sensor 305, the process shifts to control of the stacking unit 302.

The control of the accumulation unit 302 is performed by the ASIC
Control C via the ASIC 318 and the unit side ASIC 314
This is performed by the PU 316. In the stacking unit 302, the passage of the medium conveyed from the loading unit 301 is monitored by the sensor 306. When the passage of the medium is detected by the sensor 306, and the medium is to be accumulated in the stacker 311, the gate 320 is driven to accumulate the medium in the stacker 311. If this medium is to be transported to the stacking unit 303, the gate 32
This medium is conveyed to the stacking unit 303 without driving 0.

The control of the stacking unit 303 is performed by the ASIC on the CPU side.
Control C via the ASIC 318 and the unit side ASIC 315
This is performed by the PU 316. The basic operation of the stacking unit 303 is the same as that of the stacking unit 302.

Next, the flow of control in the simulator will be described with reference to FIG. As shown in FIG. 12, the take-out unit simulator 404 and the accumulation unit simulator 40
5. The integration unit simulator 406 is independent. The accumulation unit simulator 405 and the accumulation unit simulator 406 are both connected to the CPU-side ASIC 318. The two accumulation units may be combined into one simulator so as to simulate the two accumulation units. However, the simulator processing capacity may be insufficient, and individual simulators are more flexible. Control C
PU 316, CPU-side ASIC 317, CPU-side ASI
C318 is the same as the actual machine.

First, the control CPU 316 determines whether the CPU side AS
When attempting to control the capturing unit 301 via the IC 317 and the unit-side ASIC 313, the extracting unit simulator 404 is actually performed via the CPU-side ASIC 317.
The simulator hardware 407 receives a command such as a motor drive command, and a simulation of a take-out operation is started. As a result, the take-out unit simulator 404 simulates taking-out of the medium, reaching and passing the sensor of the actual machine, and outputs a signal corresponding to the sensor output according to the state of the simulation to the CPU ASIC 31
7 is transmitted. The control CPU 316 executes control in exactly the same manner as when a medium is taken out by an actual machine and passes through each sensor. After performing the simulation up to the passage of the sensor in the extraction unit simulator 404, the integration unit simulator 405 takes over the simulation.

A separate monitoring terminal of the simulator hardware 409 of the integration unit simulator 405 is connected to the CPU-side ASIC 31.
7 serial lines. The integration unit simulator 405 can monitor control information from the CPU side such as a port on / off signal exchanged between the CPU side ASIC 317 and the extraction unit simulator 404, and a simulation result such as a sensor on / off signal. . The accumulation unit simulator 405 recognizes the timing of the passage of the medium by the above-described mechanism, and starts the simulation of the medium conveyance by the accumulation unit simulator 404 after a certain delay from the passage.

Subsequently, the simulator hardware 407, 40
Details of 9, 411 will be described.

First, selection of an address will be described.
In the actual machine, for example, for one CPU-side ASIC,
Up to 16 unit-side ASICs can be connected. The ASICs on all units are connected to C via a serial line.
Connected to PU side ASIC. The address data transmitted from the CPU-side ASIC is input to the unit-side ASIC via a serial line. Then, a specific unit-side ASIC is selected by the address data. The specific unit-side ASIC selected is:
Start sending and receiving data. Similarly, the simulator hardware is selected by the address.

The simulator CPU 115-1 shown in FIG.
Writes the designated address in the self address holding unit 270. The address comparing unit 271 is an address synchronization signal receiving unit 2
20 compares the received address data with the address held by the self address holding unit. If the addresses match, the parallel / serial converters 221 and 222
, And a reception permission signal to the serial / parallel converter. With this operation, it is possible to simulate the unit control of the address written in the self address holding unit 270. The self address holding unit 270 can hold a plurality of addresses (up to 16 addresses).
), And the simulation of the mechanism controlled by the plurality of unit-side ASICs can be performed by one simulator.

Second, reception of a command will be described.
Commands from the CPU-side ASIC are transmitted at short intervals. For example, the period is 128 μsec. For this reason,
A case occurs where the simulator software cannot receive the command. Therefore, the command memory 235 has a memory area capable of holding a plurality of commands inside, and can continue operation without generating a command reception error even if reading of commands by the simulator software is slightly delayed. . Further, when the reading of the simulator software is sent, the next command is sent before the command memory 235 is read, and the contents of the command memory 235 may be overwritten. In this case, the command is not received by the simulator, and the simulation result becomes abnormal. Therefore, it is necessary to display the abnormality. Specifically, there are provided a write counter 260 for counting the writing from the serial / parallel converter 224 and a read counter 261 for counting the reading from the simulator CPU 115-1. When the difference between the count values of the two counters exceeds the number of commands that can be stored in the command memory 235, the comparator 262 holds an error. After the end of the simulation, the simulator checks the content of the comparator 262, and if an error is held, displays the occurrence of the error.

Third, transmission of a response will be described. The unit ASIC of the actual device analyzes the command received by the command analysis unit 26 in FIG. 6, controls the selector 32 based on the analysis result, and sends out response data. The response data is a result of the operation of the unit-side ASIC, and the response data is transmitted in a very short time because only the data already held is transmitted. For example, 200 ns
c. Actual machine CPU side ASIC and unit side ASI
Communication between C is a fixed protocol in which response reception starts immediately after command transmission (FIG. 13).
reference). If the response is delayed, the ASIC on the CPU side generates an error. For this reason, it is difficult for the simulator software to perform the response sending process following the command reception.

The simulator hardware stores response contents in the response memory 238 in advance. Upon receiving the command, the command analysis unit 223 automatically selects a corresponding response from the response memory and sends it.

Fourth, transmission of sensor on / off information will be described. Unit side ASIC to CPU side ASIC
The transmission of the sensor on / off signal to the sensor must be as short as possible in order not to reduce the monitoring time accuracy of the sensor. For example, if the transmission interval of the sensor ON / OFF signal is 1 msec, the time required for the CPU ASIC to recognize a change in the sensor state varies in 1 msec (error occurs). In the actual machine, for example, the transmission interval of the sensor ON / OFF signal is 128 μsec.

However, in the simulation on the simulator, the execution time varies depending on the conditions, and
It is difficult to maintain a transmission interval of 28 μsec. Therefore, in the present invention, the simulator CPU 115-
1 is stored in the sensor memory 233, and the simulator CPU 115-1 stores the sensor information (on / off information).
Until the device updates the contents of the sensor memory 233, the sensor information previously written in the sensor memory 233 is transmitted. This can prevent a malfunction based on the sensor signal as viewed from the control CPU side.

Further, as shown in FIG. 14, a simulator and a real machine mechanism may be mixed. FIG.
With the configuration shown in (1), it is possible to simulate only a part of the mechanism constituting the system by the simulator, and to confirm the operation of the entire system by using the actual mechanism of the other machine as it is. The simulator, as described above,
The operation of other simulators can be monitored. That is, in the configuration shown in FIG. 14, the simulator can monitor the operation of the actual device, and can perform the simulation while maintaining the synchronization with the operation of the actual device.

According to the application example described above, the following effects can be obtained.

Simulating the ASIC on the unit side of the mechanism control hardware and making it possible to connect to the ASIC on the CPU via a serial line, without modifying the control hardware of the actual machine, as if the units were connected as if the units were connected. Can simulate operation.

When a plurality of simulators are used, the control information and the sensor change information from the control CPU can be mutually monitored by the simulators, and their operations can be synchronized.

When a plurality of CPU-side ASICs are used, the above-mentioned mutual monitoring cannot be performed because the serial lines are individual. However, by equipping each simulator with a function of monitoring other serial lines, the same CPU side ASIC is provided. ASIC
The operation can be synchronized in the same manner as when connected to.

[0113]

According to the present invention, the control program can be debugged as if the actual machine was not completed even if the actual machine was not completed, and the control program was verified by arbitrarily generating various abnormal states. Capable of providing a simulator and a simulating method.

[Brief description of the drawings]

FIG. 1 is a diagram showing an example of a schematic configuration of actual hardware for explaining debugging using an actual device.

FIG. 2 is a diagram illustrating a schematic configuration of a simulator for explaining debugging without using an actual device.

FIG. 3 is a diagram for explaining the operation of the simulator shown in FIG. 2 (operation such as reading / writing to / from a register);

FIG. 4 is a diagram showing an interrupt process by a control program.

FIG. 5 is a diagram showing task processing by a control program.

FIG. 6 is a diagram illustrating an example of an actual machine.

FIG. 7 is a diagram illustrating an example of a schematic configuration of actual hardware (in a case where there are a plurality of units) for explaining debugging using the actual device;

FIG. 8 is a diagram illustrating a schematic configuration of a simulation system (when there are a plurality of simulators) for explaining debugging without using an actual machine.

9 is a diagram showing in detail an internal configuration of a CPU-side ASIC and a simulator in the simulation system shown in FIG. 8;

FIG. 10 is a flowchart showing the operation of the simulation system.

FIG. 11 is a diagram schematically illustrating an actual device including a capturing unit and a plurality of accumulation units.

FIG. 12 is a diagram schematically showing the simulation system of the actual machine shown in FIG. 11;

FIG. 13 is a diagram showing a communication format.

FIG. 14 is a diagram illustrating an example of a simulation system in which a simulator and a real machine are mixed.

FIG. 15 is a flowchart illustrating a simulation method.

[Explanation of symbols]

 101: Control CPU 102: ASIC (CPU side) 103: ASIC (unit side) 104: Serial line 105: Motor 106: Solenoid 107: Sensor 111: Personal computer 112: Simulator board 113: Control CPU 114: Simulator hardware 114a: Register Group 115: CPU (PC side) 116: PCI bus

Claims (29)

[Claims] 1. A simulation CPU, a memory readable from one of a control CPU connected to the simulator and the simulation CPU, and readable from the other, and a memory written from the control CPU to the memory. A simulator comprising: means for reading control information by the simulation CPU; and means for writing a result of executing a simulation based on the control information to the memory so as to be readable from the control CPU. 2. A simulation CPU, a control CPU to which the simulator is connected, and a memory readable from one of the control CPU and the simulation CPU, and connected to the simulation CPU and the memory. Connecting means for connecting the control information written in the memory from the control CPU to the simulation CP via the connecting means.
U. A simulator, comprising: means for reading by U; and means for writing the result of executing a simulation based on the control information to the memory via the connection means so as to be readable from the control CPU. 3. The simulator according to claim 1, wherein the simulation CPU requests an interrupt to the control CPU after writing the result of the simulation into the memory. 4. A control CPU to which the simulator is connected
A first memory in which control information is written from the first memory; a second memory in which information can be read from the control CPU; a unit for reading control information from the first memory; A simulator comprising: means for generating control result information; and means for writing the generated control result information to the second memory. 5. The simulator according to claim 4, further comprising means for transmitting an interrupt to the control CPU after writing a result of the simulation into the second memory. 6. A control CPU writes control information in a first memory, a simulation CPU reads out the control information written in the first memory through connection means, and the simulation CPU reads the control information. Executing a simulation based on the above, writing the simulation result to the second memory via the connection means by the simulation CPU, and reading the simulation result written to the second memory by the control CPU. Simulation method to be characterized. 7. A control CPU to which the simulator is connected
A first memory to which a command is written from the first memory; a second memory from which information can be read from the control CPU; a means for reading a command from the first memory; and a response based on the read command. And a means for writing the generated response to the second memory. 8. A control CPU to which the simulator is connected
A memory from which information can be read from a memory; and a means for periodically writing a sensor state to the memory. 9. A control CPU to which the simulator is connected
A first memory in which a command is written from the control CPU; and second and third readable information from the control CPU.
A means for reading a command from the first memory; a means for generating a response based on the read command; a means for writing the generated response to the second memory; Means for periodically writing the sensor status to the memory of (3). 10. A control CP to which the simulator is connected
A first memory in which on / off of an output port is written from U; a second memory in which a command is written from the control CPU; and third and fourth readable information from the control CPU.
A means for reading on / off of an output port from the first memory; a means for reading a command from the second memory; a means for generating a response based on the read command; A simulator comprising: means for writing the generated response to the third memory; and means for periodically writing the sensor state to the fourth memory. 11. The apparatus according to claim 3, further comprising: a counting unit for counting the interrupt; and a transmitting unit for transmitting data for timeout based on a count value of the counting unit. Simulator described. 12. The simulation method according to claim 6, wherein the simulation CPU requests an interrupt to the control CPU after writing the result of the simulation into the second memory. . 13. The simulation method according to claim 12, wherein said interrupt is counted, and timeout data is transmitted based on the count value of the interrupt. 14. The simulator according to claim 8, further comprising interrupt request means for requesting an interrupt to said control CPU after writing a sensor state to said memory. 15. A unit in a device for transmitting command information from the main unit to the unit, transmitting the execution of the command from the unit as a response to the main unit, and transmitting sensor information from the unit to the main unit. A command memory that holds the command information transmitted from the main body and can be read from the CPU of the unit, a sensor memory that can write the sensor information from the CPU of the unit, Means for transmitting the sensor information written in the sensor memory to the main body; response memory in which response information can be written from the CPU of the unit; and means for transmitting the response information written in the response memory to the main body. A simulator comprising: 16. A first simulator and a second simulator connected to the main body for simulating the operation of the unit, wherein the second simulator receives sensor information transmitted from the first simulator to the main body. A simulator comprising receiving means, wherein the second simulator operates in synchronization with the first simulator based on the received sensor information. 17. A simulator for an apparatus for transmitting command information from a main unit to a unit, transmitting a command execution structure from the unit as a response to the main unit, and transmitting sensor information from the unit to the main unit. A first simulator for simulating the operation of the unit, wherein the first simulator holds the command information transmitted from the main unit and is readable by the CPU of the unit; A sensor memory in which sensor information can be written from the CPU on the side, means for transmitting the sensor information written in the sensor memory to the main body, a response memory in which response information can be written from the CPU on the unit side, Response information written to the device is transmitted to the main unit That means and, and means for receiving the sensor information of the second simulator, this received sensor information, simulators, characterized in that operates in synchronization with the operation of the second simulator. 18. The first simulator holds port information transmitted from a main body side,
18. The simulator according to claim 16, further comprising a port memory readable by a CPU of the unit. 19. An address memory for storing a self address in advance, and comparing means for comparing the self address stored in the address memory with a designated address specified by the main unit, wherein the comparison result by the comparing means 16. The simulator according to claim 15, wherein when the addresses match, the sensor information, the command information, and the response are transmitted. 20. A unit in a device for transmitting command information from the main unit to the unit, transmitting the execution result of the command from the unit as a response to the main unit, and transmitting sensor information from the unit to the main unit. A first command memory that holds command information transmitted from the main unit through the first system and is readable from the unit-side CPU; A sensor memory in which sensor information can be written, and the sensor information written in the sensor memory
Means for transmitting the response information from the CPU of the unit to the main body via the system; and the response information written in the response memory to the main body via the first system. And a second command memory that holds command information transmitted from the main unit via the second system and is readable from the CPU of the unit. 21. A first simulator connected to the main body via a first system, and a second simulator connected to the main body via a second system. The second simulator has means for receiving sensor information transmitted from the first simulator to the main body via the first system, and the second simulator has a first simulator and a second simulator based on the received sensor information. Operating in synchronization with each other, the first simulator has means for receiving sensor information transmitted from the second simulator to the main body via the second system, A simulator that operates in synchronization with a second simulator based on information. 22. A simulator for an apparatus for transmitting command information from the main unit to the unit, transmitting the execution of the command from the unit as a response to the main unit, and transmitting sensor information from the unit to the main unit. A simulator for simulating the operation of the unit, wherein the first simulator holds the command information transmitted from the main unit via the first system and reads out the command information from the CPU of the unit. A first command memory that can be used; a sensor memory that can write sensor information from a CPU on the unit side;
Means for transmitting the response information from the CPU of the unit to the main body via the system; and the response information written in the response memory to the main body via the first system. Means for holding command information transmitted from the main unit side via the second system, a second command memory readable from the CPU on the unit side, and means for receiving sensor information of the second simulator. A simulator that operates in synchronization with the operation of the second simulator based on the received sensor information. 23. The first simulator holds port information transmitted from the main unit via the first system, reads port data from a CPU on the unit side, and communicates with the second simulator via the second system. 23. The simulator according to claim 21, further comprising: a port memory that retains port information transmitted from the main body side and is readable from a CPU of the unit side. 24. A unit in a device for transmitting command information from the main unit to the unit, transmitting the execution of the command from the unit as a response to the main unit, and transmitting sensor information from the unit to the main unit. Is a method of simulating the operation of the device, wherein the command information transmitted from the
A simulation method comprising: maintaining a state readable from a PU; and transmitting sensor information and response information written from a CPU on a unit side to a main body side. 25. A method in a simulator including a first simulator and a second simulator, wherein the second simulator receives sensor information transmitted from the first simulator to the main body, and includes a second simulator. Operates in synchronization with a first simulator based on received sensor information. 26. A simulator for an apparatus for transmitting command information from a main unit to a unit, transmitting a command execution structure from the unit as a response to the main unit, and transmitting sensor information from the unit to the main unit. A method for simulating the operation of a unit having at least two units, wherein a first simulator transmits command information transmitted from a main unit to a C
The sensor information and the response information written from the CPU on the unit side are transmitted to the main body side, and the sensor information of the second simulator is received. A simulation method that operates in synchronization with the operation of the simulator. 27. A unit in a device for transmitting command information from the main unit to the unit, transmitting the execution of the command from the unit as a response to the main unit, and transmitting sensor information from the unit to the main unit. Which simulates the operation of the above, the command information transmitted from the main body through the first system,
And command information transmitted from the main unit via the second system in a state where the command information can be read from the CPU on the unit side, and the sensor information and response information written from the CPU on the unit side are stored in the first system. Transmitting to the main body via the computer 28. A method in a simulator including a first simulator, a second simulator, and a main body, wherein the second simulator receives sensor information transmitted from the first simulator to the main body, The second simulator operates in synchronization with the first simulator based on the received sensor information. The first simulator receives the sensor information transmitted from the second simulator to the main body side. And operating in synchronization with a second simulator based on the received sensor information. 29. A simulator for an apparatus for transmitting command information from a main unit to a unit, transmitting the execution result of the command from the unit as a response to the main unit, and transmitting sensor information from the unit to the main unit. A simulator for simulating the operation of the unit side, wherein the first simulator comprises: command information transmitted from the main unit via the first system; and The transmitted command information is held in a readable state from the unit side CPU, the sensor information and the response information written from the unit side CPU are transmitted to the main body side, and the sensor information of the second simulator is received. Operating according to the received sensor information in synchronization with the operation of the second simulator. Shon way.