JP2001325577A - Information recording medium - Google Patents

Information recording medium

Info

Publication number
JP2001325577A
JP2001325577A JP2000145223A JP2000145223A JP2001325577A JP 2001325577 A JP2001325577 A JP 2001325577A JP 2000145223 A JP2000145223 A JP 2000145223A JP 2000145223 A JP2000145223 A JP 2000145223A JP 2001325577 A JP2001325577 A JP 2001325577A
Authority
JP
Japan
Prior art keywords
card
chip
recording medium
information recording
chips
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2000145223A
Other languages
Japanese (ja)
Inventor
Takeo Kusumi
武生 楠見
Toshihisa Inabe
敏久 稲部
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Tokin Corp
Original Assignee
Tokin Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokin Corp filed Critical Tokin Corp
Priority to JP2000145223A priority Critical patent/JP2001325577A/en
Publication of JP2001325577A publication Critical patent/JP2001325577A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124—Aluminium (Al) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors

Landscapes

  • Credit Cards Or The Like (AREA)

Abstract

PROBLEM TO BE SOLVED: To reduce the breakage when a card type information recording medium having an IC bare chip inside is bent. SOLUTION: The functions given to one conventional IC bare chip are divided to different chips to reduce the size of the chips and also make the distances between the chips larger than the thickness of the chips, thereby reducing the damage to the chips when the card is bent to deform.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【発明の属する技術分野】本発明は、ＩＣベアチップな
どの回路素子を配線基板に実装した状態で、カード形状
の担体に埋設した、情報記録媒体に関するものである。
更に詳しくは、前記カード形状の記録媒体の、曲げ変形
に対する信頼性を向上させる技術に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information recording medium in which circuit elements such as an IC bare chip are mounted on a wiring board and embedded in a card-shaped carrier.
More specifically, the present invention relates to a technique for improving the reliability of the card-shaped recording medium against bending deformation.

【０００２】[0002]

【従来の技術】ＩＣベアチップなどを内蔵したカード形
状の記録媒体において、従来、埋設されるＩＣベアチッ
プは、１個のベアチップの中に、マイクロコンピュー
タ、プログラム、メモリなどの全機能を具備しており、
そのサイズは概ね一辺が５ｍｍ程度と比較的大きなもの
であり、カードが折り曲げられた際に、破損することが
あった。2. Description of the Related Art Conventionally, in a card-shaped recording medium having a built-in IC bear chip, an embedded IC bear chip has all functions such as a microcomputer, a program, and a memory in one bare chip. ,
The size of the card is relatively large, about 5 mm on a side, and the card may be damaged when bent.

【０００３】その対策として、ベアチップに曲げ応力が
加わらないように、例えばチップを金属板などに挟みこ
んで補強したり、機能別に分離したベアチップを厚み方
向に重ねたりして、曲げ強度を向上させるという手段が
とられていた。しかし、これら従来の対策では、製造プ
ロセスが極めて煩雑となり、コスト高となることが大き
な欠点であった。[0003] As a countermeasure, the bending strength is improved by, for example, sandwiching the chip between metal plates or the like or reinforcing the bare chips separated according to their functions in the thickness direction so that bending stress is not applied to the bare chips. That means was taken. However, these conventional measures have a serious drawback in that the manufacturing process becomes extremely complicated and the cost is increased.

【０００４】[0004]

【発明が解決しようとする課題】従って、本発明の技術
的課題は、上記従来の情報記録媒体の問題点を改善し、
外力による曲げ変形を生じても、破損することが少ない
カード形状の情報記録媒体を、低コストで提供すること
にある。SUMMARY OF THE INVENTION Accordingly, the technical problem of the present invention is to improve the above-mentioned problems of the conventional information recording medium,
An object of the present invention is to provide a card-shaped information recording medium that is less likely to be damaged even when bending deformation occurs due to external force, at low cost.

【０００５】[0005]

【課題を解決するための手段】本発明は、ＩＣベアチッ
プのサイズを小さくすることにより、それが内蔵される
カードが曲げられても、ＩＣベアチップの破損が少なく
なることに着目して、ＩＣベアチップのサイズと配置方
法の最適化を検討した結果なされたものである。SUMMARY OF THE INVENTION The present invention focuses on reducing the size of an IC bare chip so that damage to the IC bare chip is reduced even when a card in which it is built is bent. This is the result of studying the optimization of the size and arrangement method.

【０００６】即ち本発明は、マイクロコンピュータ、プ
ログラム記録装置、メモリの機能を具備したＩＣベアチ
ップを埋設したカード形状の情報記録媒体において、Ｉ
Ｃベアチップを機能毎に個別のベアチップに分離し、カ
ード内に一定の距離をおいて埋設してなることを特徴と
する情報記録媒体である。That is, the present invention relates to a card-shaped information recording medium in which an IC bear chip having a function of a microcomputer, a program recording device, and a memory is embedded.
An information recording medium characterized in that a C bare chip is separated into individual bare chips for each function and is embedded at a certain distance in a card.

【０００７】また本発明は、前記の情報記録媒体におい
て、前記個別のベアチップ同士の距離はベアチップ自体
の厚さ以上であることを特徴とする情報記録媒体であ
る。[0007] The present invention is also the information recording medium, wherein the distance between the individual bare chips is equal to or greater than the thickness of the bare chips themselves.

【０００８】[0008]

【作用】一般に、部材に荷重が加わった場合の曲げモー
メントは、荷重が加わった位置からの距離に比例する。
従って、ＩＣベアチップの場合においても、チップを内
蔵したカードを同じ曲率で曲げた場合、チップのサイズ
が小さい方が破損は少なくなる。このため、必要な機能
毎に別個のチップを構成することでチップサイズを小さ
くし、これを内蔵した情報記録媒体の信頼性を向上する
ことができる。In general, the bending moment when a load is applied to a member is proportional to the distance from the position where the load is applied.
Therefore, even in the case of an IC bare chip, when a card containing a chip is bent at the same curvature, the smaller the chip size, the less the damage. Therefore, by forming a separate chip for each required function, the chip size can be reduced, and the reliability of the information recording medium incorporating the chip can be improved.

【０００９】また、ＩＣベアチップ同士の距離を、チッ
プ自体の厚さ以上とすることで、情報記録媒体が直角程
度に折り曲げられても、チップ同士が接触することなく
なる。従って、チップの破損がより少なくなり、情報記
録媒体の信頼性を向上することができる。Further, by setting the distance between the IC bare chips to be equal to or greater than the thickness of the chips themselves, the chips do not come into contact with each other even if the information recording medium is bent at a right angle. Therefore, breakage of the chip is further reduced, and the reliability of the information recording medium can be improved.

【００１０】[0010]

【発明の実施の形態】以下、本発明の実施の形態につい
て図を参照しながら説明する。Embodiments of the present invention will be described below with reference to the drawings.

【００１１】図１は、ＩＣベアチップを機能別の小サイ
ズに分離した状態を示す斜視概略図である。図中、１
は、マイクロコンピュータチップ、２はプログラムチッ
プ、３はメモリチップを示す。この場合のチップの形状
は、厚さが０.１５ｍｍで、一辺が約２ｍｍの略正方形
の板である。FIG. 1 is a schematic perspective view showing a state in which an IC bare chip is separated into small sizes according to functions. In the figure, 1
Indicates a microcomputer chip, 2 indicates a program chip, and 3 indicates a memory chip. The shape of the chip in this case is a substantially square plate having a thickness of 0.15 mm and a side of about 2 mm.

【００１２】図２は、フィルムキャリア５上に形成され
ている回路パターン４上に、前記各個別ベアチップ１、
２、３を銀ペーストなどの導電性接着剤６よって接着さ
れ、各ベアチップの電極パッド７と、回路基板の電極パ
ッド群８とＡｌなどのボンディングワイヤー９よって接
続されて、ＩＣモジュールを完成した状態を示す。な
お、ここでは、非接触ＩＣカードにおける構成部品であ
るアンテナコイルや、接触式カードにおける外部との接
点電極などについては本発明の内容とは関係が薄いので
省略した。FIG. 2 shows the individual bare chips 1, 2 on a circuit pattern 4 formed on a film carrier 5.
2 and 3 are bonded by a conductive adhesive 6 such as a silver paste, and are connected to the electrode pads 7 of each bare chip, the electrode pads 8 of the circuit board and the bonding wires 9 of Al or the like to complete an IC module. Is shown. Here, the antenna coil, which is a component in the non-contact IC card, the contact electrode with the outside in the contact type card, and the like are omitted because they have little relation to the contents of the present invention.

【００１３】図３は、ＩＣモジュールの断面を示したも
ので、ＩＣモジュールを半導体用ジャンクションコーテ
ィングレジンなどの被覆材１０で封止した後、例えばポ
リエチレンテレフタレートなどのコアシート１１、１
１′及びオーバーシート１２で挟み込み、熱プレスで埋
設一体化、あるいはエポキシ樹脂接着剤などで貼り合わ
せ一体化を行って、ＩＣカードの基本構造を完成した状
態を示す。なお、ここではＩＣベアチップ間の距離を、
チップ厚さよりも長くしている。FIG. 3 shows a cross section of the IC module. After sealing the IC module with a coating material 10 such as a junction coating resin for semiconductors, a core sheet 11 such as polyethylene terephthalate is used.
1 shows a state in which the basic structure of the IC card is completed by sandwiching between 1 'and the oversheet 12 and embedding and integrating with a hot press or bonding and integrating with an epoxy resin adhesive or the like. Here, the distance between the IC bare chips is
It is longer than the chip thickness.

【００１４】ここで、前記のＩＣカードと、従来の１個
のＩＣベアチップを用いたＩＣカードの曲げ変形に対す
る信頼性を確認するために、一定の曲率で各ＩＣカード
を曲げたときの不良発生率を調査した。図４は、その結
果を示したものである。前記のＩＣカードの不良発生率
を１３、従来のＩＣカードの不良発生率を１４で示し
た。ここで用いた従来のＩＣカードのＩＣベアチップの
形状は、厚さが０.１５ｍｍで、一辺が約５ｍｍの略正
方形の板である。Here, in order to confirm the reliability of the above-mentioned IC card and a conventional IC card using one IC bear chip against bending deformation, occurrence of a defect when each IC card is bent at a constant curvature. The rates were investigated. FIG. 4 shows the result. The defect occurrence rate of the above-mentioned IC card is indicated by 13, and the defect occurrence rate of the conventional IC card is indicated by 14. The shape of the IC bare chip of the conventional IC card used here is a substantially square plate having a thickness of 0.15 mm and a side of about 5 mm.

【００１５】図４から明らかなように、同程度の曲率に
変形した場合、内蔵しているＩＣベアチップが小さい方
が、不良発生率は低い。なお、本実施の形態では、回路
パターンとＩＣベアチップとの接続をボンディングワイ
ヤーで行った例を示したが、例えば回路パターンの電極
パッドとＩＣベアチップの電極パッドとを直接接続す
る、いわゆるバンプボンディングによっても、同様の効
果が得られることは勿論である。As apparent from FIG. 4, when the curvature is changed to the same degree, the smaller the built-in IC bear chip, the lower the defect occurrence rate. In this embodiment, an example in which the connection between the circuit pattern and the IC bare chip is performed by a bonding wire has been described. However, for example, a so-called bump bonding is used to directly connect the electrode pad of the circuit pattern and the electrode pad of the IC bare chip. Of course, the same effect can be obtained.

【００１６】[0016]

【発明の効果】以上に説明したように、本発明によるカ
ード形状情報記録媒体では、従来のＩＣベアチップのサ
イズが５ｍｍ角程度のワンチップカードに比べ、各機能
別ベアチップのサイズを、各々２ｍｍ角程度以下にして
いるため、カードの折り曲げた際の損傷が著しく少なく
なる。As described above, in the card-shaped information recording medium according to the present invention, the size of the bare chip for each function is reduced to 2 mm square compared with the conventional one-chip card having the IC bare chip size of about 5 mm square. Because of this, the damage when the card is bent is significantly reduced.

【図面の簡単な説明】[Brief description of the drawings]

【図１】本発明による機能別ＩＣベアチップの概略図。FIG. 1 is a schematic diagram of a functional IC bare chip according to the present invention.

【図２】本発明によるＩＣモジュール斜視図。FIG. 2 is a perspective view of an IC module according to the present invention.

【図３】本発明によるＩＣカードの断面の概略図。FIG. 3 is a schematic view of a cross section of an IC card according to the present invention.

【図４】本発明のＩＣカードを曲げた時の不良発生率を
示すグラフ。FIG. 4 is a graph showing a defect occurrence rate when the IC card of the present invention is bent.

【符号の説明】[Explanation of symbols]

１ マイクロコンピュータＩＣベアチップ ２ プログラムＩＣベアチップ ３ メモリＩＣベアチップ ４ 回路パターン ４′ 引出しパターン ５ フィルムキャリア ６ 導電性接着剤 ７ 各ＩＣベアチップの電極パッド ８ 回路基板の電磁パッド ９ ボンディングワイヤー １０ 被覆材 １１、１１′ コアシート １２ オーバーシート １３ 本発明のＩＣカードの不良発生率 １４ 従来のＩＣカードの不良発生率 DESCRIPTION OF SYMBOLS 1 Microcomputer IC bare chip 2 Program IC bare chip 3 Memory IC bare chip 4 Circuit pattern 4 'Leader pattern 5 Film carrier 6 Conductive adhesive 7 Electrode pad of each IC bare chip 8 Electromagnetic pad of circuit board 9 Bonding wire 10 Coating material 11, 11 ′ Core sheet 12 Oversheet 13 Failure rate of IC card of the present invention 14 Failure rate of conventional IC card

Claims (2)

【特許請求の範囲】[Claims] 【請求項１】 マイクロコンピュータ、プログラム記憶
装置、メモリの機能を具備したＩＣベアチップを埋設し
たカード形状の情報記録媒体において、ＩＣベアチップ
を機能毎に個別のベアチップに分離し、カード内に一定
の距離をおいて埋設してなることを特徴とする情報記録
媒体。In a card-shaped information recording medium in which an IC bear chip having functions of a microcomputer, a program storage device, and a memory is embedded, the IC bear chip is separated into individual bear chips for each function, and a predetermined distance is provided in the card. An information recording medium characterized by being buried in the medium. 【請求項２】 請求項１に記載の情報記録媒体におい
て、前記個別のベアチップ同士の距離はベアチップ自体
の厚さ以上であることを特徴とする情報記録媒体。2. The information recording medium according to claim 1, wherein a distance between the individual bare chips is equal to or greater than a thickness of the bare chip itself.
JP2000145223A 2000-05-17 2000-05-17 Information recording medium Pending JP2001325577A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2000145223A JP2001325577A (en) 2000-05-17 2000-05-17 Information recording medium

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2000145223A JP2001325577A (en) 2000-05-17 2000-05-17 Information recording medium

Publications (1)

Publication Number Publication Date
JP2001325577A true JP2001325577A (en) 2001-11-22

Family

ID=18651760

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2000145223A Pending JP2001325577A (en) 2000-05-17 2000-05-17 Information recording medium

Country Status (1)

Country Link
JP (1) JP2001325577A (en)

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