JP2001319496A - Semiconductor memory and its test method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve such a problem that since data are read out alternately and repeatedly from memory cells arranged on a word line physically adjacently by an extensive number of times, an extensive time is required for test time. SOLUTION: This device is provided with a memory cell selecting means which makes prescribed plural word lines out of plural word lines constituting a memory cell array a selection-state and sets plural memory cells corresponding to the prescribed plural word lines to a read-out enable state, and a memory cell test means for testing stability of write-in contents of the memory cell by repeatedly reading out write-in contents of the plural memory cells made to the read-out enable state for a prescribed number of times.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory circuit device incorporated in a microcomputer, and more particularly to a semiconductor memory circuit device capable of performing a test for stability of written contents efficiently in a short time and a test thereof. It is about the method.

[0002]

2. Description of the Related Art A semiconductor memory circuit device, for example, an SR built in a microcomputer (hereinafter abbreviated as "microcomputer").
A test for examining the stability of the written contents of an AM (static RAM) is important in seeing the quality.

FIG. 11 schematically shows a structure of a conventional SRAM. In the figure, reference numerals 1 to 3 denote memory cells constituting a memory cell array 11, which are provided at intersections of a plurality of word lines and a plurality of bit lines arranged orthogonally in a matrix. Reference numeral 11 denotes a memory cell array including a plurality of word lines and a plurality of bit lines and memory cells 1 to 3 arranged orthogonally in a matrix, and 12 denotes a predetermined memory from a CPU (not shown) to the SRAM. Upon receiving an address signal corresponding to a cell, an X decoder 13 outputs a decode signal to a word line provided with the predetermined memory cell and sets the selected memory cell to a selected state.
When an address signal corresponding to a predetermined memory cell is received from a CPU (not shown), a decode signal corresponding to a bit line provided with the predetermined memory cell is supplied to selector 1.
4 receives a decode signal from the Y decoder 13, outputs a signal to a bit line provided with a predetermined memory cell, and sets a selector to a selected state.
This is a sense amplifier that amplifies a signal output from a memory cell on an intersection of a word line and a bit line selected by the decoder 12, the Y decoder 13, and the selector 14.

Next, the operation will be described. Here, S
The description of the data storage operation of the RAM is omitted,
A description will be given of a test for the stability of the contents written in the memory cells constituting the AM. First, for example, data having a value of 0 is written to all the memory cells constituting the memory cell array 11. Specifically, all the word lines and bit lines are selected by the X decoder 12, the Y decoder 13, and the selector 14, and all the memory cells constituting the memory cell array 11 are set to the ground potential Vss, and the stored content is set to 0 value.

Next, a CPU (not shown) of the microcomputer
When an address signal corresponding to a predetermined memory cell (in this case, for example, an address signal corresponding to the memory cell 1 of the memory cell array 11) is input to the AM, the X decoder 12
Outputs a decode signal corresponding to the word line having the memory cell (for example, the word line in the first row), and sets it to the selected state. Next, the Y decoder 13 outputs a decode signal corresponding to the bit line having the memory cell (for example, the bit line in the first column) to the selector 14 to set it to the selected state. As a result, the memory cell (for example, the memory cell 1) located at the intersection of the selected word line and bit line is made readable. From the memory cell in the readable state in this way, a signal related to the written content is read via the sense amplifier 15.

The above-described read operation is repeated 128 to 50,000 times alternately for memory cells physically adjacently arranged on a word line of the memory cell array 11. In the illustrated example, first, the read operation of the written content is repeatedly performed alternately on the memory cells 1 and 2. Next, the data is shifted by one bit, and the read operation of the written contents is repeatedly performed alternately on the memory cells 2 and 3.

When the above-described repeated reading operation of the written contents of the memory cells is performed on all the memory cells provided on one word line, the same operation is continuously performed on the memory cells on the next word line. Are repeatedly performed.

When the above-described repetitive read operation is performed on all the word lines constituting the memory cell array, finally, the X decoder 12, the Y decoder 13, and the selector 1
The word line and the bit line are sequentially selected by 4 and all the memory cells constituting the memory cell array 11 are read, and it is confirmed that the written contents of all the memory cells are 0 values, and the test is finished.

The quality of the SRAM can be maintained by checking the stability of the written contents of the SRAM. In the above example, by repeatedly performing the read operation alternately on the memory cells physically adjacently arranged on the word line, the ground potential Vss fluctuates, and the write contents of the memory cells do not show a 0 value. Then, an SRAM having a defective cell is detected as having no predetermined stability.

[0010]

Since the conventional semiconductor memory circuit device is configured as described above, it is arranged physically adjacent to the word line in testing the stability of the written content of the memory cell. There is a problem that a huge amount of time is required for the test time because the memory cells are alternately and repeatedly read a huge number of times.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems, and a plurality of memory cells constituting a memory cell array are simultaneously selected to repeatedly perform a read operation, thereby stabilizing the write contents of the memory cells. It is an object of the present invention to obtain a semiconductor memory circuit device capable of efficiently performing the test in a short time and a test method thereof.

[0012]

A semiconductor memory circuit device according to the present invention selects a predetermined plurality of word lines and / or bit lines from a plurality of word lines and / or bit lines constituting a memory cell array, A memory cell selecting means for setting a plurality of memory cells corresponding to a plurality of predetermined word lines and / or bit lines to a readable state; and a plurality of memory cells set to a readable state by the memory cell selecting means. And memory cell testing means for repeatedly reading the written contents a predetermined number of times and testing the stability of the written contents of the memory cells.

In the semiconductor memory circuit device according to the present invention, a predetermined plurality of word lines and / or bit lines are selected from a plurality of word lines and / or bit lines constituting a memory cell array, and a predetermined plurality of word lines and / or bit lines are selected. And / or memory cell selecting means for setting a plurality of memory cells corresponding to bit lines to a readable state, and writing contents of the plurality of memory cells set to a readable state by the memory cell selecting means are repeated a predetermined number of times. A memory cell test means for reading and testing the stability of the written contents of the memory cell; and selecting a memory cell without using the CPU while synchronizing with the operation clock signal of the microcomputer using the start signal received from the CPU as a trigger. Means, and automatic test means for operating the memory cell test means. It is.

In the semiconductor memory circuit device according to the present invention, when all the memory cells in the memory cell array are tested by the automatic test means, the automatic test means transmits an interrupt signal indicating that the test is completed to the CPU.

In a semiconductor memory circuit device according to the present invention, the number of word lines and / or bit lines to be simultaneously selected by the memory cell selecting means is limited so as not to exceed an allowable value of power consumption of the device. It is.

A method for testing a semiconductor memory circuit device according to the present invention includes a data writing step of writing data of the same content to all memory cells forming a memory cell array, a plurality of word lines and / or a plurality of word lines forming a memory cell array.
Alternatively, a memory cell selecting step of setting a predetermined plurality of word lines and / or bit lines from bit lines to a selected state and setting a plurality of memory cells corresponding to the predetermined plurality of word lines and / or bit lines to a readable state. And a memory cell test step of repeatedly reading the write contents of the plurality of memory cells in a readable state in the memory cell select step a predetermined number of times, and testing the stability of the write contents. This operation is repeated until the operation up to the memory cell test step is performed on all the memory cells constituting the memory cell array.

According to a method of testing a semiconductor memory circuit device according to the present invention, a data write step in which a CPU writes data of the same content to all memory cells constituting a memory cell array, and a plurality of word lines and / or a plurality of word lines constituting a memory cell array are provided. Alternatively, a memory cell selecting means for selecting a predetermined plurality of word lines and / or bit lines from bit lines and setting a plurality of memory cells corresponding to the predetermined plurality of word lines and / or bit lines to a readable state. And a memory cell test step of repeatedly reading a predetermined number of times the written contents of the plurality of memory cells that can be read in the memory cell selecting step, and testing the stability of the written contents. The signal is used as a trigger to synchronize with the operation clock signal of the microcomputer. While, without interrupting CPU, in which repeated from the memory cell selecting step up operation to the memory cell test steps are performed for all the memory cells constituting the memory cell array.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below. Embodiment 1 FIG. FIG. 1 is a diagram schematically showing a configuration of a semiconductor memory circuit device according to a first embodiment of the present invention. In FIG. 1, reference numerals 1 to 8 denote memory cells constituting a memory cell array 11, which are provided at intersections between a plurality of word lines and a plurality of bit lines arranged orthogonally in a matrix. Reference numeral 11 denotes a plurality of word lines and a plurality of bit lines arranged orthogonally in a matrix, and memory cells 1 to 8.
, And a memory cell array 12 including an SRAM
When an address signal corresponding to a plurality of predetermined memory cells is received from a CPU (not shown), an X-decoder outputs an H-level decode signal to a word line having the plurality of predetermined memory cells to enter a selected state. Upon receiving an address signal corresponding to a plurality of predetermined memory cells from the CPU (not shown) to the SRAM, the memory cell selecting means 13 outputs an H level signal corresponding to the plurality of bit lines having the predetermined memory cells. A Y decoder (memory cell selecting means) for outputting a decode signal to the OR gate 16; a selector (memory cell selecting means) 14 for selecting a bit line based on the output signal of the OR gate 16; A memory cell on the intersection of a word line and a bit line selected by the Y decoder 13, the selector 14, and the OR gate 16 A sense amplifier for amplifying a signal et output (memory cell test unit).

Reference numeral 16 denotes a plurality of memory cells provided between the Y decoder 13 and the selector 14 corresponding to a plurality of bit lines and having predetermined memory cells based on a control signal inputted from outside via signal lines 17 and 18. OR gates (memory cell selecting means) 17 and 18 for selecting the bit line of the memory cell (memory cell selecting means) for transmitting a control signal input from the outside through a test mode terminal (not shown) to the OR gate 16 In the selection means), an H-level signal corresponding to a value 1 and an L-level signal corresponding to a value 0 are appropriately input as control signals.
Here, the output signal of the OR circuit constituting the OR gate 16 is output to the selector corresponding to the plurality of bit lines in the selector 14, and the bit line receiving the H level signal from the OR circuit is in the selected state. In the illustrated example, an SRAM is used as the semiconductor storage circuit device.

Next, the operation will be described. Since the present invention aims at improving the efficiency of the test for the stability of the contents written in the memory cells constituting the semiconductor memory circuit device, the description of the data storage operation of the semiconductor memory circuit device is omitted. FIG. 2 is a timing chart showing the operation of the stability test of the written contents of the memory cell of the semiconductor memory circuit device according to the first embodiment. In the drawing, reference numerals 17 and 18 indicate the levels of control signals propagating through the signal lines 17 and 18 in FIG. 1 with respect to time. A stability test of the written contents of the memory cells of the semiconductor memory circuit device according to the first embodiment will be described with reference to FIG. First, in a period T21 in FIG. 2, the control signals propagating through the signal lines 17 and 18 are both at the L level corresponding to the 0 value. At this time, the CPU (not shown) writes, for example, data of value 0 to all the memory cells constituting the memory cell array 11. More specifically, C (not shown) is used for the SRAM.
When an address signal corresponding to all memory cells is transmitted from the PU, the X decoder 12 sequentially outputs an H level decode signal to each word line constituting the memory cell array 11 to be in a selected state. Further, the Y decoder 13 sequentially outputs an H level decode signal to each OR circuit constituting the OR gate 16. Since the control signals propagating through the signal lines 17 and 18 are both at the L level, the bit line is selected by the H level decode signal from the Y decoder 13. As a result, the memory cell corresponding to the selected word line and bit line becomes in a writable or readable state, and this memory cell is set to the ground potential Vss.
Then, the operation of setting the stored contents to the 0 value is sequentially performed, and the 0 value is written to all the memory cells (data writing step). When the microcomputer performs a normal operation, the state during the period T21, that is, a state where all the memory cells constituting the memory cell array 11 can be written or read is set.

Next, in a period T22, the control signal propagating through the signal line 17 is set at L level, and the control signal propagating through the signal line 18 is set at H level. At this time, the memory cells 1 and 2 in FIG.
The bit lines corresponding to 3, 5, 7 are selected, and the X decoder 12 sets the word lines in the first row of the memory cell array 11 in FIG.
Since the plurality of memory cells 1, 3, 5, and 7 can be read simultaneously, a signal relating to the write content is output from these, and this is amplified by the sense amplifier 15 and the write content is detected by a detector (not shown). (Memory cell selection step, memory cell test step).

As described above, the memory cells 1, 3, 5,
After detecting the written content of No. 7, the process proceeds to period T23. In the period T23, the control signal propagating through the signal line 17 is set to H level.
The control signal propagating through the signal line 18 is set to L level. At this time, the bit lines corresponding to the memory cells 2, 4, 6, and 8 in FIG. 1 in which the output signal from the OR gate 16 is at the H level are selected, and the X decoder 12 causes the memory cell array 11 in FIG. Is set to the selected state, the memory cells 2, 4, 5, 7 physically adjacent to the memory cells 1, 3, 5, 7 from which the read operation was performed in the period T22. Since signals 6 and 8 are simultaneously readable, a signal relating to the contents to be written is outputted therefrom, amplified by the sense amplifier 15 and inspected for the contents to be written by a detector (not shown) (memory cell selection step, Memory cell test step).

Thereafter, as shown in a period T24, control signals propagating through the signal lines 17 and 18 are alternately changed to H level and L level.
To level. The level change of the control signal propagating through the signal lines 17 and 18 is periodically performed a predetermined number of times, for example, 128 to 50,000 times in accordance with the specification of the test, so that the control signal is physically adjacent to the word line in the first row. The written contents of the matched memory cells are alternately read, and the written contents of all the memory cells in the word line of the first row are inspected (memory cell selecting step, memory cell testing step).

When the stability test of the written contents for all the memory cells in the first word line is completed, X
The decoder 12 outputs a decode signal corresponding to the next word line (second row), and the same write operation is performed on the memory cells on this word line (memory cell selection step, memory cell test). Steps).

When the inspection of the written contents is completed for all the memory cells constituting the memory cell array 11, the X decoder 12, the Y decoder 13, the selector 14, and the OR gate 16 finally operate.
With each word line and a plurality of bit lines sequentially selected, all the memory cells constituting the memory cell array 11 are read, and the test is completed after confirming that the written contents of all the memory cells are 0 values.

Thus, the quality of the SRAM can be maintained by checking the stability of the written contents of the SRAM which is the semiconductor memory circuit device according to the first embodiment. In the above example, by repeatedly performing the read operation alternately on the memory cells physically adjacently arranged on the word line, the ground potential Vss fluctuates, and the write contents of the memory cells do not show a 0 value. Then, an SRAM having a defective cell is detected as having no predetermined stability.

As described above, according to the first embodiment, a predetermined plurality of bit lines are selected from a plurality of bit lines constituting memory cell array 11, and a plurality of bit lines corresponding to the predetermined plurality of bit lines are selected. A memory cell selecting means including an X decoder 12, a Y decoder 13, a selector 14, and an OR gate 16 for setting a memory cell to a readable state, and a plurality of memory cells readable by the memory cell selecting means And a memory cell test means having a sense amplifier 15 for testing the stability of the written contents of the memory cells by repeatedly reading the written contents of the memory cell for a predetermined number of times. Read operation is not required and multiple memory cells are selected simultaneously on each word line , It is possible to greatly reduce the time required for the stability test of writing the contents of the memory cell.

Embodiment 2 In the first embodiment, a plurality of memory cells are simultaneously selected on each word line constituting the memory cell array 11, but in the second embodiment, a plurality of bit lines constituting the memory cell array 11 are simultaneously selected. It is something that can be done.

FIG. 3 schematically shows a structure of a semiconductor memory circuit device according to a second embodiment of the present invention. In the figure, reference numerals 1 to 16 denote memory cells constituting the memory cell array 11, 31 denotes an X decoder 12 and the memory cell array 11.
Are provided in correspondence with each word line, and the signal lines 32,
OR gates (memory cell selection means) for selecting a plurality of word lines having predetermined memory cells based on a control signal input through propagation through 33, and 32, 33 are externally connected test mode terminals (not shown). A signal line (memory cell selecting means) for transmitting a control signal input through the OR gate 31 to an H level corresponding to a value 1 and a value 0 as a control signal
Is appropriately input. here,
The output signal of the OR circuit constituting the OR gate 31 is output for each word line in the memory cell array 11, and the word line receiving the H-level signal from the OR circuit is selected.
In the illustrated example, an SRAM is used as a semiconductor storage circuit device.
You are using The same components as those in FIG. 1 are denoted by the same reference numerals, and duplicate description will be omitted.

Next, the operation will be described. Since the present invention aims at improving the efficiency of the test for the stability of the contents written in the memory cells constituting the semiconductor memory circuit device, the description of the data storage operation of the semiconductor memory circuit device is omitted. First, an L-level signal corresponding to a 0 value is externally input to the signal lines 32 and 33 as a control signal.
At this time, the CPU (not shown) writes, for example, data of value 0 to all the memory cells constituting the memory cell array 11. More specifically, when an address signal corresponding to all memory cells is transmitted from a CPU (not shown) to the SRAM, the X decoder 12 sends an H level decode signal to each OR circuit constituting the OR gate 31. Output sequentially. At this time, since the control signals propagating through the signal lines 32 and 33 are both at the L level, the H level decode signal from the X decoder 12 is sequentially input to each word line via the OR gate 31 to be in the selected state. Become. Further, Y decoder 13 outputs an H level decode signal corresponding to a predetermined bit line to selector 14. As a result, the memory cells corresponding to the selected word line and bit line become in a writable or readable state. The operation of setting the memory cells to the ground potential Vss and setting the stored contents to 0 is sequentially performed. Is written to the memory cell (data writing step). When the microcomputer performs a normal operation, all the memory cells constituting the memory cell array 11 are set to a state in which writing or reading is possible.

Next, the control signal propagating through the signal line 32 is set to H
The control signal propagating through the signal line 33 is set to L level. At this time, by outputting the decode signals for all the word lines from the X decoder 12 to the L level to the OR gate 31, the word line in the first row and the word line in the third row are selected. Further, the Y-decoder 13 alternately selects the bit lines in the first column and the bit lines in the second column that constitute the memory cell array 11 in FIG. Thereby, the memory cells 1 and 2 of the word line in the first row
Since the memory cells 9 and 10 of the third row word line are simultaneously readable, a signal relating to the contents to be written is outputted therefrom, amplified by the sense amplifier 15 and written by a detector (not shown). Inspect the contents. The above-described alternate selection of the bit lines by the Y decoder 13 is periodically performed a predetermined number of times in accordance with the test specification, for example, 128 to 5 bits.
By performing 0000 times, the written contents of the physically adjacent memory cells 1 and 2 on the first row word line and the physically adjacent memory cells 9 and 10 on the third row word line are inspected. (Memory cell selection step, memory cell test step).

As described above, the memory cells 1, 2, 9,
After detecting the writing content of 10, the control signal propagating on the signal line 32 is set at L level, and the control signal propagating on the signal line 33 is set at H level. At this time, as described above, the decode signals for all the word lines are output from the X decoder 12 to the OR gate 31 at the L level, so that the word lines in the second row and the fourth row are in the selected state. Become. Further, the Y-decoder 13 alternately selects the bit lines in the first column and the bit lines in the second column that constitute the memory cell array 11 in FIG. By performing the above-described alternate selection of the bit line by the Y decoder 13 periodically a predetermined number of times according to the test specification, for example, 128 to 50,000 times,
The written contents of the physically adjacent memory cells 5 and 6 on the second row word line and the physically adjacent memory cells 13 and 14 on the fourth row word line are inspected (memory cell selecting step, Memory cell test step).

When the stability test of the written contents for all the memory cells in the bit lines in the first and second columns is completed, the Y decoder 13 sets the next bit line (in the second and third columns).
The decode signals corresponding to the second column and the third column are alternately output, and the memory cells 2, 3, 6, 7,.
The same read operation of the written contents is performed for 10, 11, 14, and 15 (memory cell selection step, memory cell test step).

In this manner, when the inspection of the written contents is completed for all the memory cells constituting the memory cell array 11, finally, the X decoder 12, the Y decoder 13, the selector 14, and the OR gate 31
With each bit line and a plurality of word lines sequentially selected, all the memory cells constituting the memory cell array 11 are read, and it is confirmed that the written contents of all the memory cells are 0 values, and the test is terminated.

Thus, the quality of the SRAM can be maintained by checking the stability of the written contents of the SRAM which is the semiconductor memory circuit device according to the second embodiment. In the above example, by repeatedly performing the read operation alternately on the memory cells physically adjacently arranged on the word line, the ground potential Vss fluctuates, and the write contents of the memory cells do not show a 0 value. Then, an SRAM having a defective cell is detected as having no predetermined stability.

As described above, according to the second embodiment, a predetermined plurality of word lines are selected from a plurality of word lines constituting memory cell array 11, and a plurality of word lines corresponding to the predetermined plurality of word lines are selected. A memory cell selecting means including an X decoder 12, a Y decoder 13, a selector 14, and an OR gate 31 for setting a memory cell to a readable state, and a plurality of memory cells readable by the memory cell selecting means And a memory cell testing means including a sense amplifier 15 for testing the stability of the written contents of the memory cells by repeatedly reading the written contents of the memory cell for a predetermined number of times. Read operation is not required and multiple memory cells are simultaneously selected on each bit line , It is possible to greatly reduce the time required for the stability test of writing the contents of the memory cell.

Embodiment 3 The third embodiment has a configuration in which the first and second embodiments are combined, so that a plurality of word lines and a plurality of bit lines constituting a memory cell array can be simultaneously selected.

FIG. 4 is a diagram showing a configuration of a semiconductor memory circuit device according to a third embodiment of the present invention. In the figure, 1
To 56 are memory cells constituting the memory cell array 11,
16a is provided between the Y decoder 13 and the selector 14 in correspondence with a plurality of bit lines, and the signal lines 17a,
OR gates (memory cell selecting means) for selecting a plurality of bit lines having predetermined memory cells based on a control signal input via 18a, and 17a and 18a are externally connected via a test mode terminal (not shown). A signal line (memory cell selecting means) for transmitting a control signal input to the OR gate 16a to the H-level signal corresponding to the value 1 and an L-level signal corresponding to the value 0 are appropriately input as control signals.
Here, the output signal of the OR circuit forming the OR gate 16a is output to the selector corresponding to the plurality of bit lines in the selector 14, and the bit line receiving the H level signal from the OR circuit is selected.

A plurality of reference numerals 31a are provided between the X decoder 12 and the memory cell array 11 for each word line, and include a plurality of predetermined memory cells based on a control signal transmitted and input through the signal lines 32a and 33a. OR gate (memory cell selecting means) for selecting a word line, 32a, 33
Reference symbol a denotes a signal line (memory cell selection means) for transmitting a control signal input from the outside via a test mode terminal (not shown) to the OR gate 31a. A corresponding L-level signal is appropriately input. Here, the output signal of the OR circuit constituting the OR gate 31a is output for each word line in the memory cell array 11, and the word line that has received the H level signal from the OR circuit is selected. In the illustrated example, an SRAM is used as the semiconductor storage circuit device. The same components as those in FIGS. 1 and 2 are denoted by the same reference numerals, and redundant description will be omitted.

Next, the operation will be described. Since the present invention aims at improving the efficiency of the test for the stability of the contents written in the memory cells constituting the semiconductor memory circuit device, the description of the data storage operation of the semiconductor memory circuit device is omitted. FIG. 5 is a timing chart showing the operation of the stability test of the written contents of the memory cells of the semiconductor memory circuit device according to the third embodiment. In the figure, 17a, 18
a, 32a, 33a are signal lines 17a, 18a,
The level of a control signal propagating through 32a and 33a is shown with respect to time. Embodiment 3 along this FIG.
A description will be given of the stability test of the written contents of the memory cell of the semiconductor memory circuit device according to the present invention.

First, in a period T51 in FIG. 5, the control signals propagating through the signal lines 17a, 18a, 32a, and 33a are all at the L level corresponding to the 0 value. At this time, the CPU (not shown) writes, for example, data of value 0 to all the memory cells constituting the memory cell array 11.
More specifically, a CPU (not shown) is provided for the SRAM.
When the address signals corresponding to all the memory cells are transmitted from X, the X decoder 12 sequentially outputs an H level decode signal to the OR circuit constituting the OR gate 31a. At this time, the control signal propagating through the signal lines 32a and 33a is:
Since both are at the L level, the word line is selected according to the decode signal from the X decoder 12. Also,
The Y decoder 13 sequentially outputs an H level decode signal to an OR circuit forming the OR gate 16a. Signal line 17
Since the control signals propagating through a and 18a are both at the L level, the H level decode signal from the Y decoder 13 is output via the selector 14, and the bit lines are sequentially selected. As a result, the memory cell corresponding to the selected word line and bit line becomes in a writable or readable state, and this memory cell is set to the ground potential V.
The operation of sequentially setting the storage content to 0 value as ss is performed, and the 0 value is written to all the memory cells (data writing step). When the microcomputer performs a normal operation, the state during the period T51, that is, a state where all the memory cells constituting the memory cell array 11 can be written or read is set.

Next, in a period T52, the signal line 32a
Is set to H level, and the control signal propagating through the signal line 33a is set to L level. At this time, the X decoder 1
By outputting the decode signals for all the word lines from L2 to the L level to the OR gate 31a,
The word lines in the third, fifth, and seventh rows are selected. further,
As shown in FIG. 5, the control signals propagating through the signal lines 17a and 18a are alternately set to L level and H level. Here, the control signal propagating through the signal line 17a is at L level,
When the control signal propagating through a is at the H level, the OR gate 3
FIG. 4 shows that the word lines on the first, third, fifth, and seventh rows constituting the memory cell array 11 in FIG. 4 in which the output signal from 1a goes high are in a selected state, and the output signal from the OR gate 16a goes high. 4, the bit lines in the first, third, fifth and seventh columns are in a selected state.
5, 7, 17, 19, 21, 23, 33, 35, 37,
Since 39, 49, 51, 53, and 55 are simultaneously in a readable state, a signal relating to the contents to be written is outputted therefrom, amplified by the sense amplifier 15, and inspected by a detector (not shown). (Memory cell selection step, memory cell test step).

When the control signal propagating on signal line 17a is at H level and the control signal propagating on signal line 18a is at L level, the output signal from OR gate 31a attains H level. 1,3
The word lines on the fifth and seventh rows are selected, and the OR gate 1
4 in which the output signal from 6a is at the H level.
Since the bit lines in the sixth and eighth columns are in the selected state, a plurality of memory cells 2, 4, 6, 8, 18, 20, 22, 2
4,34,36,38,40,50,52,54,56
Are simultaneously readable, so that a signal relating to the contents of writing is output from them, amplified by the sense amplifier 15 and inspected for the contents of writing by a detector (not shown) (memory cell selection step, memory cell test). Steps).

As described above, when the control signal propagating on the signal line 32a is at the H level and the control signal propagating on the signal line 33a is at the L level, the control signals transmitted on the signal lines 17a and 18a are periodically tested. Are alternately set to the L level and the H level only a predetermined number of times, for example, from 128 to 50,000 times in accordance with the specification. Thereby, the written contents of the physically adjacent memory cells on the odd-numbered word lines are alternately read,
The contents written to all the memory cells in the odd-numbered word lines are checked (memory cell selecting step,
Memory cell test step).

After detecting the written contents of the memory cells in the odd-numbered word lines as described above, the period T5
Proceed to 3. In the period T53, a control signal transmitted through the signal line 32a is set at an L level, and a control signal transmitted through the signal line 33a is set at an H level. At this time, the decode signals for all the word lines from the X decoder 12 are set to L level,
By outputting to the R gate 31a, 2, 4, 6, 8
The word line in the row is selected. Further, as shown in FIG. 5, the control signals propagating through the signal lines 17a and 18a are alternately set to L level and H level. Here, the signal line 17a
When the control signal propagating through the signal line L is at the L level and the control signal propagating through the signal line 18a is at the H level, the output signal from the OR gate 31a is at the H level.
4, the word lines in the second, fourth, and sixth rows are selected, and the bit lines in the first, third, fifth, and seventh columns in FIG. 4 in which the output signal from the OR gate 16a goes high are selected. State, a plurality of memory cells 9, 11, 13, 15,
25, 27, 29, 31, 41, 43, 45, and 47 are simultaneously in a readable state, so that a signal relating to the contents of writing is output from these, and this is output to the sense amplifier 15.
And write data is inspected by a detector (not shown) (memory cell selection step, memory cell test step).

When the control signal propagating on signal line 17a is at H level and the control signal propagating on signal line 18a is at L level, the output signal from OR gate 31a attains H level. Make up 2,4
The word line in the sixth row is selected, and the OR gate 16a
2, 4, 6, and 6 in FIG.
Since the bit line in the eighth column is in the selected state, the plurality of memory cells 10, 12, 14, 16, 26, 28, 30,
Since 32, 42, 44, 46, and 48 are simultaneously in a readable state, a signal relating to the written content is output from these, and the amplified signal is amplified by the sense amplifier 15 and the written content is inspected by a detector (not shown). (Memory cell selection step, memory cell test step).

As described above, when the control signal propagating on the signal line 32a is at L level and the control signal propagating on the signal line 33a is at H level, the control signals propagating on the signal lines 17a and 18a are periodically tested. Are alternately set to the L level and the H level only a predetermined number of times, for example, from 128 to 50,000 times in accordance with the specification. As a result, the written contents of the physically adjacent memory cells on the even-numbered word lines are alternately read out,
The write contents for all the memory cells in the even-numbered word lines are checked (memory cell selecting step,
Memory cell test step).

When the inspection of the written contents is completed for all the memory cells constituting the memory cell array 11, the X decoder 12, the Y decoder 13, the selector 14, the OR gate 16a, and the OR The gate 31a reads out all the memory cells constituting the memory cell array 11 while sequentially selecting the plurality of word lines and the plurality of bit lines, and confirms that the written contents of all the memory cells are 0 values and performs a test. finish.

As described above, according to the third embodiment, a predetermined plurality of word lines and bit lines are selected from a plurality of word lines and bit lines constituting memory cell array 11, and a plurality of predetermined word lines and bit lines are selected. X decoder 12, Y decoder 13, selector 14, OR for setting a plurality of memory cells corresponding to a line and a bit line to a readable state
A memory cell selecting means comprising a gate 16a and an OR gate 31a; and a plurality of times of repeatedly reading the written contents of the plurality of memory cells which are made readable by the memory cell selecting means, thereby stabilizing the written contents of the memory cells. And a memory cell testing means including a sense amplifier 15 for testing a memory cell, a plurality of memory cells are simultaneously selected on a plurality of word lines and a plurality of bit lines. Thus, the time required for the stability test of the written contents of the memory cell can be greatly reduced.

Embodiment 4 In the above-described embodiment, an example has been described in which the CPU of the microcomputer controls the stability test of the written content of the memory cell by transmitting an address signal corresponding to the memory cell. In this case, the stability test of the written contents of the memory cell can be performed automatically.

FIG. 6 schematically shows a structure of a semiconductor memory circuit device according to a fourth embodiment of the present invention. In the illustrated example, an SRAM is used as a semiconductor storage circuit device. In the figure, 16b is the Y decoder 13 and the selector 1
4, a plurality of bit lines are provided corresponding to a plurality of bit lines.
O that sets a plurality of bit lines having predetermined memory cells to a selected state based on a control signal input from circuits 60 and 64
An R gate (memory cell selection means), 60 receives signals from the SRAM test register 69 and the frequency divider 62,
AND circuit (memory cell selecting means, automatic test means) for outputting the operation result to the OR gate 16b, 61a is an SRAM
A signal line (automatic test means) for transmitting a signal corresponding to the data stored in the test register 69 to the selectors 66 and 68, the AND circuits 60 and 64, and a signal 62 for dividing the Xin signal, which is the operation clock signal of the microcomputer, by １ ／ A frequency divider (automatic test means) that outputs the signal to the AND circuit 60, the inverter 63, and the counter 65.

Reference numeral 63 denotes an inverter (automatic test means) for inverting the level of the Xin signal obtained by dividing the frequency of the Xin signal from the ２ frequency divider 62 and outputting the inverted signal to the AND circuit 64; AND circuit (memory cell selection means, automatic test means) which inputs the signal of
The number of times of the level change of the output signals of the circuits 60 and 64 (that is, the Y decoder 13, the selector 14, and the OR gate 1)
6b) is a counter (automatic test means) that counts the number of times a bit line is selected according to 6b.
For example, it is set to count 128 to 50,000 times. When the counter 65 has counted the predetermined number of times,
A signal to that effect is output to the counter 67. 66, based on a signal corresponding to the data stored in the SRAM test register 69, converts a signal input to the sense amplifier 15 into an SR from a CPU (not shown) in the normal operation mode.
A selector (automatic test means) for switching from the AM read signal to the Xin signal in the test mode, 66a is a signal line (automatic test means) for inputting the Xin signal to the selector 66, and switches the selector 66 to the signal line 66a side. Thus, the sense amplifier 15 can perform the read operation of the memory cell in synchronization with the Xin signal. When receiving a signal indicating that the predetermined number of counts have been completed from the counter 65, the counter 67 outputs a switching signal to the selector 68 to switch from the signal line 68a side to the address side (automatic test means). A selector (automatic test means) for switching to the signal line 68a or the address side based on a signal corresponding to the data stored in the test register 69 and a switching signal from the counter 67. In the operation mode, a CPU (not shown) can control the X decoder 12. Reference numeral 68a denotes a signal line (automatic test means) for transmitting a signal between the selector 68 and the counter 67, and 69 denotes a normal operation mode or a test mode when a CPU (not shown) stores 0-value or 1-value data. S to set
RAM test register (automatic test means). In addition,
The same components as those in FIG. 1 are denoted by the same reference numerals, and redundant description will be omitted.

Next, the operation will be described. Since the present invention aims at improving the efficiency of the test for the stability of the contents written in the memory cells constituting the semiconductor memory circuit device, the description of the data storage operation of the semiconductor memory circuit device is omitted. First, a CPU (not shown) stores 0-value data in the SRAM test register 69. This allows
From the SRAM test register 69, an L-level signal corresponding to 0-value data is sent to the AND circuit 6 via the signal line 61a.
0, 64 and output to selectors 66, 68. When an L-level signal is input to the AND circuits 60 and 64, the control signal input to the OR gate 16b becomes L level corresponding to the 0 value. At this time, the CPU (not shown) writes, for example, data of value 0 to all the memory cells constituting the memory cell array 11. Specifically, SRA
When an address signal corresponding to all memory cells is transmitted from the CPU (not shown) to M, the X decoder 12 outputs an address signal for the memory cell stored in the register (not shown) from the selector 68 connected to the address side. When it is received, an H-level decode signal is sequentially output to each corresponding word line to bring it into a selected state. Also, Y decoder 1
Reference numeral 3 sequentially outputs an H level decode signal to each OR circuit constituting the OR gate 16b. Since the signals from the AND circuits 60 and 64 input to the OR gate 16b are both at L level, the bit line is selected by the H level decode signal from the Y decoder 13. As a result, the memory cells corresponding to the selected word line and bit line become in a writable or readable state, and the memory cells are sequentially set to the ground potential Vss and the operation of resetting the stored contents to 0 is performed. Is written to the memory cell (data writing step). Also,
When the microcomputer performs a normal operation, zero-value data is stored in the SRAM test register 69, and the sense amplifier 15
Is ready to receive the SRAM read signal, that is,
All the memory cells constituting the memory cell array 11 are set to be in a writable or readable state.

Next, the CPU (not shown) stores one-value data (start signal) in the SRAM test register 69. As a result, an H-level signal corresponding to one-value data is output from the SRAM test register 69 through the signal line 61a.
The signals are output to the ND circuits 60 and 64 and the selectors 66 and 68. When the selector 66 receives the H-level signal via the signal line 61a, the selector 66 receives the signal from the SRAM read signal side.
The state is switched to the side a, and the sense amplifier 15 changes from a state capable of receiving the SRAM read signal to a state capable of receiving the Xin signal. When the selector 68 receives the signal of H level via the signal line 61a, the selector 68 receives the signal line 68 from the address side.
The state is switched to the side a, and the X decoder 12 becomes controllable by the output signal of the counter 67.

When an H level signal is input to the AND circuits 60 and 64, the control signal input to the OR gate 16b is alternately changed to H in synchronization with the Xin signal which is the operation clock signal.
Level, L level. More specifically, AND
Each of the circuits 60 and 64 includes the SRAM test register 6
9 and the Xin signal from the divide-by-2 frequency divider 62 is directly input to the AND circuit 60.
The level of the Xin signal is inverted and input to the D circuit 64 by the inverter 63. Therefore, the AND circuits 60 and 6
The signal output from 4 alternately goes to H level and L level in synchronization with the Xin signal.

At this time, H is alternately synchronized with the Xin signal.
Since the output signals from the AND circuits 60 and 64 at the L level and the L level are input to the OR gate 16b, the output signal from the OR gate 16b also alternately goes to the H level and the L level in synchronization with the Xin signal. Thus, for example, the signal output from the Y decoder 13 to the OR gate 16b is set at L level, and when the output signals from the AND circuits 60 and 64 are at L level and H level, respectively, the output signal from the OR gate 16b is at H level. The memory cell 1 in FIG.
The bit lines corresponding to 3, 5, and 7 are selected, and AN
Output signals from the D circuits 60 and 64 are at H level, respectively.
When the output signal from the OR gate 16b is at the L level, the bit lines corresponding to the memory cells 2, 4, 6, and 8 in FIG. 6 are selected. Therefore, if the word line of the first row constituting the memory cell array 11 in FIG. 6 is selected by the X decoder 12 based on the output signal from the counter 67, a plurality of memory cells 1
Since the memory cells 3, 5, 7 and the memory cells 2, 4, 6, 8 are simultaneously and alternately readable in synchronization with the Xin signal, a signal relating to the contents of writing is output from these, and this is sensed. The amplified data is amplified at 15 and the written contents are inspected by a detector (not shown) (memory cell selection step, memory cell test step).

Thereafter, the AND counted by the counter 65
When the number of level changes of the signals output from the circuits 60 and 64 reaches the set predetermined number (that is, the write contents of the physically adjacent memory cells on the word line of the first row are alternately performed by the predetermined number of times). When the reading is performed and the contents written to all the memory cells in the word line of the first row are inspected), the counter 65 outputs to the counter 67 a signal indicating that the predetermined number of times has been counted. Counter 67
Receives the signal from the counter 65, counts the completion of the test on the word line in the first row, and causes the X decoder 12 to output a decode signal corresponding to the next word line (second row). As a result, the same read operation of the written contents is performed on the memory cells on the word lines in the second row (memory cell selection step, memory cell test step).

As described above, the CPU (not shown) uses the SRA
By simply writing one-value data to the M test register 69, the written contents are automatically inspected for all the memory cells constituting the memory cell array 11, so that a predetermined value expected in advance as the test time is obtained. After a lapse of time, the CPU (not shown) sets the SRAM test register 6
The above test is stopped by writing 0-value data to 9. Thereafter, all the memory cells constituting the memory cell array 11 are read, and it is confirmed that the write contents of all the memory cells are 0 values, and the test is terminated.

As described above, according to the fourth embodiment, a predetermined plurality of bit lines are selected from a plurality of bit lines constituting memory cell array 11, and a plurality of bit lines corresponding to the predetermined plurality of bit lines are selected. A memory cell selecting means including a Y decoder 13, a selector 14, an OR gate 16b, AND circuits 60 and 64 for setting a memory cell to a readable state, and a plurality of readable states by the memory cell selecting means. A memory cell test means such as a sense amplifier 15 for repeatedly reading out the written contents of the memory cells a predetermined number of times to test the stability of the written contents of the memory cells, and an Xin signal of the microcomputer triggered by a start signal received from the CPU. Memory cell selecting means and memory cell 2 divider to operate the test means 62
And automatic test means including counters 65 and 67, etc., so that the stability test of the written contents of the memory cell can be performed without the intervention of the CPU. Therefore, the CPU can be used for other processing during the execution of the test. And the microcomputer can be used efficiently. For example, if the CPU is used for another test while the above test is being executed, the test time of the entire microcomputer can be significantly reduced.

Embodiment 5 FIG. The fifth embodiment is different from the fourth embodiment in that a plurality of word lines and a plurality of bit lines constituting a memory cell array can be simultaneously selected.

FIG. 7 schematically shows a structure of a semiconductor memory circuit device according to a fifth embodiment of the present invention. In the figure, reference numeral 67a denotes a counter (automatic test means) for outputting a control signal for simultaneously selecting a plurality of word lines to an OR gate 71, and 68b denotes a signal corresponding to data stored in an SRAM test register 69 and a counter 67. Is a selector (automatic test means) for switching to the ground potential side or the address side based on the switching signal of the switch.
When U is in a state where the X decoder 12 can be controlled and is switched to the ground potential side, all the output signals to the OR gate 71 propagating through the input address line of the X decoder 12 become L level corresponding to 0 value. Reference numeral 71 is provided between the X decoder 12 and the memory cell array 11 for each word line, and sets a plurality of word lines having predetermined memory cells to a selected state based on a control signal from the counter 67a.
R gate (memory cell selection means, automatic test means). The same components as those in FIGS. 1 and 6 are denoted by the same reference numerals, and redundant description will be omitted.

Next, the operation will be described. Since the present invention aims at improving the efficiency of the test for the stability of the contents written in the memory cells constituting the semiconductor memory circuit device, the description of the data storage operation of the semiconductor memory circuit device is omitted. First, a CPU (not shown) stores 0-value data in the SRAM test register 69. This allows
From the SRAM test register 69, an L-level signal corresponding to 0-value data is sent to the AND circuit 6 via the signal line 61a.
0, 64 and output to the selectors 66, 68b. AND
When the circuits 60 and 64 receive an L-level signal, both of the control signals input to the OR gate 16b have an L level corresponding to a 0 value. At this time, the CPU (not shown) writes, for example, data having a value of 0 to all the memory cells constituting the memory cell array 11 (data writing step). Since this operation is the same as that of the fourth embodiment,
Specific description is omitted.

Next, the CPU (not shown) stores one-value data in the SRAM test register 69. Thereby, S
An H-level signal corresponding to one-value data is output from the RAM test register 69 to the AND circuit 6 via the signal line 61a.
0, 64 and output to the selectors 66, 68b. When the selector 66 receives the H level signal via the signal line 61a, the selector 66 switches from the SRAM read signal side to the signal line 66a side, and the sense amplifier 15 switches from the state capable of receiving the SRAM read signal to the state capable of receiving the Xin signal. Become.
Further, when the selector 68b receives an H level signal via the signal line 61a, the selector 68b switches from the address side to the ground potential side, and an OR signal propagating through the input address line of the X decoder 12.
The output signals to the gate 71 are all at the L level corresponding to the 0 value.

When an H-level signal is input to AND circuits 60 and 64, as described in the fourth embodiment, the OR gates 16 and 64 are synchronized with the Xin signal as the operation clock signal.
The control signal input to b alternately becomes H level and L level. At this time, the H level is alternately synchronized with the Xin signal,
Since the output signals from the AND circuits 60 and 64 at L level are input to the OR gate 16b, the OR gate 16b
The output signal from the inverter also alternately goes to H level and L level in synchronization with the Xin signal.

As a result, for example, O
The signal output to the R gate 16b is set to L level, and AND
The output signals from the circuits 60 and 64 are L level and H level respectively.
When the level is at the level, the output signal from the OR gate 16b goes to the H level, and the bit lines in the odd columns forming the memory cell array 11 in FIG.
When the output signals from 0 and 64 are at H level and L level, respectively, the bit lines in the even columns in FIG. 7 in which the output signal from OR gate 16b is at H level are in a selected state.

At this time, an H-level signal is output to the OR circuit in the OR gate 71 corresponding to the word line of the odd-numbered row constituting the memory cell array 11 in FIG. When a signal indicating that the test of the word line of the second row is completed is received from the counter 65, a high-level signal is output to the OR circuit in the OR gate 71 corresponding to the word line of the even-numbered row. Since the memory cells corresponding to the plurality of word lines and the plurality of bit lines constituting the memory cell array 11 can be simultaneously read out in synchronization with the Xin signal, a signal relating to the written content is output from these, and this is output. The data is amplified by the sense amplifier 15 and the written contents are inspected by a detector (not shown) (memory cell selection step, memory cell test step).

When the inspection of the written contents is completed for all the memory cells constituting the memory cell array 11 in this manner, finally, all the memory cells constituting the memory cell array 11 are read, and all the memory cells constituting the memory cell array 11 are read. The test is terminated after confirming that the written content of is zero.

As described above, according to the fifth embodiment, a predetermined plurality of word lines and bit lines are selected from a plurality of word lines and bit lines constituting memory cell array 11, and a plurality of predetermined word lines and bit lines are selected. X decoder 12, Y decoder 13, selector 14, OR for setting a plurality of memory cells corresponding to a line and a bit line to a readable state
A memory cell selecting means including a gate 16b, an OR gate 71, etc .; and repeatedly writing a predetermined number of times the write contents of the plurality of memory cells which can be read by the memory cell select means, thereby stabilizing the write contents of the memory cells. A memory cell testing means including a sense amplifier 15 for testing the performance, a memory cell selecting means, and a memory cell selecting means, not through a CPU, synchronized with an Xin signal of a microcomputer using a start signal received from the CPU as a trigger. Counter 67 for operating test means
a and the like, the same effects as in the fourth embodiment can be obtained, and a plurality of memory cells are simultaneously selected on a plurality of word lines and a plurality of bit lines. The time required for the stability test of the written contents of the memory cell can be significantly reduced as compared with the fourth embodiment.

Embodiment 6 FIG. In the sixth embodiment, the number of word lines and / or bit lines to be simultaneously selected by the memory cell selecting means so as not to exceed the allowable value of the power consumption of the device is limited.

FIG. 8 schematically shows a structure of a semiconductor memory circuit device according to a sixth embodiment of the present invention. In the figure, 31b denotes the X decoder 12 and the memory cell array 11
Are provided corresponding to each word line, and signal lines 81 to 81 are provided.
OR gates (memory cell selection means) for selecting a plurality of word lines having predetermined memory cells based on a control signal from 84, and control signals are inputted to 81 to 84 from outside using test mode terminals. The signal lines 81 to 84 are connected to two OR circuits in the OR gate 31b. Note that FIG.
The same components as those described above are denoted by the same reference numerals, and redundant description will be omitted.

Next, the operation will be described. In the third embodiment, one other word line is provided by the signal lines 32a and 33a. That is, in the example of FIG. 4, the word lines in the odd-numbered rows are simultaneously selected. However, this causes half of the memory cells constituting the memory cell array 11 to be in a state where data can be read at the same time, and if the test of the written contents is performed on them, the power consumption may exceed the allowable power consumption in the SRAM. is there.

Therefore, in the sixth embodiment, in order to limit the number of word lines to be simultaneously selected, for example, each signal line 81 to 84 is connected to two OR circuits in the OR gate 31b. Are configured such that when an H-level control signal is input to each of them, two word lines are selected. As a specific operation, H level control signals are sequentially output to the signal lines 81 to 84 every time a write content test is performed on a memory cell on one word line, and two word lines are simultaneously selected.

FIG. 9 is a diagram schematically showing another configuration of the semiconductor memory circuit device according to the sixth embodiment of the present invention. In the figure, 67b is a counter (memory cell selecting means, automatic test means) for outputting a control signal for simultaneously selecting a plurality of word lines to the OR gate 71a via signal lines 91 to 94, and 91 to 94 are counters 67b , And a signal line (memory cell selecting means) to which a control signal is input. Each of the signal lines 91 to 94 is connected to two OR circuits in the OR gate 71a. Reference numeral 71a is provided between the X decoder 12 and the memory cell array 11 for each word line, and selects a plurality of word lines having predetermined memory cells based on control signals from the signal lines 91 to 94. An OR gate (memory cell selecting means, automatic test means). The same components as those in FIGS. 1 and 7 are denoted by the same reference numerals, and redundant description will be omitted.

Next, the operation will be described. FIG. 9 shows an example in which the above-described configuration for limiting the number of word lines to be simultaneously selected is applied to the configuration of the fifth embodiment. Here, the detailed operation is the same as that of the fifth embodiment, and thus the description thereof will be omitted, and the operation of selecting a word line will be described.
When the writing content test is completed for all the memory cells on one word line, the counter 67b is connected to the signal lines 91 to 94 each connected to two OR circuits in the OR gate 71a.
Sequentially output H-level control signals to simultaneously select two word lines.

As described above, according to the sixth embodiment, the memory cell selecting means including the OR gate 71a and the signal lines 91 to 94 are simultaneously selected so as not to exceed the allowable value of the power consumption of the device. Since the number of word lines to be set is limited, the power consumed when performing a write test on a memory cell can be reduced.
The load on the microcomputer can be reduced.

In the above embodiment, an example in which the number of word lines to be simultaneously selected is limited has been described.
At the same time, the number of bit lines to be selected may be limited.

In the above-described embodiment, an example has been described in which the number of word lines to be simultaneously selected is two. However, another number may be used as long as the power consumption of the device does not exceed the allowable value.

Embodiment 7 FIG. In the seventh embodiment, when all the memory cells in the memory cell array are tested, the automatic test means outputs an interrupt signal indicating that the test is completed to C.
This is transmitted to the PU.

FIG. 10 schematically shows a structure of a semiconductor memory circuit device according to a seventh embodiment of the present invention. In the figure, when receiving a signal from the counter 65 that notifies the counter 65 that counting of all memory cells has been completed a predetermined number of times (that is, the writing content test for all memory cells is completed), the CPU (not shown) executes the test. A counter (memory cell selection means, automatic test means) for outputting an interrupt signal for notifying the completion is shown. Reference numeral 100 denotes a signal line for transmitting an interrupt signal from the counter 67c to a CPU (not shown). The same components as those in FIGS. 1 and 6 are denoted by the same reference numerals, and redundant description will be omitted.

Next, the operation will be described. In the fourth embodiment, it is possible to automatically perform a write content test on a memory cell without the intervention of a CPU (not shown), and to provide a configuration in which the CPU (not shown) can perform other processing during execution of the test. Indicated. In this configuration, when the CPU (not shown) executes another process, the time for executing the other process must be adjusted in consideration of the time for completing the write content test. For example, during execution of the above test, C (not shown)
Assuming that the PU executes another test having a short processing time, it is necessary to adjust the CPU time by executing another process after the completion of this test until the completion of the write content test. . Therefore, this embodiment 7
When the counter 65c receives a signal from the counter 65 indicating that the count of all memory cells has been completed a predetermined number of times (that is, the writing content test for all memory cells has been completed), the counter 67c is disabled via the signal line 100. An interrupt signal for notifying that the test is completed is output to the illustrated CPU. Thus, the CPU (not shown) can know that the write content test has been completed by the interrupt signal even if the CPU (not shown) performs other processing during the execution of the write content test without considering the completion time. .

As described above, according to the seventh embodiment, when all the memory cells in memory cell array 11 are tested, counter 67c transmits an interrupt signal indicating that the test is completed to CPU. Since the CPU can perform other processing without considering the time required for completing the write content test on the memory cell,
Can be used efficiently.

Note that the seventh embodiment may be applied to the configurations of the fourth to sixth embodiments.

[0083]

As described above, according to the present invention, a predetermined plurality of word lines and / or bit lines are selected from a plurality of word lines and / or bit lines constituting a memory cell array, and a predetermined plurality of word lines and / or bit lines are selected. A plurality of memory cells corresponding to the word lines and / or bit lines are set in a readable state, and the written contents of the plurality of readable memory cells are repeatedly read a predetermined number of times, and the written contents of the memory cells are read. Is tested, the time required for the stability test of the written contents of the memory cell can be greatly reduced.

In the semiconductor memory circuit device according to the present invention, a predetermined plurality of word lines and / or bit lines are selected from a plurality of word lines and / or bit lines constituting a memory cell array, and a predetermined plurality of word lines and / or bit lines are selected. And / or setting a plurality of memory cells corresponding to the bit lines to a readable state, and repeatedly reading the written contents of the plurality of memory cells in the readable state a predetermined number of times, thereby stabilizing the written contents of the memory cells. Is automatically performed without the intervention of the CPU while synchronizing with the operation clock signal of the microcomputer using the start signal received from the CPU as a trigger.
In addition to providing the same effect as the test 83, the stability test of the written contents of the memory cells can be performed without the intervention of the CPU. Therefore, the CPU can be used for other processing during the execution of the test, and the microcomputer can be used. There is an effect that can be used efficiently.

In the semiconductor memory circuit device according to the present invention, when all the memory cells in the memory cell array have been tested, an interrupt signal indicating that the test has been completed is transmitted to the CPU. Since other processing can be executed without considering the time when the test is completed, there is an effect that the CPU can be used efficiently.

In the semiconductor memory circuit device according to the present invention, the number of word lines and / or bit lines to be simultaneously selected is limited so as not to exceed the allowable value of power consumption of the device. Since the power consumed in performing the test can be reduced, there is an effect that the load applied to the microcomputer can be reduced.

[Brief description of the drawings]

FIG. 1 is a diagram schematically showing a configuration of a semiconductor memory circuit device according to a first embodiment of the present invention;

FIG. 2 is a timing chart illustrating an operation of a stability test of a written content of a memory cell of the semiconductor memory circuit device according to the first embodiment;

FIG. 3 is a diagram schematically showing a configuration of a semiconductor memory circuit device according to a second embodiment of the present invention;

FIG. 4 is a diagram showing a configuration of a semiconductor memory circuit device according to a third embodiment of the present invention;

FIG. 5 is a timing chart showing an operation of a stability test of a written content of a memory cell of a semiconductor memory circuit device according to a third embodiment;

FIG. 6 is a diagram schematically showing a configuration of a semiconductor memory circuit device according to a fourth embodiment of the present invention;

FIG. 7 is a diagram schematically showing a configuration of a semiconductor memory circuit device according to a fifth embodiment of the present invention;

FIG. 8 schematically shows a configuration of a semiconductor memory circuit device according to a sixth embodiment of the present invention.

FIG. 9 schematically shows another configuration of a semiconductor memory circuit device according to a sixth embodiment of the present invention.

FIG. 10 is a diagram schematically showing a configuration of a semiconductor memory circuit device according to a seventh embodiment of the present invention;

FIG. 11 is a diagram schematically showing a configuration of a conventional SRAM.

[Explanation of symbols]

1 to 56 memory cells, 11 memory cell arrays, 12
X decoder (memory cell selecting means), 13 Y decoder (memory cell selecting means), 14 selector (memory cell selecting means), 15 sense amplifier (memory cell testing means), 16 OR gate (memory cell selecting means), 16
a OR gate (memory cell selecting means), 16b OR
Gate (memory cell selecting means), 17, 18 signal line (memory cell selecting means), 17a, 18a signal line (memory cell selecting means), 31 OR gate (memory cell selecting means), 31a OR gate (memory cell selecting means) ), 31b OR gate (memory cell selecting means), 3
2, 33 signal lines (memory cell selecting means), 32a, 3
3a signal line (memory cell selecting means), 60 AND circuit (memory cell selecting means, automatic test means), 61a signal line (automatic test means), 622 frequency divider (automatic test means), 63 inverter (automatic test means) ), 64 AN
D circuit (memory cell selection means, automatic test means), 65
Counter (automatic test means), 66 selector (automatic test means), 66a signal line (automatic test means), 67 counter (automatic test means), 67a counter (automatic test means), 67b counter (memory cell selecting means, automatic test) Means), 67c counter (memory cell selecting means, automatic test means), 68 selector (automatic test means), 68a
Signal line (automatic test means), 68b selector (automatic test means), 69 SRAM test register (automatic test means), 71 OR gate (memory cell selecting means, automatic test means), 71a OR gate (memory cell selecting means,
Automatic test means), 81 to 84 signal lines (memory cell selecting means), 91 to 94 signal lines (memory cell selecting means),
100 signal lines.

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) G11C 11/413 G01R 31/28 B 5L106 H01L 21/66 G11C 11/34 341D F-term (Reference) 2G032 AA07 AE07 AG07 AK11 AL11 4M106 AB07 AC01 CA26 DJ11 5B015 KB44 KB92 MM07 RR00 5B018 GA03 HA01 JA30 MA01 NA03 PA10 5B062 AA08 CC01 DD10 JJ05 5L106 AA02 DD04 EE02

Claims (6)

[Claims] 1. A semiconductor memory circuit device comprising: a plurality of word lines and a plurality of bit lines arranged orthogonally in a matrix, and a memory cell array including a plurality of memory cells provided in a grid at respective intersections. A predetermined plurality of word lines and / or bit lines from the plurality of word lines and / or bit lines forming the memory cell array;
Alternatively, a memory cell selecting means for setting a bit line to a selected state and setting a plurality of memory cells corresponding to the predetermined plurality of word lines and / or bit lines to a readable state, and readable by the memory cell selecting means A semiconductor memory circuit device comprising: memory cell testing means for repeatedly reading the written contents of the plurality of memory cells in the state a predetermined number of times and testing the stability of the written contents. A plurality of word lines and a plurality of bit lines are arranged in a matrix so as to be orthogonal to each other in a microcomputer, and a memory cell array including a plurality of memory cells provided in a grid on each intersection is provided. A semiconductor memory circuit device which is appropriately used for arithmetic processing of a CPU of the microcomputer, wherein the plurality of word lines and / or bit lines constituting the memory cell array are replaced with a predetermined plurality of word lines and / or bit lines.
Alternatively, a memory cell selecting means for setting a bit line to a selected state and setting a plurality of memory cells corresponding to the predetermined plurality of word lines and / or bit lines to a readable state, and readable by the memory cell selecting means Memory cell test means for repeatedly reading the written contents of the plurality of memory cells in the state a predetermined number of times to test the stability of the written contents; and an operation clock of the microcomputer triggered by a start signal received from the CPU. A semiconductor memory circuit device comprising: a memory cell selecting unit; and an automatic test unit that operates the memory cell test unit without intervening the CPU while synchronizing with a signal. 3. The semiconductor memory according to claim 2, wherein the automatic test means sends an interrupt signal to the CPU when all the memory cells in the memory cell array have been tested, to notify the completion of the test. Circuit device. 4. The memory cell selector according to claim 1, wherein the number of word lines and / or bit lines to be simultaneously selected is limited so as not to exceed an allowable value of power consumption of the device. The semiconductor memory circuit device according to claim 2. 5. A semiconductor memory circuit device having a memory cell array in which a plurality of word lines and a plurality of bit lines are arranged orthogonally in a matrix, and a plurality of memory cells are provided in a grid at respective intersections. In the test method, a data writing step of writing data of the same content to all the memory cells constituting the memory cell array; and a plurality of word lines and / or bit lines from the plurality of word lines and / or bit lines constituting the memory cell array. /
Alternatively, a memory cell selecting step of setting a bit line to a selected state and setting a plurality of memory cells corresponding to the predetermined plurality of word lines and / or bit lines to a readable state; A memory cell test step of repeatedly reading the written contents of the plurality of memory cells in the state a predetermined number of times to test the stability of the written contents, wherein the operation from the memory cell selecting step to the memory cell testing step is performed. A test method for a semiconductor memory circuit device, which is repeated until the process is repeated for all the memory cells constituting the memory cell array. 6. A memory cell array built in a microcomputer, comprising a plurality of word lines and a plurality of bit lines arranged orthogonally in a matrix, and a plurality of memory cells provided in a grid at respective intersections. A method for testing a semiconductor storage circuit device, which is appropriately used for arithmetic processing of a CPU of the microcomputer, comprising: a data writing step in which the CPU writes data of the same content to all memory cells constituting the memory cell array; From the plurality of word lines and / or bit lines constituting the memory cell array, a predetermined plurality of word lines and / or
Alternatively, a memory cell selecting means for setting a bit line to a selected state and setting a plurality of memory cells corresponding to the predetermined plurality of word lines and / or bit lines to a readable state; A memory cell test step of repeatedly reading out the written contents of the plurality of memory cells in the state a predetermined number of times, and testing the stability of the written contents, wherein the start signal received from the CPU is used as a trigger to trigger the microcomputer. The operation from the memory cell selection step to the memory cell test step is repeated in synchronization with the operation clock signal without intervention of the CPU until the operation from the memory cell selection step to the memory cell test step is performed on all the memory cells constituting the memory cell array. A method for testing a semiconductor storage circuit device.