JP2001318126A - Method for testing semiconductor integrated circuit, equipment for testing semiconductor, and semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To shorten the inspection time required for acceleration test at the time of testing a semiconductor integrated circuit including a novolatile memory element. SOLUTION: The method for testing a semiconductor integrated circuit having a novolatile memory element and a peripheral circuit part other than the novolatile memory element comprises a first step for applying a high voltage to all memory cells in the novolatile memory element and a second step for imparting a test pattern to the peripheral circuit part other than the novolatile memory element while applying a high voltage wherein both steps are performed simultaneously.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique for simultaneously performing an acceleration test of a nonvolatile element portion and a peripheral circuit thereof in a semiconductor integrated circuit including a nonvolatile memory element.

[0002]

2. Description of the Related Art In general, in a semiconductor integrated circuit, in order to stabilize the quality and remove (screen) a product having unstable performance, an acceleration stress is applied by a high temperature and a high voltage to accelerate the occurrence of a failure, and a short time. A burn-in test is conducted to remove defective products. The temperature condition and voltage condition of the acceleration test at this time are derived from the temperature acceleration coefficient and the voltage acceleration coefficient on the basis of the guaranteed condition.

On the other hand, in a semiconductor integrated circuit including a nonvolatile memory element such as a flash memory, a voltage applied to a nonvolatile memory element is generally higher than a voltage applied to a peripheral portion other than the nonvolatile memory element. There is a feature. Therefore, in a semiconductor integrated circuit including a nonvolatile storage element, it is necessary to perform an acceleration test in which a higher voltage is applied to a part of the nonvolatile storage element than to other parts in order to guarantee its operation.

In this case, it is conceivable to simply increase the applied voltage to the entire semiconductor integrated circuit. However, in order to perform the voltage acceleration test within the limit of the withstand voltage and to satisfy the required operation guarantee level, it is necessary to separately increase the voltage. Acceleration conditions.

[0005] The acceleration test of a conventional semiconductor integrated circuit including a nonvolatile memory element is as shown in the flowchart of FIG. That is, as shown in (a), a voltage accelerating test of a nonvolatile memory element, in which a voltage is statically applied to a nonvolatile memory element portion (memory cell portion) at a maximum and a predetermined time is waited, and (b)
As described above, voltage acceleration tests of peripheral circuits other than the non-volatile memory element portion (memory cell portion) in which Vcc of the semiconductor integrated circuit is set to a high voltage and the function operation is performed for a fixed time are separately performed.

[0006]

As described above, in a conventional semiconductor integrated circuit including a nonvolatile storage element, an acceleration test for the entire semiconductor integrated circuit and an acceleration test for only the nonvolatile storage element are performed. Was performed separately. Although the two-stage method is a sufficient test for guaranteeing the operation of the semiconductor integrated circuit, it has a problem that the time required for the accelerated test becomes long.

In particular, when the withstand voltage of the semiconductor integrated circuit is low, the voltage cannot be sufficiently increased in the accelerated test, but the test time becomes longer. As a result, the method of performing the accelerated test twice causes a longer test time, which is a serious problem.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems. In a test of a semiconductor integrated circuit including a nonvolatile memory element, an accelerated test for the nonvolatile memory element is performed while performing an accelerated test. An object of the present invention is to reduce an inspection time required for an acceleration test by performing an acceleration test on a peripheral portion other than the nonvolatile memory element.

[0009]

According to a first aspect of the present invention, there is provided a test method for a semiconductor integrated circuit having a nonvolatile memory element and a peripheral circuit section other than the nonvolatile memory element. The method includes a first step of applying a voltage at most and a second step of applying a test pattern while applying a high voltage to a peripheral circuit portion other than the nonvolatile memory element. Features.

According to a second aspect of the present invention, in the first aspect of the invention, when a voltage is applied to all the memory cells of the nonvolatile memory element at most, all the word lines and the bit lines of the nonvolatile memory element are multiple-selected. It is characterized by the following.

[0011] The invention of claim 3 is claim 1 or claim 2.
According to the invention, the peripheral circuit section other than the nonvolatile storage element includes a volatile storage element section.

According to a fourth aspect of the present invention, in a semiconductor test apparatus for testing a semiconductor integrated circuit having a nonvolatile memory element and a peripheral circuit portion other than the nonvolatile memory element, a voltage is applied to all memory cells of the nonvolatile memory element at most. First means for applying;
A second means for applying a test pattern while applying a high voltage to a peripheral circuit portion other than the nonvolatile memory element is provided, and the semiconductor integrated circuit is tested simultaneously by the two means.

According to a fifth aspect of the present invention, in a semiconductor integrated circuit having a nonvolatile memory element and a peripheral circuit portion other than the nonvolatile memory element, means for applying a voltage to all memory cells of the nonvolatile memory element at most is provided. Means for applying a test pattern while applying a high voltage to a peripheral circuit portion other than the memory element, and the acceleration test can be performed simultaneously by the two means.

According to a sixth aspect of the present invention, in the fifth aspect of the present invention, a control circuit for inputting a signal from a semiconductor test apparatus and analyzing a command thereof is multiplexed with all word lines and bit lines of a nonvolatile memory element. A multi-selection circuit for selecting a voltage; and a high-voltage source switching circuit for inputting a voltage from a high-voltage generator and applying a voltage at most to a nonvolatile memory element.

[0015] The invention of claim 7 is the invention of claim 5 or claim 6.
According to the invention, the peripheral circuit section other than the nonvolatile storage element includes a volatile storage element section.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiment 1 FIG. 1 is a schematic flowchart showing a method for testing a semiconductor integrated circuit according to the present invention. As shown in the figure, in the present invention, in a semiconductor integrated circuit including a nonvolatile memory element, a voltage acceleration test of a nonvolatile memory element (memory cell section) and a voltage acceleration test of a peripheral circuit section other than the nonvolatile memory element are performed. Perform at the same time. Thereby, the inspection time required for the accelerated test of the semiconductor integrated circuit can be reduced.

FIG. 2 is a schematic block diagram showing a semiconductor integrated circuit 3 according to the present invention and a semiconductor test apparatus 10 for testing the same. In the figure, a semiconductor test apparatus 10 includes a control unit 11 including a CPU for controlling the entire test apparatus.
A timing generator 12 for generating a test periodic signal (clock pulse), a pattern generator 13 for generating a test pattern signal, and a test pattern from the pattern generator 13 An output signal from the semiconductor integrated circuit 3 while being applied to an input pin of the semiconductor integrated circuit 3 via a format controller 14 for shaping into a predetermined waveform mode by an edge and a driver for determining a voltage level of the pattern shaped by the format controller 14 And a pattern comparator 16 for inputting a signal of the comparison result from the pin electronics 15 and performing a logical comparison with an expected value pattern generated from the pattern generator 13. Have been. Further, the semiconductor test apparatus 10 includes high voltage generators 17 and 18 that can apply a voltage to external pins of the semiconductor integrated circuit 3 at most to perform a voltage acceleration test of the nonvolatile memory element 1.

The semiconductor integrated circuit 3 includes a nonvolatile memory element 1 such as a flash memory, and a peripheral circuit unit 2 other than the nonvolatile memory element 1. And the peripheral circuit section 2
Is a control circuit 5 which receives at least a test signal from the pin electronics 15 and analyzes the command.
A multi-select circuit 6 for multi-selecting all word lines and bit lines of the nonvolatile memory element 1; and inputting voltages from the high voltage generators 17 and 18 to apply a voltage at most to the nonvolatile memory element 1. And a high-voltage source switching circuit 7 capable of performing such operations.

FIG. 3 is a detailed flowchart showing a method of testing a semiconductor integrated circuit according to the present invention.
FIG. 4 is a block diagram showing an operation state of a semiconductor test in steps 1 to 5 of FIG. Hereinafter, the accelerated test of the semiconductor integrated circuit including the nonvolatile memory element according to the present invention will be described in detail.

First, in step 1, the semiconductor test circuit 10 controls the semiconductor integrated circuit 3 to multi-select all word lines and bit lines of the nonvolatile memory element 1 and to select all the memory cells of the semiconductor memory element 1. Apply voltage at the same time. That is, as shown in FIG. 4, a command is output from the pin electronics 15 of the semiconductor test apparatus 10 to the control circuit 5 so that all the word lines and bit lines of the semiconductor memory element 1 are multi-selected. Is a multi-selection circuit 6
Is prepared so that a voltage is simultaneously applied to all the memory cells of the semiconductor memory element 1.

Next, in step 2, control is performed so that an externally applied voltage from the semiconductor test apparatus 10 is applied to the nonvolatile memory element 1. That is, as shown in FIG. 5, the high voltage source switching circuit 7 is controlled, and at most the voltages from the high voltage generators 17 and 18 of the semiconductor test apparatus 10 are applied to the nonvolatile memory element 1 via the multiple selection circuit 6. Prepare as follows.

Next, in step 3, a voltage is applied at most to the external application pin of the semiconductor integrated circuit 3 to start a static voltage acceleration test for the nonvolatile memory element 1. That is, as shown in FIG. 6, all the word lines and bit lines of the semiconductor memory element 1 are selected by the multiple selection circuit 6 (step 1), and at most the high voltage generators 17 and 18 output the high voltage from the high voltage generators 17 and 18 by the high voltage source switching circuit 7. In response to the voltage being prepared to be applied to the nonvolatile memory element 1 (step 2), a command for applying a voltage at most is output from the pin electronics 15 of the semiconductor test apparatus 10 to the control circuit 5, and the high voltage is applied by the command. The application of voltage at most to all the cells of the nonvolatile memory element 1 via the source switching circuit 7 is started.

Next, in step 4, an acceleration test of the peripheral circuit unit 2 other than the nonvolatile memory element 1 is performed while performing a voltage acceleration test of a portion of the nonvolatile memory element 1.
That is, as shown in FIG. 7, a high voltage is applied to a power supply pin / signal pin of the semiconductor integrated circuit 3 and a binary signal of “H” and “L” generated by the pattern generator 13 is applied to the signal pin. Various combinations are successively given, and a voltage acceleration test of the peripheral circuit unit 2 other than the nonvolatile memory element 1 is performed.

In step 5, after a lapse of a predetermined time required for the acceleration test, the signals and voltages applied to the semiconductor integrated circuit 3 are cut off, and the acceleration test of the nonvolatile memory element 1 and the acceleration test of the peripheral circuit section 2 are performed. The process is terminated (see FIG. 8).

As described above, according to the embodiment of the present invention, in a semiconductor integrated circuit including a nonvolatile memory element, an acceleration test is performed on the nonvolatile memory element, and at the same time, parts other than the nonvolatile memory element are tested. By performing the accelerated test, the inspection time required for the accelerated test can be reduced.

In the method of the present embodiment in which a plurality of tests are simultaneously performed for an accelerated test that consumes a long time, the effect of reducing the inspection time is great.

In particular, in the case where the miniaturization of the semiconductor integrated circuit advances and the breakdown voltage becomes low, the voltage cannot be increased sufficiently and the time of the acceleration test is lengthened instead. The time saving effect of the form is greater.

Other Embodiments In the above embodiment, the method of testing the semiconductor integrated circuit including the nonvolatile memory element and the peripheral circuit unit other than the nonvolatile memory element has been described. However, the nonvolatile memory element unit, the volatile memory element unit, The same can be applied to a method for testing a three-part semiconductor integrated circuit including the peripheral circuit portion.

[0029]

As described above, according to the present invention, in a semiconductor integrated circuit having a nonvolatile memory element and a peripheral circuit section other than the nonvolatile memory element, a voltage of at most is applied to all memory cells of the nonvolatile memory element. The acceleration test, which applies a test pattern while applying a high voltage to peripheral circuits other than the non-volatile storage element, and the acceleration test to apply a high voltage to the peripheral circuit section are performed simultaneously. The required inspection time can be reduced.

In the method of the present invention in which a plurality of tests are simultaneously performed for an accelerated test that consumes a long time, the effect of shortening the inspection time is great.

In particular, when the semiconductor integrated circuit is miniaturized and the breakdown voltage is reduced, the voltage cannot be sufficiently increased, and the time required for the acceleration test is lengthened instead. The time saving effect is greater.

[Brief description of the drawings]

FIG. 1 is a schematic flowchart showing a method for testing a semiconductor integrated circuit according to the present invention.

FIG. 2 is a schematic block diagram showing a semiconductor integrated circuit and a semiconductor test device according to the present invention.

FIG. 3 is a detailed flowchart showing a test method of a semiconductor integrated circuit according to the present invention.

4 is a block diagram showing an operation state of a semiconductor test in step 1 of FIG.

5 is a block diagram showing an operation state of a semiconductor test in step 2 of FIG.

6 is a block diagram showing an operation state of a semiconductor test in step 3 of FIG.

FIG. 7 is a block diagram showing an operation state of a semiconductor test in step 4 of FIG.

FIG. 8 is a block diagram showing an operation state of a semiconductor test in step 5 of FIG.

FIG. 9 is a schematic flowchart illustrating a conventional method for testing a semiconductor integrated circuit.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Non-volatile memory element, 2 Peripheral circuit parts other than a non-volatile memory element, 3 Semiconductor integrated circuit, 5 Control circuit, 6 Multiple selection circuit, 7 High voltage source switching circuit, 10 Semiconductor test apparatus, 11 Control section, 12 Timing generator , 13 pattern generator, 14 format controller, 15
Pin electronics, 16 pattern comparators, 1
7,18 High voltage generator.

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) G11C 29/00 673 G01R 31 / 28H G11C 17/00 601Z F-term (Reference) 2G003 AA07 AA08 AC01 AE06 AE09 AH01 AH04 2G032 AA08 AB01 AC03 AE07 AE08 AE12 AF10 AG07 AG10 AK03 AK15 AL00 5B025 AD00 AE09 AF00 5L106 AA10 DD21 DD36 FF01 GG00

Claims (7)

[Claims] 1. A method for testing a semiconductor integrated circuit having a nonvolatile memory element and a peripheral circuit portion other than the nonvolatile memory element, wherein a first step of applying a voltage to all memory cells of the nonvolatile memory element at most. A second step of applying a test pattern while applying a high voltage to a peripheral circuit unit other than the nonvolatile memory element, wherein both steps are performed simultaneously. 2. The semiconductor according to claim 1, wherein, when a voltage is applied to all the memory cells of the nonvolatile memory element at most, all the word lines and bit lines of the nonvolatile memory element are multiply selected. Test method for integrated circuits. 3. The test method for a semiconductor integrated circuit according to claim 1, wherein a peripheral storage unit other than the nonvolatile storage element includes a volatile storage element unit. 4. A semiconductor test apparatus for testing a semiconductor integrated circuit having a nonvolatile memory element and a peripheral circuit portion other than the nonvolatile memory element, wherein a first voltage is applied to all memory cells of the nonvolatile memory element. And a second means for applying a test pattern while applying a high voltage to a peripheral circuit portion other than the nonvolatile memory element, wherein the semiconductor integrated circuit is tested simultaneously by the two means. . 5. A semiconductor integrated circuit having a nonvolatile memory element and a peripheral circuit section other than the nonvolatile memory element, wherein means for applying a voltage to all memory cells of the nonvolatile memory element at most is provided. A semiconductor integrated circuit, comprising: means for applying a test pattern while applying a high voltage to a peripheral circuit part, wherein an acceleration test can be performed simultaneously by the two means. 6. A semiconductor integrated circuit having a nonvolatile memory element and a peripheral circuit section other than the nonvolatile memory element, a control circuit for inputting a signal from a semiconductor test device and analyzing a command thereof, and a nonvolatile memory element A multi-select circuit for multi-selecting all word lines and bit lines of
6. The semiconductor integrated circuit according to claim 5, further comprising a high-voltage source switching circuit that inputs a voltage from a high-voltage generator and applies a voltage to a nonvolatile memory element at most. 7. The semiconductor integrated circuit according to claim 5, wherein the peripheral circuit section other than the nonvolatile storage element includes a volatile storage element section.