JP2001313563A - Ripple counter, and counter correction method for the ripple counter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a ripple counter that corrects the count between circuits at different operating speed on the basis of prescribed correction data, and a counter correction method in the ripple counter. SOLUTION: The ripple counter is provided with a bipolar counter 11 that counts load data 1a received by a load clock 1b on the basis of a counter basic clock 1d outputted from FF(1)-FF(2) placed in a bipolar circuit on a gate array, a MOS counter 12 that counts load data 1c received by a load clock 1h on the basis of a counter clock 1i after the correction received by FF(m+1)-FF(n) placed in a MOS circuit on the gate array, and a timing correction circuit 13 that corrects a pulse width of a counter clock 1e transferred from the bipolar circuit to the MOS circuit on the basis of a level of the load data 1a received by a flip lop circuit FF(2) at a final stage in the bipolar circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a ripple counter and a counter compensation method in the ripple counter, and more particularly, to a counter compensation technique for a ripple counter in which circuits having different characteristics are mounted on a gate array.

[0002]

2. Description of the Related Art Conventionally, an n-type semiconductor and a p-type semiconductor have been
A bipolar circuit using bipolar transistors having a structure joined in the order of npn or pnp, and a MOS (Metal Oxide Semiconductor) type circuit using one of electrons and holes are used for amplifying electric signals and switching circuits. It is used as an element. In general, a bipolar circuit is M
Compared to the OS-type circuit, it can operate at a higher speed and flow a large amount of current, but consumes large power and is difficult to achieve high integration.

Referring to FIGS. 4 and 5, the configuration of the main part of a conventional ripple counter 20 having both the above-mentioned bipolar and MOS type circuits will be described. FIG.
FIG. 3 is a block diagram showing a functional configuration of a ripple counter 20. As shown in FIG. 4, the ripple counter 20 includes an ASIC (Application License) in which a plurality of basic logic circuits are wired.
n Specific Integrated Circuit), a bipolar counter 21 that counts ripples in a bipolar circuit on the surface,
MOS counter 2 for ripple counting in S-type circuit
2

The bipolar counter 21 receives predetermined load data 2a, a load clock 2b which is a clock signal of the load data 2a, and a counter basic clock 2d which is a reference signal for ripple counting, as input signals. A counter clock 2e, which is a ripple count signal of the load data 2a, is used as an output signal. MO
The S counter 22 receives the load clock 2b, the counter clock 2e, and the load data 2c output from the bipolar counter 21 as input signals.

FIG. 5 is a circuit diagram of the ripple counter 20. As shown in FIG. 5, the bipolar-side counter 21 includes m flip-flop circuits (hereinafter referred to as “F”).
F ". ) Are connected in series, and are configured with a frequency that allows high-speed operation on a bipolar circuit. Each FF is a binary element circuit that temporarily stores 1-bit information. On the other hand, the MOS-side counter 22 includes nm FFs (m + 1) to FF (n).
Are connected in series, and are configured at a frequency capable of operating at a low speed on the MOS circuit.

That is, the ripple counter 20 is divided into a high-speed operation unit for the bipolar counter 21 and a low-speed operation unit for the MOS counter 22.
For this reason, the level conversion circuit 24 that converts the clock level of the clock signal transferred between the two different types of operation units
a and 24b are required.

The level conversion circuit 24a converts the frequency of the load clock 2b input from the bipolar counter 21 into a low-speed frequency operable by the MOS counter 22. Similarly, the level conversion circuit 24b sets the frequency of the counter clock 2e input from the MOS counter 22 to M
The signal is converted into a low-speed frequency operable by the OS counter 22.

However, the delay time of the load clock 2b by the level conversion circuit 24a does not always coincide with the delay time of the counter clock 2e by the level conversion circuit 24b due to circuit delay, wiring delay, and the like. Therefore, delay circuits 25a and 25b are provided between the level conversion circuits 24a and 24b and the MOS counter 22.
The delay circuit 25a adjusts the delay time of the load clock 2b, and the delay circuit 25b adjusts the delay time of the counter clock 2e to make each delay time uniform.

[0009]

As described above, the conventional ripple counter 20 includes the level conversion circuits 24a and 24a.
b and the arrangement and wiring of the delay circuits 25a and 25b were required. Therefore, as the speed of the ripple counter 20 increases, the input timing of each clock signal shifts due to the difference in characteristics between the two types of counters. This adjustment is difficult and causes an increase in circuit design and development man-hours.

It is an object of the present invention to provide a ripple counter for compensating a counter between circuits having different operation speeds based on predetermined compensation data, and a counter compensation method for the ripple counter.

[0011]

In order to solve the above-mentioned problems, the invention according to claim 1 uses a counter clock output from a flip-flop circuit provided in a bipolar circuit on a gate array to perform a predetermined operation. First counter means (for example, a bipolar counter 11) for counting load data input by a data synchronous clock, and a counter clock input to a flip-flop circuit provided in a MOS circuit on the gate array The second counter means (for example, the MOS-side counter 1) counts the load data inputted by the predetermined data synchronous clock.
2) in the ripple counter (for example, the ripple counter 10), which adjusts the time width of the data synchronous clock so that the counting operation of the second counter means is possible (for example, a timing adjusting circuit). 1
3) is further provided.

According to the first aspect of the present invention, the first counter means is inputted with a predetermined data synchronous clock by a counter clock outputted from a flip-flop circuit provided in a bipolar circuit on the gate array. The second counter means counts the load data inputted by a predetermined data synchronous clock by a counter clock inputted to a flip-flop circuit arranged in a MOS type circuit on the gate array. Counting,
The compensating means compensates the time width of the data synchronization clock so that the counting operation of the second counter means can be performed.

According to a second aspect of the present invention, in the ripple counter according to the first aspect, the compensation means is based on, for example, a clock level of the load data input to a last-stage flip-flop circuit in the bipolar circuit. And correcting the pulse width of the counter clock transferred from the bipolar circuit to the MOS type circuit.

According to a third aspect of the present invention, in the ripple counter according to the first aspect, the correction means transfers the data transferred from the bipolar circuit to the MOS circuit based on, for example, externally input correction data. The time width of at least one of the synchronous clock and the counter clock is adjusted.

According to a fourth aspect of the present invention, there is provided a first circuit for counting load data inputted by a predetermined data synchronization clock by a counter clock outputted from a flip-flop circuit provided in a bipolar circuit on a gate array. And a second counter step of counting load data input by a predetermined data synchronization clock by a counter clock input to a flip-flop circuit provided in a MOS circuit on the gate array. And adjusting the time width of the data synchronization clock so that the counting operation can be performed in the second counter step.

According to the fourth aspect of the present invention, in the first counter step, a predetermined data synchronous clock is input by the counter clock output from the flip-flop circuit provided in the bipolar circuit on the gate array. The load data inputted is counted by a counter clock inputted to a flip-flop circuit arranged in a MOS type circuit on the gate array in a second counter step, and the load inputted by a predetermined data synchronous clock is counted. The data is counted, and the time width of the data synchronous clock is adjusted so that the counting operation can be performed in the second counter step in the adjusting step.

According to a fifth aspect of the present invention, in the counter compensation method of the ripple counter according to the fourth aspect, the clock level of the load data input to the last-stage flip-flop circuit in the bipolar circuit in the compensation step. From the bipolar circuit to the MO
The pulse width of the counter clock transferred to the S-type circuit is adjusted.

According to a sixth aspect of the present invention, in the counter compensation method of the ripple counter according to the fourth aspect, the bipolar circuit is transferred from the bipolar circuit to the MOS circuit based on compensation data inputted from outside in the compensation step. The time width of at least one of the data synchronization clock and the counter clock is adjusted.

Therefore, it is possible to easily and accurately correct a shift in the input timing of the data synchronous clock or the counter clock due to a difference in operation speed or a variation in characteristics between the bipolar circuit and the MOS circuit constituting the ripple counter. In addition, since a ripple counter and wiring corresponding to an increase in signal speed can be easily configured, design and development man-hours can be reduced.

[0020]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a ripple counter 10 according to an embodiment of the present invention will be described in detail with reference to FIGS.

First, the configuration will be described. FIG. 1 is a block diagram showing a functional configuration of the ripple counter 10. The ripple counter 10 includes a plurality of basic logic circuits,
It is configured as a gate array, which is a kind of wired ASIC, and has on its surface a bipolar counter 11 for ripple counting in a bipolar circuit and a MOS counter 12 for ripple counting in a MOS type circuit.
Further, between the two counters, a timing adjustment circuit 13 for adjusting the input timing of a load clock 1b and a counter clock 1e described later is arranged.

As shown in FIG. 1, the bipolar counter 11 includes a predetermined load data 1a and a load data 1a.
, And a counter basic clock 1d, which is a reference signal for ripple counting, as input signals, the load clock 1b and the load data 1a.
The counter clock 1e, which is a ripple count signal, is used as an output signal.

The MOS counter 12 receives as input signals the load clock 1h after the load clock 1b output from the timing correction circuit 13, the counter clock 1i after the counter clock 1e correction, and the load data 1c.

The timing correction circuit 13 receives the load clock 1b, the counter clock 1e, the load data 1a, and the timing correction data 1f output from the bipolar counter 11 as input signals. The clock 1i is an output signal.

FIG. 2 is a circuit diagram of the ripple counter 10. As shown in FIG. As shown in FIG. 2, the bipolar counter 11 is configured with a frequency at which two FFs (1) to FF (2) are connected in series and can operate at high speed on the bipolar circuit. Each FF is a binary element circuit that temporarily stores 1-bit information. On the other hand, the MOS-side counter 12 includes nm frequency FF (m + 1) to FF (n) connected in series, and is configured with a frequency capable of operating at a low speed on the MOS circuit.

The level conversion circuit 14a converts the frequency of the load data 1a-2 input from the bipolar counter 11 into a low frequency operable by the MOS counter 12. Similarly, the level conversion circuit 14b converts the frequency of the load clock 1b input from the bipolar counter 11 into a low frequency operable by the MOS counter 12. Further, the level conversion circuit 14c converts the frequency of the counter clock 1e input from the MOS counter 12 into a low frequency operable by the MOS counter 12.

The timing compensation circuit 13 includes two level conversion circuits 14 based on the timing compensation data 1f.
b and 14c, the load clock 1b and the counter clock 1e, respectively,
h, output as the adjusted counter clock 1i.

Next, the operation will be described. FIG. 3 is a timing chart of the ripple counter 10. In FIG. 3, the horizontal axis represents elapsed time T1 to T13, and the vertical axis represents High (hereinafter, referred to as “H”) or Low (hereinafter, referred to as “L”) state levels. Note that the wiring delay time inside the bipolar counter 11 and the MOS counter 12 and the FF (1) to FF (n), the level conversion circuits 14a,
It is assumed that the gate basic delay times of 4b and 14c are uniform.

As shown in FIG. 2A, the counter basic clock 1d alternately repeats transitions to H level and L level with T3-T1 as a basic cycle. Further, as shown in (b), the load clock 1b transitions to the H level at the time point of the elapsed time T1, and the load clock 1b
Load data 1a- to bit FF (1) and FF (2)
It is assumed that the setting of 1, 1a-2 is started, and at the time point of the elapsed time T3, the state transits to the L level again, and the data setting to each FF is completed.

FIGS. 3 (c), (d), (f),
As shown in (g), the load data 1a-1 input to the bipolar counter 11 is at the H level, the load data 1a-2 input to the MOS counter 12 is at the H level, and the load after the load data 1c-m + 1 is loaded. Data 1c
Assuming that an L level is set for data up to −n, a description will be given of compensation times (removal times and release times described later) secured for counter compensation.

At this time, as shown in (c), the counter clock 1g-x which is the x component of the counter clock 1g
Transitions to the H level at the elapsed time T2 and to the L level at the elapsed time T4 with the basic delay time T2-T1 of the FF (1). Thereafter, transition to H level and L level is continuously repeated with T6 to T2 as one cycle.

Similarly, as shown in (d), the counter clock 1e-x which is the x component of the counter clock 1e
Transitions to the H level at the elapsed time T2 and to the L level at the elapsed time T6 with the basic delay time T2-T1 of the FF (2). Then, T10-T2 is set to 1
As a cycle, the transition to the H level and the L level is continuously repeated.

Next, as shown in (e), the load pulse 1h-x, which is the x component of the load clock 1h inside the MOS counter 12, is supplied to the gate basic delay time of the level conversion circuit 14b and the timing compensation circuit 13 The transition to the H level occurs at the time point of the elapsed time T3, with the total time T3-T2 of the wiring delay time of FIG. At the same time, load pulse 1h-x
Are load data 1c-m + 1 to load data 1c-n
Is set to each of the FFs of FF (m + 1) to FF (n), and at the time point of the elapsed time T7, the data again transitions to the L level, and the data setting ends.

That is, the rise edge Ex of the counter clock 1ex (see (d) in the figure) becomes the rise edge Ex1 at the time of the elapsed time T4 via the gate basic delay time and the wiring delay time. Then, the time width of the elapsed times T1 to T3 of the load clock 1b is adjusted to the time width of the elapsed times T3 to T7 of the load pulse 1h-x, thereby securing the removal time T7-T4 of FF (m + 1).

Similarly, as shown in (f), the counter clock 1g-y which is the y component of the counter clock 1g
Transitions to the H level at the elapsed time T2 and to the L level at the elapsed time T4 with the basic delay time T2-T1 of the FF (1). Thereafter, transition to H level and L level is continuously repeated with T6 to T2 as one cycle.

Similarly, as shown in (g), the counter clock 1e-y which is the y component of the counter clock 1e
Changes to the H level at the time point of the elapsed time T6 with the basic delay time T6-T1 of the FF (2), and the elapsed time T10
At this point, the state transits to the L level. Thereafter, transition to H level and L level is alternately repeated with T10-T2 as one cycle.

Next, as shown in (h), the load pulse 1h-y, which is the y component of the load clock 1h inside the MOS counter 12, is supplied to the gate basic delay time of the level conversion circuit 14c and the timing compensation circuit 13 The transition to the H level occurs at the time point of the elapsed time T3, with the total time T3-T2 of the wiring delay time of FIG. At the same time, load pulse 1h-y
Are load data 1c-m + 1 to load data 1c-n
Is set to each of the FFs of FF (m + 1) to FF (n), and at the time point of the elapsed time T5, the data transits again to the L level, and the data setting ends.

That is, the rising edge Ey of the counter clock 1e-y (see (g) in the figure) becomes the rising edge Ey1 at the time of the elapsed time T8 via the gate basic delay time and the wiring delay time. Then, the release time T8-T5 of FF (m + 1) is secured by adjusting the time width of the elapsed times T1 to T3 of the load clock 1b to the time width of the elapsed times T3 to T5 of the load pulse 1h-y.

Further, the timing compensating circuit 13 loads the load data 1a- input via the level converting circuit 14a.
2, the pulse width of the load pulse 1h-x is adjusted, and the timing correction data 1 is converted into data using the remove time and the release time as an adjustment time.
f, the load pulse 1h-x and the load pulse 1h-
The generation timing and time width of y are variably controlled.

As described above, according to the ripple counter 10 in the present embodiment, the counter basic clock 1d output from the FF (1) to FF (2) provided in the bipolar circuit on the gate array. , The bipolar counter 11 for counting the load data 1a input by the load clock 1b, and the corrected FF (m + 1) to FF (n) provided in the MOS type circuit on the gate array. M for counting the load data 1c input by the load clock 1h by the counter clock 1i
Based on the OS type counter 12 and the level of the load data 1a input to the flip-flop circuit FF (2) at the last stage in the bipolar circuit,
The pulse width of the counter clock 1e transferred to the OS-type circuit is adjusted, and based on the timing adjustment data 1f input from the outside, the MO is output from the bipolar circuit.
A timing adjusting circuit 13 for adjusting the time width of the counter clock 1e transferred to the S circuit.

Therefore, it is possible to compensate for the delay time of the level conversion circuits 14b and 14c generated between the two types of circuits having different operation speeds and the wiring delay of each circuit. For this reason, it is possible to easily and accurately correct a shift in the input timing of the load clock 1h or the counter clock 1i due to a difference in operation speed or a variation in characteristics between the bipolar circuit and the MOS circuit included in the ripple counter 10. Further, since the ripple counter 10 and the arrangement and wiring thereof corresponding to the increase in the signal speed can be easily configured, the number of design and development steps can be reduced.

The period of the counter basic clock, the load clock, etc., and the number of FFs in each circuit are arbitrary, and other details such as the detailed configuration and arrangement of the circuits are not deviated from the scope of the present invention. Can be changed.

[0043]

According to the present invention, the shift of the input timing of the data synchronous clock or the counter clock due to the difference in the operation speed or the variation in the characteristics between the bipolar circuit and the MOS circuit constituting the ripple counter can be easily and easily improved. Can be compensated for accuracy. In addition, since a ripple counter corresponding to an increase in signal speed and its arrangement and wiring can be easily configured, design and development man-hours can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a functional configuration of a ripple counter 10 according to an embodiment of the present invention.

FIG. 2 is a circuit configuration diagram of the ripple counter 10 of FIG.

FIG. 3 is a timing chart of the ripple counter 10 of FIG.

FIG. 4 is a block diagram showing a functional configuration of a conventional ripple counter 20.

FIG. 5 is a circuit configuration diagram of the ripple counter 20 of FIG.

[Explanation of symbols]

1, 2 Ripple counter 1a, 2a Load data 1b, 2b Load clock 1c, 2c Load data 1d, 2d Counter basic clock 1e, 2e Counter clock 1e-x Counter clock 1ey Counter edge 1f Timing correction data 1g Counter clock 1g- x counter clock 1g-y counter edge 1h load clock 1h-x load pulse 1h-y load pulse 1i counter clock 11,21 bipolar counter 12,22 MOS counter 13 timing correction circuit 14a, 14b, 14c, 24a, 24b level Conversion circuit 25a, 25b Delay circuit

Claims (6)

[Claims] A first counter for counting load data input by a predetermined data synchronization clock in accordance with a counter clock output from a flip-flop circuit disposed in a bipolar circuit on a gate array; A second counter means for counting load data input by a predetermined data synchronization clock in accordance with a counter clock input to a flip-flop circuit provided in a MOS type circuit on the gate array. And a compensating means for compensating a time width of the data synchronization clock so that the second counter means can perform a counting operation. 2. The counter clock transferred from the bipolar circuit to the MOS type circuit based on a clock level of the load data input to a last-stage flip-flop circuit in the bipolar circuit. 2. The ripple counter according to claim 1, wherein the pulse width is compensated. 3. The compensation circuit according to claim 2, wherein said compensation means is adapted to output said MOS signal from said bipolar circuit based on compensation data inputted from outside.
2. The ripple counter according to claim 1, wherein a time width of at least one of the data synchronization clock transferred to the circuit and the counter clock is adjusted. 4. A first counter step of counting load data input by a predetermined data synchronization clock in accordance with a counter clock output from a flip-flop circuit disposed in a bipolar circuit on a gate array; A second counter step of counting load data input by a predetermined data synchronization clock in accordance with a counter clock input to a flip-flop circuit provided in a MOS type circuit on the gate array; Adjusting a time width of the data synchronization clock so that a counting operation can be performed in the step. 5. The counter clock transferred from the bipolar circuit to the MOS type circuit based on a clock level of the load data input to a last-stage flip-flop circuit in the bipolar circuit. 5. The method according to claim 4, wherein the pulse width is adjusted. 6. The compensating step includes the steps of:
5. The counter compensation method for a ripple counter according to claim 4, wherein a time width of at least one of the data synchronization clock transferred to the circuit and the counter clock is compensated.