JP2001306265A - Storage controller and method for controlling the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the efficiency of an access to a shared memory, and to improve data transferring performance in a storage controller in a multi- processor constitution equipped with a shared memory. SOLUTION: In the disk array controller 600 constituted so that a channel adapter mounting processor 17 with plural channel adapters 11 for performing input and output control with a host computer 500 and plural disk adapter loading processors 21 of plural disk adapters 20 for performing input and output control with a magnetic disk device 50 can perform access to a shared memory 32, a shared memory loading processor 36 equipped with a built-in data cache 38 is arranged, and access from the channel adapter loading processor 17 and the disk adapter loading processors 21 to the shared memory 32 is executed through the built-in data cache 38 so that a time required for the access to the shared memory 32 can be reduced, and that the performance of the disk array controller 600 can be improved.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a storage control device and a control technique thereof, and more particularly, to a storage control device comprising a plurality of processors sharing a memory and distributing data from a host computer to a plurality of storage devices such as magnetic disk devices. The present invention relates to a technology that is effective when applied to a disk array control device or the like that performs a control operation of storing data.

[0002]

2. Description of the Related Art In recent years, in order to obtain higher performance, a system for executing data transfer processing in parallel with a plurality of channel adapters and a plurality of disk adapters has become mainstream in order to obtain higher performance.

For example, in the reference technology shown in FIG. 11, a host computer 1100 and a disk array controller 11
01, a plurality of channel adapters 1010 for performing data transfer control between the hard disk drives, a plurality of disk adapters 1020 for performing data transfer control between the magnetic disk device 1050 and the disk array control device 1101, and between each adapter and the magnetic disk device 1050. Shared memory unit 1 having a cache function for temporarily storing data transmitted and received by the CPU and a shared memory function for storing control information between a plurality of channel adapters 1010 and disk adapters 1020
030, and two common buses 1040 between each adapter.
It is conceivable that the configuration is such that the connection is made by the user and accessible from all adapters. The disk adapter 1020 is connected to the magnetic disk device 1050 and the drive interface 106.
0,1061.

[0004]

The common bus structure of the reference technology shown in FIG.
When the number of accesses to the shared memory unit 1030 increases as the number of disk adapters 1020 increases, the common bus 1
040, which has been a factor limiting the I / O performance of the disk array controller 1101.

Therefore, as shown in the reference technology of FIG. 12, a channel adapter 1011 and a disk adapter 1020
In order to reduce the access path utilization rate to the shared memory unit 1030 and to reduce the shared memory response time by connecting the shared memory unit 1030 to the shared memory unit 1030 on a one-to-one basis.

However, the host computer 110
The data transfer rate from 0 is remarkably increased, and the I / O performance required for the disk array controller 1101 is larger. The disk array controller 1101 has responded by increasing the number of channel adapters 1010 and disk adapters 1020, increasing the number of processors mounted on each adapter, and increasing the processing capacity of the mounted processors. The number of accesses to the shared memory unit 1030 is not only increased, but also the utilization rate of the access path to the shared memory unit 1030 is increased.
Shared memory 1032 and shared memory control circuit 1031
Also, the utilization rate of the data transfer path between them becomes saturated, and the I / O performance of the disk array controller 1101 is limited due to the increase in the shared memory access time.

An object of the present invention is to improve the data input / output performance by shortening the access occupation time of each processor to a shared memory in a storage control device having a multiprocessor configuration.

It is another object of the present invention to improve the data input / output performance by reducing the number of accesses to the shared memory of each processor in a storage control device having a multiprocessor configuration.

Another object of the present invention is to increase the number of processors and increase the complexity of processing in the processing time of each processor mounted on a channel adapter / disk adapter in a disk array controller. An object of the present invention is to reduce the memory access occupation time.

Another object of the present invention is to increase the number of processors and increase the complexity of processing in the processing time of each processor mounted on a channel adapter / disk adapter in a disk array controller. An object of the present invention is to reduce the number of accesses to a memory.

[0011]

According to the present invention, there are provided a plurality of first processors for controlling transmission and reception of information between a higher-level device and a storage device, and a first processor for transmitting and receiving information between the higher-level device and the storage device. And a shared memory unit having a shared memory for storing the information of the first processor and the second information used in the first processor. And a second processor for controlling access to the server.

Further, the present invention provides a plurality of first processors for controlling transmission and reception of information between a higher-level device and a storage device, and a first processor for transmitting and receiving information between the higher-level device and the storage device.
And a shared memory unit having a shared memory in which the first information and the second information used by the first processor are stored. A second processor having a data cache in which first and second information exchanged with the shared memory is temporarily stored is provided, and a first and a second in the shared memory of the first processor are arranged. The information access request is responded via the data cache as much as possible.

More specifically, a disk array controller, which is an example of a storage controller of the present invention, includes a shared memory unit as a means for shortening the time for reading / writing shared memory from a processor equipped with a channel adapter and a disk adapter. And a processor with a shared memory having a built-in data cache. The access time of the data cache built in the processor with shared memory is usually 1/10 of that of the fastest general-purpose memory.
It is known that the following time is enough. As an increasing time, the processing step time of the processor equipped with the shared memory slightly occurs, but the processor processing clock has been dramatically increased in recent years, and the processor processing of several clocks is less than 1/10 of the access time of the general-purpose memory. Yes, not overhead. If the shared memory data is written in advance to the data cache of the processor equipped with the shared memory and this data is read, the occupation time of the shared memory access of the processor equipped with the channel adapter / disk adapter is reduced.

In the shared memory, there are many control processes in which all processors communicate with each other by writing / reading flag control information. In such a process, the shared memory address is the same for each processor access. Therefore, the probability of hitting the built-in data cache of the processor equipped with the shared memory is extremely high, which is effective for reducing the access time of the shared memory.

Further, in the present invention, as means for increasing the hit rate of the built-in data cache of the processor equipped with the shared memory, the identification number of the channel adapter / disk adapter equipped with the access source is recognized, and the previously accessed address is read ahead. Means, means for prefetching the peripheral address of the access address, and means for recognizing the access processing to be executed and predicting the next address.

A general-purpose memory constituting a shared memory generally increases the speed of read / write by burst access or continuous pipeline access of a plurality of words. However, a single read / write has a large overhead and a high speed. The fact is that they have not. Therefore, there is a characteristic that the access time does not increase so much even when a plurality of words are burst-accessed, as compared with the one-time access, and the increase in the access time by pre-reading a plurality of consecutive bytes of data is small.

According to the present invention, as another means for reducing the shared memory access occupation time of the processor with the channel adapter / disk adapter, the processor with the channel adapter / disk adapter accesses the shared memory on behalf of the processor with the shared memory. A method of reducing the number of accesses itself by providing a command interface for performing the command is used.

That is, the processor equipped with the channel adapter / disk adapter performs the branching process based on the data read from the shared memory, and often reads the shared memory further at the branch destination. The number of accesses to the shared memory of the processor equipped with the channel adapter / disk adapter is reduced by causing the processor equipped with the shared memory to substitute an arbitrary processing unit involving multiple accesses. This method is particularly effective for reducing the path utilization rate between the channel adapter / disk adapter and the shared memory unit.

If the above-described means for reducing the number of times of access to the shared memory is used in combination with the use of the built-in data cache of the processor equipped with the shared memory, the number of accesses between the channel adapter and the disk adapter and the shared memory unit is reduced, and By reading the shared memory data from the data cache, the response time from the shared memory unit is also significantly reduced.

[0020]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a conceptual diagram showing an example of the configuration of an information processing system including a storage control device for executing a storage control method according to an embodiment of the present invention.

The information processing system according to the present embodiment comprises a host computer 500 and a disk array subsystem that operates under the host computer 500 and includes a disk array controller 600 and a plurality of magnetic disk devices 50 in a redundant configuration. .

The disk array controller 6 according to the present embodiment
Reference numeral 00 denotes a plurality of channel adapters (PKs) 11 for controlling the exchange of information with one or more host computers 500 via the host interface 700.
, A plurality of disk adapters (PK) 20 for controlling the transfer of information between the plurality of magnetic disk devices 50 via the drive interface 60 and the drive interface 61, and the channel adapter 11 and the disk adapter 20. It comprises a shared memory unit 30.

Each of the channel adapters 11 includes a plurality of processors (MP) 17 with channel adapters, individual processors 17 with channel adapters, and a shared memory unit 3.
The processor adapter (MPA) 18 controls transmission and reception of information via the path interface 19 to and from the processor adapter (MPA) 18.

Similarly, each of the disk adapters 20
Processor (MP) 21 with multiple disk adapters
And a processor adapter (MPA) 22 that controls the transfer of information between the individual MPs 21 and the shared memory unit 30 via the path interface 19.

The shared memory unit 30 has a shared memory control LS
I31 and a shared memory 32 as a storage medium. The shared memory control LSI 31 includes a path interface control 33 having control logic for performing processing such as arbitration of access requests to the shared memory 32 from each of the plurality of MPAs 18 and MPAs 22 via the path interface 19.
And a request to read / write data from / to the shared memory 32 coming from the path interface control 33 via the memory access path 40 and execute data read / write processing to / from the shared memory 32 via the shared memory interface 41. A shared memory control 34 is included.

In the case of this embodiment, the shared memory control LS
Inside the I31, a shared memory processor 36 connected in parallel with the shared memory control 34 with respect to the memory access path 40 is provided.
A request to read / write data from / to the shared memory 32 coming from the processor is simultaneously input to the processor 36 with the shared memory. A built-in data cache 38 is provided inside the processor 36 with the shared memory. A control interface (not shown) is provided between the shared memory mounted processor 36 and the shared memory control 34, and controls access to various types of the shared memory 32 as described later.

The shared memory-equipped processor 36 provided in the shared memory unit 30 operates according to a control program 95 stored in a local memory 35 provided in the shared memory control LSI 31, as exemplified in FIG. I do. In the local memory 35, priority setting information 96 for controlling the priority in access control to the shared memory 32 as described later is stored as needed.
Also, access log information 97 that records the state of access to the shared memory 32 by the channel adapter-equipped processor 17 and the disk adapter-equipped processor 21 is stored.

The processor 36 with a shared memory can be constituted by, for example, a general-purpose microprocessor having a built-in data cache 38, and a shared memory control LS
In the I31, a path interface control 33, a shared memory control 34, and a local memory 35 can be mounted in a one-chip configuration. In this case, the portion of the processor 36 with the shared memory can be manufactured by using the IP (design assets) of the existing general-purpose microprocessor without newly developing it.

The shared memory processor 36 includes a LAN controller 37 provided in the shared memory unit 30 and a hub (HU) provided outside the shared memory unit 30.
B) External service processor (SVP) via 70
A disk array that is connected to the SVP 80 and receives various control information inside the shared memory unit 30 from the SVP 80, and sets the operation status such as the presence or absence of a failure inside the shared memory unit 30 to the SVP 80. It is also used for subsystem management and operation.

As exemplified in FIG. 3, the shared memory 32
For example, the system management information 91 (first information) accessed by the plurality of channel adapter-equipped processors 17, the disk adapter-equipped processors 21 and the like, and the plurality of channel adapter-equipped processors 17, the disk adapter-equipped processors 21 and the like. An inter-processor communication area 92 (first area) used for exchanging control information between each other.
Data), a cache data area 94 in which data (second information) exchanged between the host computer 500 and the magnetic disk device 50 is temporarily stored, and management of data stored in the cache data area 94 (for example, identification). Of the cache management information 93 (first information), which is used for checking the presence or absence of the data, etc.).

In the case of the present embodiment, the plurality of magnetic disk devices 50 are, for example, RAID (Redanda).
nt Arrays of Inexpensive
Disks), a data block obtained by dividing write data from the host computer 500, and a redundant data block generated from the data block are distributed and stored in a plurality of magnetic disk devices 50.

Accordingly, in order to make the management of the cache data area 94 more efficient, for example, the cache management information 9
Reference numeral 3 denotes a cache segment management table 93d in which a real address of an arbitrary data block (segment) in the shared memory 32 is stored, and an address in the cache segment management table 93d of a segment constituting each stripe of RAID. The cache stripe management table 93c, the cache group address management table 93b storing the addresses of the respective stripes belonging to the cache group in the cache stripe management table 93c, and the addresses in the cache group address management table 93b of the cache groups constituting the virtual device are stored. The virtual device group table 93a has a hierarchical structure.

The processor 17 equipped with each channel adapter of the channel adapter 11 and the disk adapter 2
0 individual disk adapter mounted processors 21
In the case of the present embodiment, an access request to the shared memory 32 and the magnetic disk device 50 exchanged with the path interface control 33 via the MPA 18 and the MPA 22 is, for example, as shown in FIG. It is performed using the format.

That is, as illustrated in FIG. 2A, when a write request is issued from the MPA 18 and the MPA 22 to the path interface control 33, the MPA transmission phase 100 (write format)
2 and an address portion 100a for instructing a write position to the magnetic disk device 50, a type of operation such as read / write, a requesting channel adapter 11 (PK), a disk adapter 20 (PK), and a processor with a channel adapter in each PK. 17. Command unit 10 in which information for identifying processor 21 with disk adapter is set
0b, a data section 100c in which write data is stored, and an encoding section 100d used for error checking and error correction in the MPA transmission phase 100.

The MPA transmission phase 100 responds to the MPA
The reception phase 101 includes a status unit 101a including information indicating the execution result of the write process and the like, and an encoding unit 101b used for error checking and error correction of the MPA reception phase 101. When a failure occurs in the write request processing, the MPA reception phase 101 includes, as illustrated in FIG.
1c is added.

On the other hand, as exemplified in FIG.
At the time of a read request issued from the PA 18 and the MPA 22 to the path interface control 33, the MPA transmission phase 102 (read format) includes an address section 102a for designating a read position with respect to the shared memory 32 and the magnetic disk device 50, and a read / write operation. A command section 102b in which information for identifying the type of operation and the channel adapter 11 (PK), disk adapter 20 (PK), and channel adapter-equipped processor 17 and disk adapter-equipped processor 21 in each PK are set;
And an encoding unit 102c used for error checking, error correction, and the like in the MPA transmission phase 102.

Also, the MPA transmitted from the path interface control 33 to the MPA transmission phase 102
The reception phase 103 includes a status section 103a including information indicating the execution result of the read processing, a data section 103b in which read read data is stored, and codes used for error checking and error correction of the MPA reception phase 103. Unit 103c. When a failure occurs in the read request processing, the MPA reception phase 103
As shown in FIG. 2D, the error content part 1
03d is added.

As illustrated in FIG. 2C, an intelligent command (search command) in the present embodiment described below is read format (MPA transmission phase 1).
02-1). That is, the command unit 1
A bit indicating that the instruction is a search instruction different from a normal read instruction is set in 02b. The MPA receiving phase 103-
1, the data section 103b stores the cache data area 94 in the shared memory 32 instead of the read data.
The storage location (cache real address) of the target data block that was hit in is stored.

The data write transfer from the host computer 500 to the magnetic disk device 50 will be described.
The channel adapter 11 receives the data transferred from the host computer 500 via the host interface 700 and, under the control of the processor 17 equipped with the channel adapter, sends an MPA transmission phase 1 comprising an address, a command, write data, etc. from the MPA 18 to the shared memory unit 30.
00 is transmitted. At this time, the channel adapter 11 is equipped with a plurality of channel adapter-equipped processors 17, each of which requests data transfer to the shared memory unit 30. Therefore, the MPA 18 arbitrates the transfer request of each of the channel adapter-equipped processors 17, Access to the shared memory unit 30 is narrowed down. In the present embodiment, the number of path interfaces 19 from the channel adapter 11 and the disk adapter 20 to the shared memory unit 30 is one, but the path interface 19 may have a plurality of paths.

The shared memory control LSI 31 mounted on the shared memory unit 30 has the path interface control 33, the shared memory processor 36, the shared memory control 34, and the local memory 35 built therein, as described above.

The path interface control 33 receives data (MPA transmission phase 100) sent from the channel adapter 11. Path interface control 33
Recognizes from the address and command of the transfer data (MPA transmission phase 100) that the address is an address write in the shared memory 32, and requests the shared memory control 34 to write the corresponding address.

The shared memory control 34 writes the data transferred from the path interface control 33 to the shared memory 32 via the memory access path 40. At this time, the shared memory processor 36 simultaneously refers to the data between the path interface control 33 and the shared memory control 34 via the memory access path 40, and
8, the shared memory write data is written. The shared memory-equipped processor 36 also stores the processor number of the channel adapter 11 that is the access source in addition to the shared memory write data. When the shared memory write is completed, the shared memory control 34 reports the completion to the path interface control 33. The path interface control 33 reports the end of the shared memory write access to the channel adapter 11 via the path interface 19 as a status. The shared memory write operation of the processor 17 with the channel adapter is performed according to the above procedure. The shared memory write operation of the disk adapter-equipped processor 21 has the same procedure.

The processor 17 equipped with the channel adapter mounted on the channel adapter 11 performs the same data write procedure as described above, and the communication area between the channel adapter 11 and the disk adapter 20 on the shared memory 32 (communication area 92 between processors). Host computer 500
Write a flag indicating that the data has been written. On the other hand, the disk adapter-mounted processor 21 periodically reads information in the inter-processor communication area 92 on the shared memory 32 and checks whether data of the host computer 500 has been written.

At this time, the shared memory reading procedure is performed by the MPA 22 under the control of the processor 21 equipped with the disk adapter.
Sends an address and a command (MPA transmission phase 102) to the shared memory unit 30. At this time, the disk adapter 20 has a plurality of disk adapter-equipped processors 21 mounted thereon, each of which makes a data transfer request to the shared memory unit 30. Therefore, the MPA 22 arbitrates the transfer request of each disk adapter-equipped processor 21, Access to the shared memory unit 30 is narrowed down. In FIG. 1 of the present embodiment, the disk adapter 20 to the shared memory unit 3
Although there is one path interface 19 to 0, it may have a plurality of paths.

The shared memory control LSI 31 mounted on the shared memory unit 30 receives the data (MPA transmission phase 102) sent from the disk adapter 20 by the path interface control 33. The path interface control 33 recognizes from the address and command of the transfer data (MPA transmission phase 102) that the address is a certain address read of the shared memory 32, and requests the shared memory control 34 to read the corresponding address.

At this time, the processor 36 with the shared memory determines whether or not the data of the corresponding address exists in the internal data cache 38, and if so, reads the data from the internal data cache 38 and sends the data to the path interface control 33. Data is transmitted, and the shared memory control 34 cancels the access to the shared memory at the corresponding address via a control interface (not shown). If no hit is found in the built-in data cache 38 of the shared memory processor 36, the shared memory control 34 continues the processing, reads the shared memory 32, and sends the read data to the path interface control 33. The processor 36 with the shared memory stores the processor number of the disk adapter 20 that is the access source even when the shared memory is read.

The path interface controller 33 transmits read data from the shared memory 32 to the disk adapter 20 via the path interface 19. The disk adapter-equipped processor 21 can fetch the data of the specified shared memory address. Note that the read operation of the shared memory 32 by the processor 17 with the channel adapter has the same procedure.

The processor 21 with the disk adapter reads the data transferred from the channel adapter 11 to the shared memory 32, transfers the data read from the shared memory 32 via the drive interface 60 to the magnetic disk device 50, Writes the transfer data.

The data read request from the host computer 500 to the disk array controller 600 is transmitted to the processor 17 with the channel adapter via the host interface 700, and the requested data is stored in the shared memory 32 under the control of the processor 17 with the channel adapter. A process of reading the cache management information 93 in the shared memory 32 is performed to confirm whether or not there is any.
If the requested data exists, the processor 17 with the channel adapter executes a read process from the shared memory 32. When the requested data does not exist, the channel adapter-equipped processor 17 requests the disk adapter-equipped processor 21 via the inter-processor communication area 92 of the shared memory 32 to read the requested data from the magnetic disk device 50. The disk adapter-equipped processor 21 that has received the command reads the requested data from the magnetic disk device 50 via the drive interface 60 and transfers the requested data to the shared memory 32 via the path interface 19. When the transfer is completed, the processor 21 with the disk adapter loads the processor 1 with the channel adapter via the inter-processor communication area 92 of the shared memory 32.
7 is notified that the transfer has been completed. In response, the processor 17 with the channel adapter performs a read process on the shared memory 32 and transfers the requested data to the host computer 500.

Next, an example of the prefetching process of the processor 36 with the shared memory will be described with reference to FIG.

In the read processing of the shared memory 32, the processor 36 with the shared memory performs the path interface control 3
3 determines whether the data is to be read from or written to the shared memory 32 based on the information such as the address and the command included in the MPA transmission phase 102 to the shared memory 32 received (processing 11
0) If it is a read, the processor 36 with the shared memory performs a hit / miss determination of the internal data cache 38 (process 111). If there is a hit, the request data is read from the built-in data cache 38 of the processor 36 with the shared memory (processing 112), and the requested data is transferred to the path interface control 33 (processing 119). In this case, the processing is performed in a shorter time than reading the request data from the shared memory 32 and transferring the data to the path interface control 33.

On the other hand, when there is no request data in the built-in data cache 38, first, an access address / MP number is collected (process 113), and a shared memory read mode is determined (process 114). In this read mode determination processing, the mode is set in advance in the initial setting, or
It is also possible to automatically select a mode so as to increase the hit rate by a learning program of the processor 36 with the shared memory. When the mode 1 is selected, an n-byte burst read instruction around the access address is issued (process 115). When mode 2 is selected, a burst read instruction or a one-shot read instruction is executed at an address where the next instruction is predicted from the command and the address (process 1).
16). When the mode 3 is selected, the processor issues an instruction to read the address previously accessed by the processor from the access source processor number (MP number) (Process 11).
7). The data read in any of the prefetch modes is stored in the built-in data cache 38 of the processor 36 with the shared memory (process 118). From the shared memory 32 executed in the above-described miss processing to the internal data cache 3
The priority of the read-ahead process to the shared memory 32 is reduced by the shared memory control 34 so that the access to the shared memory 32 is free so as not to hinder the shared memory access process requested from the original channel adapter and disk adapter. It can also be processed during the time zone.

Next, an example of an address priority process in access control of the shared memory 32 by the shared memory mounted processor 36 will be described with reference to FIG.

A plurality of access requests sequentially arriving at the shared memory control 34 from the path interface control 33 via the memory access path 40 are stored in a waiting queue (not shown) provided in the shared memory control 34 and are sequentially executed. However, when performing the following address priority processing, a normal wait queue and a priority wait queue are set as the wait queues, and the execution order of the access requests as described below is controlled.

That is, in the read / write processing of the shared memory 32, the processor 36 with the shared memory transmits the MPA transmission phase 102 / MPA transmission phase 100 to the shared memory 32 received by the path interface control 33 to the shared memory 32.
The address of the shared memory 32 and the processor number of the access source are collected from the address, command, and other information (process 210), and a priority address determination process (process 211) and a priority processor determination process are performed (process 212). . The designation of the priority address and the priority processor is performed by instructions of the processor 17 with the channel adapter and the processor 21 with the disk adapter, and the processor 36 with the shared memory.
Can be specified sequentially. In addition, processor 3 with shared memory
6 MPA transmission phase 1 by learning program
The processing routine of the disk array controller 600 is grasped from the address, command, data, processor number of the 02 / MPA transmission phase 100, and the above-mentioned context log information (access log information 97), and the performance of the disk array controller 600 is high. It is also possible to sequentially set the priority order so that it becomes as follows (process 213).

If it is determined that the access is a priority address or a priority processor, the access is registered in a priority waiting queue (process 215). If it is determined that the access is not the priority address or the priority processor, the access is registered in the normal wait queue (process 214). It is determined whether there is a channel adapter-equipped processor 17 or a disk adapter-equipped processor 21 that has been waiting N times or more (process 216).
Arbitration by round robin is performed in these waiting processors, and the next shared memory access right is determined (process 218).

On the other hand, if the channel adapter-equipped processor 17 or disk adapter-equipped processor 21 has not been waited N times or more, it is determined whether there is a wait in the priority wait queue (process 217). Performs round-robin arbitration among the processors in the priority waiting queue, and determines the next shared memory access right (process 220). Incidentally, the waiting upper limit number N is set in advance. When there is no waiting in the priority waiting queue, arbitration by round robin is performed among the processors in the normal waiting queue,
Determine the next shared memory access right (Process 21
9). Access to the shared memory 32 is performed based on the arbitration result selected for any of the above three types (process 221).

Next, a description will be given of a method in which the processor equipped with the shared memory performs the processing of the processor equipped with the channel adapter 17 and the processor equipped with the disk adapter 21 in accordance with the intelligent command of the present embodiment.

FIG. 13 shows a cache hit / miss determination process in the cache data area 94 by referring to the cache management information 93 in the shared memory 32 by the processor 17 with the channel adapter as a reference technology. A minimum of two accesses and a maximum of four accesses to the shared memory 32 are required until a hit miss in the cache data area 94 is determined. If a hit occurs, four accesses to the shared memory are required until a cache real address is collected. It is.

FIG. 7 shows a cache hit / miss determination process by the processor 17 equipped with a channel adapter using a search command (MPA transmission phase 102-1 and MPA reception phase 103-1) which is an example of an intelligent command according to the present embodiment. An example is shown below.

After converting the host logical address into a virtual device address (process 310), a search command is issued from the virtual device address to the shared memory unit 30 (process 3).
11). Thereafter, status and data are returned from the shared memory unit 30 through the path interface 19 in the MPA reception phase 103-1. The processor 17 with the channel adapter determines whether there is a cache hit from the value of the status (process 312), and reads the cache real address at the time of the hit from the data section 103b (process 313).

As described above, the search command is assigned to the bit of the command section 102b of the MPA transmission phase 102-1 corresponding to the read command of the path interface 19, and the shared memory control LSI 31 receives the shared memory 32 received through the path interface 19 Recognizing that the access request to is a search instruction, the processor 36 with the shared memory performs a cache hit / miss determination.

FIG. 8 shows a processor 3 with a shared memory using a search instruction which is an example of an intelligent command.
6 shows an example of a cache hit / miss determination process by No. 6.

The address section 102a of the MPA transmission phase 102-1 of the shared memory access indicates the virtual device address, and reads the cache group address from the virtual device group table 93a using this address (process 410). A cache hit / miss is determined from the flag in the entry of the cache group address in the cache group address management table 93b (process 411). If there is a hit, the cache stripe management table 93c is read (process 412), and a cache hit / miss is determined from the flag (process 41).
3). If there is a further hit, the cache segment management table 93d is read (process 414), and a cache hit / miss is determined from the flag (process 415). If there is a hit, the cache real address is read from the cache segment management table 93d (process 416), and M is transmitted to the transfer source channel adapter through the path interface 19 based on the PK number of the command section 102b.
The flag hit in the PA receiving phase 103-1 is set in the status section 103a, and the cache real address is returned as read data in the data section 103b (process 416). If a mistake is made, when the mistake is found, in the MPA reception phase 103-1, a flag indicating the mistake is set in the status section 103a through the path interface 19 to the channel adapter which is the transfer source, and the arbitrary data is set as the read data in the data section. The document is sent back on 103b (process 417).

FIG. 14 shows a path interface protocol and a memory interface protocol when a cache hit / miss determination is performed by a conceivable reference technique.

FIG. 9 shows a case in which a cache hit / miss determination in the shared memory 32 is performed by the shared memory processor 36 using the search instruction according to the present embodiment. An example of a protocol when a cache miss occurs and access to the shared memory 32 occurs is shown.

FIG. 10 shows an example of a protocol when the search instruction according to the present embodiment is used and a hit occurs in the built-in data cache 38 of the processor 36 with a shared memory.

9 and FIG. 10 of this embodiment, the number of uses of the path interface 19 is greatly reduced as compared with the case of the reference technology shown in FIG. It can be seen that the speeding up of access can be expected by reducing the usage rate.

Using the search command of this embodiment,
It can be seen that the number of uses of the path interface 19 is reduced, the utilization rate (load) of the path interface 19 is reduced, and the hit / miss determination time in the cache data area 94 of the shared memory 32 is reduced. Further, if several times of reading to the shared memory 32 by the search command hit the built-in data cache 38 of the processor 36 with the shared memory, the cache hit / miss determination time can be further reduced.

According to the present embodiment, the shared memory 32 in which the cache management information 93, the cache data area 94, the inter-processor communication area 92, and the like are stored is transmitted from the plurality of channel adapter-mounted processors 17, the disk adapter-mounted processors 21 and the like. In the disk array control device 600 where the access load is concentrated, the shared memory processor 36 having the built-in data cache 38 is arranged in the shared memory unit 30 so that the processor 36 By responding using the data in the data cache 38, the time required for accessing the shared memory 32 can be reduced.

The cache hit / miss determination processing in the shared memory 32 involving multiple accesses to the cache management information 93 in the shared memory 32 is performed by the shared memory processor 36 by an intelligent command. Thus, the number of accesses to the shared memory 32 can be reduced.

As a result, the disk array controller 60
0, and the response performance of the entire disk array subsystem including the disk array control device 600 and the magnetic disk device 50 to input / output requests of the host computer 500 is improved.

The invention described in the claims of the present application is expressed in another way as follows.

<1> One or more channel adapters for processing input / output data transferred from one or more host computers and one or more channel adapters for processing input / output data transferred from one or more magnetic disk devices And a disk array controller having a second processor in a shared memory unit for storing data of the magnetic disk device and information on the magnetic disk device.

<2> The disk array control device according to item <1>, wherein the second processor mounted on the shared memory unit has a built-in data cache and has means for prefetching shared memory data. Disk array controller.

<3> In the disk array control device according to item <2>, the prefetching means for the shared memory data may include a channel adapter or a disk adapter mounted on a disk adapter added to data transferred to the shared memory unit. It has a learning function of prefetching shared memory data of an address previously accessed by the first processor from the recognition ID of one processor, prefetching address peripheral data from an access address, and increasing the hit rate of the data cache. A disk array control device, characterized in that:

<4> The disk array control device according to item <1>, wherein the second memory mounted on the shared memory unit is
Wherein the processor receives an intelligent command from a first processor mounted on a channel adapter or a disk adapter, and substitutes for the processing of the first processor.

<5> The disk array control device according to item <1>, wherein the second memory mounted on the shared memory unit is
Wherein the processor manages the failure information in the shared memory unit and switches a signal path in the shared memory based on the failure statistical information.

<6> The disk array control device according to item <1>, wherein the second memory mounted on the shared memory unit is
Has a means for recognizing an access address to the shared memory by the first processor and determining an address to respond at a high speed and an address to respond to at a low speed. A disk array control device, which preferentially accesses the disk array.

<7> The disk array controller according to item <1>, wherein the second memory mounted on the shared memory unit is
Means for collecting first processor information of the channel adapter and the disk adapter, and a dedicated processor for enabling communication between a second processor mounted on the shared memory unit and an external processor for maintenance. A disk array control device comprising communication means.

<8> In the disk array control device according to item <1>, the processor mounted with the shared memory unit may be configured such that the processor mounted on the shared memory unit is configured to execute the processing when the power is turned on or periodically based on the configuration information of the external processor for maintenance. A disk array control device for performing a diagnosis.

<9> In the disk array control device according to any one of the items <1> to <8>, the second processor mounted on the shared memory unit may transmit the transfer data from the channel adapter and the disk adapter. A disk array control device which is packaged in one chip including a reception / transmission circuit and a shared memory control circuit.

<10> In the disk array control device according to any one of items <1> to <9>, a plurality of the shared memory units exist, and the channel adapter and the disk adapter are paired with the respective shared memory units. A disk array control device, wherein the shared memory is accessed by an interface connected to the storage device.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the above-described embodiments, and can be variously modified without departing from the gist thereof. Needless to say, there is.

For example, in the above-described embodiment, a case where the present invention is applied to a disk array control device as an example of a storage control device has been described. However, a general configuration having a plurality of processors commonly accessing a shared memory is described. It can be widely applied to storage control devices.

[0087]

According to the storage control device of the present invention, in a storage control device having a multiprocessor configuration, it is possible to improve the data input / output performance by shortening the access occupation time of each processor to the shared memory. The effect is obtained.

According to the storage control device of the present invention, in a storage control device having a multiprocessor configuration, there is an effect that the data input / output performance can be improved by reducing the number of times each processor accesses the shared memory. can get.

According to the storage controller of the present invention, in the disk array controller, the processing time of each processor mounted on the channel adapter / disk adapter increases due to the increase in the number of processors and the complexity of the processing. There is an effect that the shared memory access occupation time can be reduced.

According to the storage controller of the present invention, in the disk array controller, the processing time of each processor mounted on the channel adapter / disk adapter increases due to the increase in the number of processors and the complexity of the processing. Thus, the number of accesses to the shared memory can be reduced.

According to the control method of the storage control device of the present invention, in the storage control device having a multiprocessor configuration, it is possible to improve the data input / output performance by shortening the access occupation time of each processor to the shared memory. Can be obtained.

According to the control method of the storage control device of the present invention, in the storage control device having a multiprocessor configuration, it is possible to improve the data input / output performance by reducing the number of times each processor accesses the shared memory. The effect is obtained.

According to the control method of the storage control device of the present invention, in the disk array control device, the number of processors increases and the processing becomes complicated in the processing time of each processor mounted on the channel adapter / disk adapter. The effect is obtained that the increased shared memory access occupation time can be reduced.

According to the control method of the storage control device of the present invention, in the disk array control device, the number of processors increases and the processing becomes complicated in the processing time of each processor mounted on the channel adapter / disk adapter. The effect is obtained that the number of accesses to the shared memory, which is increasing, can be reduced.

[Brief description of the drawings]

FIG. 1 is a conceptual diagram illustrating an example of a configuration of an information processing system including a storage control device that executes a storage control method according to an embodiment of the present invention.

FIGS. 2A to 2D are conceptual diagrams illustrating an example of a format of a command transmission / reception phase used in a storage control device that executes a storage control method according to an embodiment of the present invention.

FIG. 3 is a conceptual diagram illustrating an example of information stored in a shared memory provided in a storage control device that executes a storage control method according to an embodiment of the present invention.

FIG. 4 is a conceptual diagram showing an example of information stored in a local memory provided in a storage control device that performs a storage control method according to an embodiment of the present invention.

FIG. 5 is a flowchart illustrating an example of an operation of a processor equipped with a shared memory provided in a storage control device that executes a storage control method according to an embodiment of the present invention.

FIG. 6 is a flowchart illustrating an example of an operation of a processor equipped with a shared memory provided in a storage control device that executes a storage control method according to an embodiment of the present invention.

FIG. 7 is a flowchart illustrating an example of an operation of a processor equipped with a shared memory provided in a storage control device that executes a storage control method according to an embodiment of the present invention.

FIG. 8 is a flowchart illustrating an example of an operation of a processor equipped with a shared memory provided in a storage control device that executes a storage control method according to an embodiment of the present invention.

FIG. 9 is a conceptual diagram illustrating an example of an operation of a processor equipped with a shared memory provided in a storage control device that executes a storage control method according to an embodiment of the present invention.

FIG. 10 is a conceptual diagram illustrating an example of an operation of a processor equipped with a shared memory provided in a storage control device that executes a storage control method according to an embodiment of the present invention.

FIG. 11 is a conceptual diagram illustrating an example of a configuration of a disk array subsystem according to a reference technique of the present invention.

FIG. 12 is a conceptual diagram showing an example of a configuration of a disk array subsystem as a reference technology of the present invention.

FIG. 13 is a flowchart illustrating an example of an operation of a disk array subsystem according to a reference technique of the present invention.

FIG. 14 is a conceptual diagram illustrating an example of an operation of a disk array subsystem according to a reference technique of the present invention.

[Explanation of symbols]

11: channel adapter (PK), 17: processor (MP) with channel adapter (first processor), 1
8: Processor Adapter (MPA), 19: Path Interface, 20: Disk Adapter (PK), 21: Processor with Disk Adapter (First Processor)
(MP), 22 ... Processor adapter (MPA), 30
... shared memory unit, 31 ... shared memory control LSI, 32 ...
Shared memory, 33: path interface control, 34: shared memory control, 35: local memory, 36: processor with shared memory (second processor), 37: LAN
Controller 38 internal data cache 40 memory access path 41 shared memory interface
50: magnetic disk device, 60: drive interface, 61: drive interface, 70: hub (HU
B), 80: Service processor (SVP), 91: System management information, 92: Inter-processor communication area, 93
... Cache management information, 93a ... Virtual device group table, 93b ... Cache group address management table, 93c ... Cache stripe management table,
93d: cache segment management table, 94: cache data area, 95: control program, 96: priority setting information, 97: access log information, 100: MP
A transmission phase (first command means), 100a ... address section, 100b ... command section, 100c ... data section, 100d ... code section, 101 ... MPA reception phase (first command means), 101a ... status section, 1
01b: code part, 101c: error content part, 102: M
PA transmission phase (second command means), 102a ...
Address part, 102b command part, 102c code part, 103 MPA reception phase (second command means), 103a status part, 103b data part,
103c: code part, 103d: error content part, 102-
1 ... MPA transmission phase (third command means), 10
3-1 MPA reception phase (third command means)
500: host computer; 600: disk array controller; 700: host interface.

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) G06F 12/08 G06F 12/08 Q 320 320 13/12 330 13/12 330T F-term (Reference) 5B005 JJ11 KK03 MM11 UU33 5B014 EB05 GC36 5B060 KA02 KA03 5B065 BA01 CA11 CA30 CH01

Claims (5)

[Claims] A plurality of first processors for controlling transmission and reception of information between a higher-level device and a storage device; first information transmitted and received between the higher-level device and the storage device; A shared memory unit having a shared memory in which second information used by the first processor is stored, wherein the shared memory unit includes the shared memory of the first processor. Storage control device, comprising a second processor for controlling access to the storage device. 2. The storage control device according to claim 1, wherein
The second processor includes: a data cache in which the first and second information exchanged between the first processor and the shared memory are temporarily stored; and a data cache stored in the shared memory. And a control logic for controlling read-ahead of first and second information to the data cache. 3. The storage control device according to claim 1, wherein the first processor and the second memory for the shared memory are provided between the first processor and the shared memory unit. First command means for executing writing of information; second command means for executing reading of the first and second information from the shared memory to the first processor; and And a third command means for causing the second processor to perform an operation of checking presence / absence of the first and second information in the shared memory. 4. A plurality of first processors for controlling transmission and reception of information between a host device and a storage device, and first information and the first information transferred between the host device and the storage device. A shared memory unit provided with a shared memory in which second information used by the processor is stored, wherein the shared memory unit includes the first processor and the shared processor. A second processor provided with a data cache in which the first and second information exchanged with the shared memory is temporarily stored, wherein the second processor in the shared memory of the first processor is arranged; A control method for a storage control device, characterized by responding to an access request for first and second information via the data cache as much as possible. 5. The control method for a storage control device according to claim 4, wherein the second processor checks whether the first and second information are present in the shared memory instead of the first processor. A method for controlling a storage control device, which performs processing on behalf of the storage control device.