JP2001297127A - Method for optimizing delay of logic circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve the conventional problems such that much manhour is required and the area of a layout is increased because the change, optimization and re-layout processing of a circuit are repeated until a delay restriction condi tion is satisfied in order to retry the timing verification of the whole logic circuit when violation of delay restriction is generated in a part of the circuit though there is an already optimized result. SOLUTION: A delay restriction violation cell is specified, a 2nd logic cell existing near the violation cell and having the same logic as the violation cell and high driving capacity is retrieved on the basis of the arrangement cell information of all logic cells and wiring information, a net list is prepared by substituting the 2nd logic cell for the violation cell, and the timing of a signal route including the substituted cell is verified. When there is no restriction violation, wiring correction for substituting the input/output of the 2nd logic cell for that of the violation cell is performed and it is confirmed that there is no restriction violation in the whole logic circuit. Thus delay restriction violation can be quickly improved only by wiring correction without changing a mask layout.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a critical path delay verification method for determining an operating frequency of an LSI in a timing design of a semiconductor logic circuit.

[0002]

2. Description of the Related Art As a prior art, FIG. 3 shows a general delay verification method for a logic circuit. In FIG. 3, 101 is an initial synthesis step, 102 is an initial layout step, 103 is a circuit optimization step, 104 is a re-layout step, and 105 is a delay constraint violation determination step.

The circuit after the initial layout is repeatedly subjected to circuit optimization and re-layout until the delay constraint is satisfied.

[0004]

However, in the above-mentioned conventional technology configuration, if a delay constraint violation occurs in some circuits even though the result of optimization already exists, the timing of the entire logic circuit is reduced. In order to perform verification again, circuit change, optimization, and re-layout processing are repeated until the delay constraint condition is satisfied, resulting in a large number of steps or an increase in layout area.

[0005]

According to the present invention, there is provided a method for verifying the delay of a logic circuit formed by arranging a plurality of cells each having a logic function and interconnecting the cells with each other. A constraint violation determining step of determining a delay value between paths and confirming the presence or absence of a constraint violation; a violation factor analyzing step of identifying a signal path that has caused a constraint violation based on the constraint violation determination; and a signal having a constraint violation. Searching for a second cell having the same logic and a higher driving capability in the vicinity of the first cell included in the path, based on the arrangement cell information and the wiring information in another signal path on the layout; First
A step of confirming that a delay constraint violation does not occur in both signal paths even when the input / output of the cell is reconnected to the input / output of the second cell; and the input / output of the first cell and the second cell And a circuit correcting step of reconnecting.

Further, if it is determined that the constraint violation cannot be eliminated by the modified layout created in the replacement circuit modifying step, the first cell is placed in the first logical level based on the logical level information obtained by further expanding the cell function. And replaces the second logic level which is replaceable and has a high driving capability with the first logic level.
And a step of confirming that the replacement of the input / output of the first logic level with the input / output of the second logic level does not cause a delay constraint violation in both signal paths. And a replacement circuit correcting step for switching the input and output of the first cell and the second cell.

[0007]

(Embodiment 1) Hereinafter, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 shows an algorithm of a delay optimizing method according to the first embodiment of the present invention.

First, referring to FIG. 1, a step 103 is performed based on the initial synthesis in the step 101 and the initial layout in the step 102.
After performing the optimization in step 104, the layout is re-laid out in step 104. The placement cell information 111 such as the driving capacity / delay coefficient and area of all the logic cells placed in this step 104, and the resistance value of the wiring between all the logic cells Information 1 such as wiring, capacitance value, wiring shape, etc.
Extract 12 In step 105, the delay constraint of all signal paths set in advance and the actual delay information determined in step 104 are compared to determine whether there is a constraint violation in all signal paths. If there is no constraint violation, the re-layout result in step 104 becomes the final data, and the delay optimization ends. The case where there is a constraint violation will be described with reference to FIG. FIG. 6 shows details of the algorithm when there is a constraint violation. Step 1
In step 06, the signal path causing the constraint violation is analyzed for the constraint violation factor, and in step 131, the constraint violation cell is specified. A replacement cell search step 107 for replacing the specified constraint violation cell includes a step 132 of searching for a replacement candidate cell having the same logic as a neighboring constraint violation cell, a step 133 of comparing the driving capability of the replacement candidate cell, and a replacement step. Step 1 for determining target cell
34. The replacement circuit confirmation step 108 includes a netlist creation step 135 in which both inputs and outputs after cell replacement are reconnected, a timing verification step 136 for both reconnected paths, and a step 137 for determining whether there is a delay constraint violation. The replacement circuit correction step 109 performs a layout creation step 138 after cell replacement in which both inputs and outputs are connected. The above steps will be specifically described with reference to FIGS. 4 shows an example of arrangement cell information, FIG. 5 shows an example of wiring information, FIG. 7 shows an example of a netlist A (a net list after replacement of a logic cell), and FIG. 8 shows an example of a netlist B (a netlist after replacement of a logic cell). Is shown. In FIG. 4, information such as the driving capability, delay time, and area of all the cells including the logic cells 211 to 233 is included in the arrangement cell information 111. In FIG. 5, all the cells including the logic cells 211 to 233 are connected. Information such as wiring resistance, capacitance, and wiring shape is wiring information 112.
Included in. In the violating cell specifying step 131 of FIG. 6, when the delay constraint violating cell in the netlist A shown in FIG. 7 is specified as the logical cell 212, the cell information 401 of the logical cell 212 and the cell information 401 of FIG. The input / output wiring information 411 of the logic cell 212 is obtained from the indicated wiring information.
-With reference to 412, a logic cell which is the same logic ABC and exists in the vicinity is searched in step 132. If the result of the search indicates that the replacement candidate cell is the logic cell 232, step 13
At 3, the driving capability is compared. For the logic cells 212 and 232, the driving capability D2 is D1 based on the cell information 401 and 403.
If it is higher, the replacement cell of the logic cell 212 is determined by the logic cell 232 in step 134. In step 135, FIG.
A netlist B is created by replacing the logic cells 212 and 232 shown in FIG. The only difference between netlists A and B is the signal path including each of the replaced logic cells 212 and 232. Perform timing verification on the signal path including both logic cells replaced in step 136, step 137
Then, the presence or absence of a constraint violation is determined based on the verification result, that is, the logic cells 212 and 23 replaced with the netlist B described above.
It is determined whether the delay constraint violation has been eliminated in the signal path including each of the two and whether a new occurrence has occurred. If there is a violation of the delay constraint, the process returns to step 132, and the replacement target cell is searched again.
The steps 32 to 137 are executed again. If there is no violation of the delay constraint, the process proceeds to the replacement circuit step 109, and in the layout creation step 138 after replacement, the layout correction for switching the input and output of both the logic cells 212 and 232 is performed only by the wiring correction based on the wiring information 112. Then, the presence or absence of a delay constraint violation is determined again in the constraint violation determination step 105 for the entire logic circuit. If it is determined in each of the above steps that there is no violation of the delay constraint in the entire logic circuit, the layout correction result in step 109 becomes the final data, and the delay optimization is completed.

(Embodiment 2) FIG. 2 shows that when the delay constraint violation cannot be eliminated by the algorithm of the delay optimizing method shown in FIG. 1, the logic function level is replaced based on logical function level information obtained by further expanding each cell function. This is an algorithm for performing delay optimization.

In FIG. 2, reference numerals 101 to 112 have the same contents as in FIG. 1, that is, the first embodiment. In addition to the algorithm of FIG. 1, the algorithm of FIG. 2 determines in a decision step 121 whether the delay constraint violation cell is the same as the previous analysis result, that is, whether the delay constraint violation has been solved by the algorithm of the first embodiment. , If the late constraint violation has not been resolved,
Based on the logic function level information 123 of each logic cell, the arranged logic cells are expanded to the logic function level, and the logic cells existing near the first logic function level causing the delay constraint violation and having the same logic It is characterized by having a replacement logic level search step 122 for searching for a second logic function level that is functional and has a high driving capability. First and second
In the replacement circuit confirmation step 108, it is confirmed that the delay constraint violation does not occur in both paths even when the input and output of both logic function levels are switched, and both logic function level inputs and outputs are connected in the replacement circuit correction step 109. The changed layout is corrected, and the presence or absence of the delay constraint violation is determined again in the constraint violation determination step 105 for the entire logic circuit. The above steps will be specifically described with reference to FIGS. FIG. 9 shows an example of logic level information, FIG. 10 shows details of an algorithm of a delay optimization method for a logic circuit according to the second embodiment of the present invention, FIG. 11 shows an example of a netlist C (logic level replacement source netlist), FIG. 12 shows the netlist D.
An example of (a netlist after logic level replacement) is shown. FIG.
In 1, the logic level information 123 includes information such as logic functions, drive capabilities, and delay coefficients of all logic function levels including the logic cells 311 to 333. In the replacement logic level search step 122 of FIG. 10, the step 142 of searching for a replacement candidate logic level of the delay constraint violation logic level 312 in the netlist C shown in FIG. 11 is performed by the logic function level information 421 of the logic level 312 shown in FIG. , And searches for a replacement candidate logical level 332 which is of the same logical function a and exists in the vicinity. In step 143, the logic level 31
A comparison of the driving ability of 2.332 is performed. Logic level 312
If the drive capability d3 is higher than d1 from the logical level information 421 and 423 with respect to 332, the logical level to be replaced with the logical level 312 is determined by the logical level 332 in step 144. In step 145, the logic level 312 shown in FIG.
Create a netlist D with 332 replaced. The difference between netlists C and D is the replaced logic level 3.
There is only a signal path that includes each of 12 and 332. Step 1
In step 147, the presence or absence of a constraint violation is determined based on the verification result, that is, a signal including each of the logic levels 312 and 332 replaced with the netlist D described above. It is determined whether the violation of the delay constraint has been eliminated in the route and whether a new occurrence has occurred. Step 142 if the delay constraint is violated
To search for the replacement target logical level again,
Step 47 is executed again. If there is no violation of the delay constraint,
Proceeding to the replacement circuit step 109, in the layout creation step 138 after replacement, the layout correction for switching the input and output of both the logic levels 312 and 332 is made to the wiring information 112.
Is performed based on only the wiring correction, and the presence or absence of a delay constraint violation is determined again in the constraint violation determination step 105 for the entire logic circuit. If it is determined in each of the above steps that there is no violation of the delay constraint in the entire logic circuit, the layout correction result in step 109 becomes the final data, and the delay optimization is completed.

[0011]

As described above, the delay verification method of the present invention improves the delay constraint violation in a short period of time without increasing the layout area by modifying only the wiring layer without changing the mask layout as much as possible. I do.

[Brief description of the drawings]

FIG. 1 is a diagram showing an algorithm of a logic circuit delay optimization method according to the present invention;

FIG. 2 is a diagram showing an algorithm of a logic circuit delay optimization method according to a second embodiment of the present invention;

FIG. 3 is a diagram showing a general algorithm for explaining a delay optimization method of a logic circuit;

FIG. 4 is a diagram showing an example of arrangement cell information.

FIG. 5 is a diagram illustrating an example of wiring information;

FIG. 6 is a diagram showing details of an algorithm of a delay optimization method for a logic circuit according to the present invention;

FIG. 7 is a circuit diagram showing a specific example of a netlist A (logical cell replacement source netlist).

FIG. 8 is a circuit diagram showing a specific example of a netlist B (a netlist after logic cell replacement).

FIG. 9 is a diagram showing an example of logical level information.

FIG. 10 is a diagram showing details of an algorithm of a delay optimization method for a logic circuit according to the second embodiment of the present invention;

FIG. 11 is a circuit diagram showing a specific example of a netlist C (a logic level replacement source netlist).

FIG. 12 is a circuit diagram showing a specific example of a netlist D (netlist after logical level replacement).

[Explanation of symbols]

101 Initial Synthesis Step 102 Initial Layout Step 103 Optimization Step 104 Re-Layout Step 105 Constraint Violation Determination Step 106 Violation Factor Analysis Step 107 Replacement Cell Search Step 108 Replacement Circuit Confirmation Step 109 Replacement Circuit Correction Step 111 Placement Cell Information 112 Wiring Information 121 Delay Step 122 of determining whether the constraint violation cell is the same as the previous analysis result 122 Searching for a replaceable logic level 123 Logic function level information originally possessed by each cell 131 Violation cell identification step 132 Replacement candidate cell search step 133 Driving capability Comparison step 134 replacement target cell determination step 135 netlist creation step after replacement 136 timing verification step 137 constraint violation determination step 138 layout creation step after replacement 142 replacement candidate logical level search step 143 drive capability comparison step 144 Replacement target logic level determination step 145 Replacement net list creation step 146 Timing verification step 147 Constraint violation determination step 211-233 Logic cell 401-403 Placement cell information 411-414 Wiring information 421-423 Logic level information

Claims (2)

[Claims] In a method for optimizing a delay of a logic circuit formed by arranging a plurality of cells including a logic function and interconnecting the cells, a delay value between signal paths in which delay constraints are set in advance is obtained. A constraint violation determining step of confirming the presence or absence of a constraint violation, a violation factor analyzing step of identifying a signal path in which the constraint violation has occurred based on the constraint violation determination, and a first constraint included in the signal path in which the constraint violation has occurred. A step of searching for a second cell which is close to the cell, has the same logic, and has a higher driving capability as a replacement cell on another signal path on the layout based on the arrangement cell information and the wiring information; The input / output of the second cell is replaced with the input / output of the second cell.
A delay of a logic circuit, comprising: a step of confirming that a delay constraint violation does not occur in both signal paths; and a replacement circuit correction step of switching input / output of a first cell and a second cell. Optimization method. 2. A delay optimization method for a logic circuit in which a plurality of cells including a logic function are arranged and the cells are wired with each other, the constraint violation cannot be eliminated by a repair layout created in a replacement circuit repair step. If it is determined, the first function is determined based on the logic level information obtained by further developing the cell function.
Expanding the cells to the first logic level, searching for a second logic level that is replaceable and has a high driving capability near the first logic level, and inputting / outputting the first logic level to the second logic level. A step of confirming that a delay constraint violation does not occur in both signal paths in a replacement circuit reconnected with the input / output of the logic level of the above, and a replacement circuit modification for reconnecting the input / output of the first cell and the second cell And a method for optimizing a delay of a logic circuit.