JP2001296327A - Method and apparatus for measurement of withstand current - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method and an apparatus, for the measurement of the pulse withstand current of a diode, wherein a pulse current application system which is simple and which can change a condition is used. SOLUTION: In an IC package, a P-N junction diode 7 which is formed intentionally in parallel with a MOS transistor 5, for output, in an IC package body 3 or a P-N junction diode 7 which is parasitic inside the IC package body 3 is contained, a forward voltage is applied to the P-N junction diode 7 on the basis of a change in a reference potential due to the control of the MOS transistor 3 for output, a parasitic transistor Q which is parasitic at the IC package body 3 is turned on forcibly, and a pulse current Iout is generated. While the MOS transistor 5 for output is kept fixed in an ON state, a pulse current Iin is applied to the P-N junction diode 7, and the parasitic transistor Q is turned on forcibly. While the ON state is maintained forcibly, a constant current It for withstand voltage test is applied to the parasitic transistor Q by changing its current value, and the limit current of the parasitic transistor Q is measured.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a display driver IC.
The present invention relates to a withstand current measuring method and an apparatus for performing a withstand current test.

[0002]

2. Description of the Related Art As an IC, a display driver IC for driving a color plasma display panel has been developed, and an example of the measurement is shown in FIG.

As shown in FIG. 3, a driver IC used for a display device of a color plasma display has a PN junction diode 7 intentionally formed in parallel with an output NchMOS transistor 5 of the IC body 3 or an IC body 3 PN junction diode 6 (corresponding between the base and emitter of a parasitic NPN bipolar transistor) and also intentionally formed in PchMOS transistor 4 or PN junction diode 6 parasitic in the IC body.
(Corresponding to a region between the base and the emitter of the parasitic PNP bipolar transistor). 1 is I
A low voltage source for applying a low voltage (for example, 5 V) to a power supply terminal of a logic circuit section 3a of the C body 3 is a power supply of a high withstand voltage output circuit section of the IC body 3 for displaying a color plasma display. This is a high voltage source that applies a high voltage (for example, 90 V) to the terminal.

A color plasma display panel (color P) is provided on the output side of the logic circuit section 3a of the IC body 3.
DP) for driving NchMO with high breakdown voltage CMOS configuration
The S transistor 5 and the PchMOS transistor 4 are connected, and 0 V and a high voltage necessary for emitting (discharging) the color PDP on the anode side of the PN junction diode 7 with respect to the connection point between the NchMOS transistor 5 and the PchMOS transistor 4. For example, by supplying a pulse voltage of 180 V) alternately from the VSS2 terminal, the output N
While the chMOS transistor 5 is kept on,
A voltage is applied to the N-junction diode 7 in the forward direction to flow a current, and a driving voltage is applied to the color PDP itself from the output terminals O1, O2,... To maintain the display state.

In this state, the logic circuit section 3 of the IC body 3
When an external image display signal is input to a, pixel data to be displayed on the output terminals O1, O2,... On are selectively output from the logic circuit section 3a, and the discharge state of the PDP is maintained by these drive voltages. To display an image (maintain a light emitting state).

[0006] Incidentally, this type of IC package is an I package.
When a current exceeding a limit value is applied to a PN junction diode intentionally formed in parallel with the output NchMOS transistor of the C body or a PN junction diode parasitic in the IC body, a thyristor ( The parasitic bipolar transistors Tr2 and Tr3) are turned on, causing a phenomenon in which an excessive power supply current flows from the VDD2 power supply terminal toward the VSS2 terminal (GND terminal), a so-called latch-up phenomenon. I
The C body itself will be destroyed. This cause will be described with reference to FIG.

FIG. 4 shows a high breakdown voltage output MO of the color plasma display panel driving IC shown in FIG.
4 shows an outline of a cross-sectional structure of an S transistor portion. In FIG. 4, the same components as those in FIG. 3 are described with the same reference numerals.

In FIG. 4, the PN junction diode 7 shown in FIG. 3 is a part (corresponding to between the base and the emitter) of the NPN bipolar transistor Tr1 which is parasitic on the drain side of the output NchMOS transistor 7, and the PN junction diode 6 is , A part of the PNP bipolar transistor Tr4 parasitic on the drain side of the output Pch MOS transistor 6 (corresponding between the base and the emitter), while the output Nch
A parasitic NPN bipolar transistor Tr3 exists on the source terminal (VSS2 terminal) side of the MOS transistor 7, and a parasitic PNP bipolar transistor Tr2 exists on the source terminal (VDD2 terminal) side of the output PchMOS transistor 6, and these parasitic bipolar transistors are present. Tr2 and Tr
3 form a parasitic PNPN thyristor. These parasitic bipolar transistors Tr1, Tr2, T
r3 and Tr4 are all the output terminals O1 and O of the IC body 3.
2,... On PchMOS transistor 4 or NchM
It is parasitic between the OS transistors 5.

PN parasitic on NchMOS transistor 5
Passing a current through the junction diode 7 means supplying a base current to the parasitic NPN bipolar transistor Tr1 of FIG. When the base current (diode current) supplied to the parasitic NPN bipolar transistor Tr1 exceeds a certain value (for example, 300 to 400 mA), the parasitic NPN bipolar transistor Tr1 is turned on, and the collector current flows from the power supply terminal VDD2, and accordingly, the collector current flows. The base potential of the parasitic PNP bipolar transistor Tr2 rises and turns on, and then the parasitic NPN bipolar transistor Tr3 turns on.
The parasitic PNPN thyristor constituted by the transistor and Tr3 is finally turned on, causing an excessive current to flow from the power supply terminal VDD2 and causing thermal destruction of the IC body 3 or melting of the metal wiring inside the IC body 3. Presumed to lead to destruction.

The parasitic bipolar transistor Tr1,
Tr2, Tr3, and Tr4 are parasitic in the process of manufacturing the IC chip and are not based on design data. Therefore, their characteristics cannot be grasped in advance. As described above, since the parasitic bipolar transistor is actively used as described above, it is necessary to grasp the characteristics of the withstand current that can flow through the parasitic PN junction diode 6 or 7 in advance.

A conventional PN junction diode used for a display device of a color plasma display,
7 (corresponding to between the base and the emitter of the parasitic transistor) will be described with reference to FIGS.

In FIG. 3 and FIG. 4, in order to evaluate the current that can flow between the base and the emitter (diode 7) of the parasitic NPN bipolar transistor Tr1 on the side of the NchMOS transistor 5, the normal curve tracer 11 is used to evaluate the current.
Each of or all of the output terminals O1, O2,... On of the C body 3 are bundled, and the parasitic NP
A forward voltage is applied between the base and the emitter of the N bipolar transistor Tr1, and a current is applied to cause a latch-up phenomenon.
The limit current value between the emitters (latch-up trigger current value) is measured.

[0013]

However, in the conventional measuring method using the curve tracer 11, the parasitic NPN
The voltage applied between the base and the emitter of the bipolar transistor Tr1 is a half-sine wave voltage having a constant period (50 Hz), and the conditions of the period, pulse width, and duty ratio cannot be changed at all. The measurement is performed in a state far away from the actual state incorporated in the display device of the color plasma display, and the NPN bipolar transistor or the parasitic PNP parasitic on the IC body 3 is measured.
There is a problem that it is impossible to accurately evaluate a bipolar transistor.

At the present time, there is no optimal evaluation method that can replace the evaluation method shown in FIG.

An object of the present invention is to provide a method and an apparatus for measuring a withstand current using a pulse current application method which is simple and whose conditions can be changed.

[0016]

In order to achieve the above object, a method for measuring a withstand current according to the present invention is directed to a bipolar transistor or a built-in bipolar transistor intentionally built in parallel with an output MOS transistor of an IC body. And a driving current for maintaining a lighting state of the color plasma display by passing a current between the base and the emitter of the parasitic bipolar transistor when the output MOS transistor is on. In the generated display driver IC, the output MO
A limit current value (latch-up / trigger current) at which the NPN bipolar transistor is turned on to cause a latch-up phenomenon by changing the value of current flowing between the base and the emitter of the NPN bipolar transistor when the S transistor is on. Value).

The value of the current flowing between the base and the emitter of the bipolar transistor when the output MOS transistor is on is applied to the gate terminal of the external MOS transistor for setting the measurement timing of the current resistance test. The pulse current is changed in synchronization with a change in the cycle, pulse width or duty ratio of the pulse voltage.

Further, the withstand current measuring device according to the present invention comprises an IC
Including a bipolar transistor intentionally formed in parallel with the output MOS transistor of the main body or a parasitic bipolar transistor (PN junction diode) parasitic in the IC main body, when the output MOS transistor is in the ON state, In a display driver IC for generating a drive current for maintaining a lighting state of a color plasma display by passing a current between a base and an emitter (a PN junction diode), the parasitic element is generated when the output MOS transistor is turned on. A means for measuring a limit current value (latch-up / trigger current value) that changes a current value flowing between the base and the emitter of the bipolar transistor and causes a latch-up phenomenon when the parasitic bipolar transistor is turned on. It is.

The value of the current flowing between the base and the emitter (PN junction diode) of the bipolar transistor when the output MOS transistor is on is determined by the period of the pulse voltage for setting the measurement timing of the current resistance test. , The pulse width or the duty ratio is changed in synchronization with the change.

Further, according to the present invention, there is provided a withstand current measuring device comprising an IC
A bipolar transistor intentionally built in parallel with the output MOS transistor of the main body or a bipolar transistor (PN junction diode) parasitic in the IC main body
Wherein the output MOS transistor is in an on state,
In a display driver IC for generating a drive current for maintaining a lighting state of a color plasma display by passing a current between a base and an emitter (PN junction diode) of the parasitic bipolar transistor, a base of the parasitic bipolar transistor is provided. An external constant current pulse supply unit connected between the emitter (PN junction diode) is provided, and the constant current pulse supply unit has a withstand current value between the base and the emitter (PN junction diode) of the bipolar transistor. When the output MOS transistor is turned on, the value of the current flowing between the base and the emitter (PN junction diode) of the bipolar transistor is changed when the output MOS transistor is in the ON state, so that the parasitic P inside the IC body 3 is changed.
NPN thyristor (parasitic bipolar transistor Tr2
And a transistor Tr3) to supply a limit current (latch-up trigger current) that causes a phenomenon of turning on, that is, a so-called latch-up phenomenon.

The constant current pulse supply section includes a constant current generation section that supplies the constant current for the withstand current test to a base-emitter (PN junction diode) of the bipolar transistor while changing its current value. A switching MOS externally connected in parallel between the base and emitter (PN junction diode) of the bipolar transistor and bypassing the constant current for withstand current test supplied between the base and emitter (PN junction diode) of the bipolar transistor; A transistor and the switching M
A pulsed voltage is applied to the gate terminal of the OS transistor to turn on the switching MOS transistor to secure a bypass for the constant current for the withstand current test, and to provide a base-emitter (PN junction diode) of the bipolar transistor. And a pulse generator for controlling the supply of the constant current for withstand current test to the bipolar transistor (PN junction diode) to set the measurement timing of the withstand current test for the bipolar transistor (PN junction diode).

When the output MOS transistor is on, the value of the current flowing between the base and the emitter of the bipolar transistor (PN junction diode) depends on the period of the pulse voltage applied to the gate terminal of the switching MOS transistor. , The pulse width or the duty ratio is changed in synchronization with the change.

[0023]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a circuit diagram showing an apparatus for implementing the withstand current measuring method according to the present invention.

As shown in FIG. 1, the withstand current measuring method according to the present invention uses the base-emitter of the NPN bipolar transistor Tr1 which is in parallel with the output NchMOS transistor 5 of the IC body 3 as shown in FIGS. Between (PN
When the output NchMOS transistor 5 is turned on, a forward current flows between the base and the emitter (parasitic PN junction diode 7) of the parasitic NPN bipolar transistor Tr1 to generate a color plasma. In a display driver IC that generates a drive current for maintaining the display state of the display from output terminals O1, O2,... On of the IC body 3, the output NchMO
When the S-transistor 5 is on, the base-emitter (parasitic P
By changing the forward current value flowing through the N-junction diode 7), the PNPN thyristor (consisting of the parasitic bipolar transistors Tr2 and Tr3) parasitic on the inside of the IC body 3 is turned on to prevent the latch-up phenomenon. The limit current value (latch-up trigger current value) to be caused is measured.

The parasitic PN junction diode 7 shown in FIG. 3 is a junction diode between the base and the emitter of the parasitic NPN bipolar transistor Tr1. That is, as described above, applying a current to the PN junction diode 7 that is parasitic on the output NchMOS transistor 5 is equivalent to FIG.
Of the parasitic NPN bipolar transistor Tr1
Since this means that a current flows between the emitters, the circuit is shown as a parasitic PN junction diode 7 in the circuit configuration of FIG. 1 for convenience, and in the schematic diagram of the cross-sectional structure of the high breakdown voltage CMOS output transistor of FIG. T
Indicated as r1. A parasitic PN junction diode 6 is also parasitic with respect to the output MOS transistor 4, and the PN junction diode 6 has a parasitic PNP as shown in FIG.
This is a junction diode between the base and the emitter of the bipolar transistor Tr4, and is similarly described.

The output Nch MOS transistor 5
In the ON state, the base-emitter of the parasitic NPN bipolar transistor Tr1 (PN junction diode 7)
The value of the forward current supplied to the external MOS transistor 8 for setting the measurement timing of the withstand current test is
In synchronization with a change in the period, pulse width, or duty ratio of the pulse voltage applied to the gate terminal of.

The diode current withstanding current measuring apparatus according to the present invention is provided with an output NchMOS transistor 5 of the IC body 3.
NPN bipolar transistor Tr1 parasitic in parallel to
When the output NchMOS transistor 5 is turned on, a forward current flows between the base and emitter (PN junction diode 7) of the parasitic NPN bipolar transistor Tr1. Output terminals O1, O2 of the IC body 3
In a display driver IC that generates a drive current for maintaining the display state of the color plasma display from 2, On, between the base and emitter of the parasitic NPN bipolar transistor Tr1 when the output MOS transistor is on. The value of the forward current flowing through the PN junction diode 7) is changed to turn on the parasitic NPN bipolar transistor Tr1, and a PNPN thyristor (parasitic bipolar transistors Tr2 and Tr3) parasitic inside the C body 3 is formed. ) Is turned on, that is, a limit current value (latch-up trigger current value) which causes a so-called latch-up phenomenon is measured.

The output Nch MOS transistor 5
In the ON state, the base-emitter of the parasitic NPN bipolar transistor Tr1 (PN junction diode 7)
The value of the forward current supplied to the external MOS transistor 8 for setting the measurement timing of the withstand current test is
In synchronization with a change in the period, pulse width, or duty ratio of the pulse voltage applied to the gate terminal of.

Specifically, the device for measuring the withstand current of a diode according to the present invention comprises a base-emitter (NPN) bipolar transistor Tr1 which is in parallel with the output NchMOS transistor 5 of the IC body 3 shown in FIGS. PN
When the output NchMOS transistor 5 is turned on, a forward current flows between the base and the emitter (PN junction diode 7) of the parasitic NPN bipolar transistor Tr1 and the IC body 3
From the output terminals O1, O2,.
In a display driver IC for generating a driving current for maintaining a display state of a display, a base-emitter (PN) of the parasitic NPN bipolar transistor Tr1 is provided.
An external constant current pulse supply unit 11 connected to the junction diode 7);
When measuring the withstand current value between the base and emitter (PN junction diode 7) of the parasitic NPN bipolar transistor Tr1, the output NchMOS transistor 5
In the ON state, the base-emitter of the parasitic NPN bipolar transistor Tr1 (PN junction diode 7)
Limit current (latch-up) which causes a phenomenon in which the parasitic PNPN thyristor (consisting of Tr2 and Tr3) inside the IC body 3 is turned on by changing the forward current value applied to the・ Trigger current).

Specifically, the constant current pulse supply section 11 changes the current value of the constant current for the withstand current test to change the current value between the base and emitter of the parasitic NPN bipolar transistor Tr1 (parasitic PN junction diode 7). The parasitic NPN is externally connected in parallel between a constant current generator 10 that supplies the parasitic NPN and a base-emitter (parasitic PN junction diode 7) of the parasitic NPN bipolar transistor Tr1.
A switching MOS transistor 8 for bypassing the constant current for the withstand current test supplied between the base and the emitter (parasitic PN junction diode 7) of the bipolar transistor Tr1, and a pulse-like voltage is applied to the gate terminal of the switching MOS transistor 8. The switching MOS transistor 8 is turned on to secure a bypass for the constant current for the withstand current test, and the withstand current to the base-emitter (parasitic PN junction diode 7) of the parasitic NPN bipolar transistor Tr1 is applied. A pulse generator 9 for controlling the supply of a test constant current and setting a measurement timing of a withstand current test between the base and the emitter (parasitic PN junction diode 7) of the parasitic NPN bipolar transistor Tr1.

The output NchMOS transistor 5
In the ON state, the value of the forward current flowing between the base and the emitter of the parasitic NPN bipolar transistor Tr1 (parasitic PN junction diode 7) is equal to the pulsed voltage applied to the gate terminal of the switching MOS transistor 8. The change is made in synchronization with the change of the cycle, pulse width or duty ratio.

The case of the base-emitter (parasitic PN junction diode 7) of the parasitic NPN bipolar transistor Tr1 included in parallel with the output NchMOS transistor 5 of the IC body 3 has been described. The same applies to a case where the emitter-to-emitter (PN junction diode 7) is intentionally made in parallel with the output NchMOS transistor 5 of the IC body 3.

Next, a description will be given of a case where a withstand current test is performed between the base and the emitter (parasitic PN junction diode 7) of the NPN bipolar transistor Tr1 which is parasitic inside the IC body 3 using the withstand current measurement method according to the present invention. 1 and FIG.

As shown in FIGS. 1 and 4, the IC to be evaluated, which is a device to be measured, is a base / emitter of an NPN bipolar transistor Tr1 intentionally formed in parallel with the output NchMOS transistor 5 of the IC body 3. Between (PN
Junction diode 7) or NP parasitic in IC body 3
Including the base-emitter (parasitic PN junction diode 7) of the N bipolar transistor Tr1, the output Nch
When the MOS transistor 5 is turned on, a forward current flows between the base and the emitter (PN junction diode 7) of the NPN bipolar transistor Tr1, and the IC
The output terminals O1, O2,... On of the main body 3 are used as display driver ICs for generating a drive current for maintaining the display state of the color plasma display. Since the image display in this case has been described in the section of the related art, the description will be omitted.

In the present invention, the output NchMOS
When the transistor 5 is turned on, the forward current flowing between the base and the emitter (PN junction diode 7) of the NPN bipolar transistor Tr1 is changed to change the forward current between the base and the emitter (PN junction diode) of the NPN bipolar transistor Tr1. The limit current value (latch-up trigger current value) of 7) is measured.

Specifically, the constant current Iin is generated from the constant current pulse supply unit 11 to supply a predetermined current to the parasitic bipolar transistor Tr1 until the latch-up phenomenon occurs.

The constant current generated from the constant current pulse supply unit 11 is shown in FIG. 2 by turning on / off a switching MOS transistor 8 connected in parallel between the base and the emitter (PN junction diode 7) of the NPN bipolar transistor Tr1. A pulse-shaped current Iin is formed and the N
A current is applied between the base and the emitter of the PN bipolar transistor Tr1 (PN junction diode 7) in the forward direction to secure the voltage between the emitter and the base (PN junction diode 7) of the NPN bipolar transistor Tr1.

When the gate voltage VG shown in FIG. 2 is at the H level, the switching MOS transistor 8 is turned on, and the constant current Iin for the withstand current test supplied from the constant current generator 10 passes through the switching MOS transistor 8. Since the bipolar transistor T is bypassed,
Although no current flows between the base and the emitter of r1 (PN junction diode 7), when the gate voltage VG shown in FIG. 2 is at the L level, the switching transistor 8 is turned off. Since a constant current Iin for a current test is conducted between the base and the emitter of the bipolar transistor Tr1 (PN junction diode 7), a current flows between the base and the emitter of the bipolar transistor Tr1 to allow the current to flow inside the IC body 3. Of the PNPN thyristor (consisting of the parasitic bipolar transistors Tr2 and Tr3), which is a parasitic current, is turned on, and a limit current value (latch-up trigger current) causing a so-called latch-up phenomenon is measured.

In this case, an external switching MOS
By adjusting the low-level pulse width and period of the gate voltage VG waveform applied to the gate of the transistor 8, a pulse current Iin having a predetermined pulse width and period is applied between the base and the emitter of the bipolar transistor Tr1 as shown in FIG. A current is applied to the (PN junction diode 7) in the forward direction to turn on the bipolar transistor Tr1 and cause a state in which a collector current flows.

In this manner, a limit current value (latch-up / threshold value) that causes a so-called latch-up phenomenon that turns on a PNPN thyristor (consisting of parasitic bipolar transistors Tr2 and Tr3) which is parasitic inside the IC body 3 is brought into an ON state. If the trigger current value is measured, the amplitude value and the waveform condition (period and duty ratio) of the pulse current become the pulse withstand current value.

As described above, according to the present invention, the output Nch
When the MOS transistor is turned on, the current flowing between the base and the emitter (PN junction diode 7) of the NPN bipolar transistor is changed to form a PNPN thyristor (parasitic bipolar transistors Tr2 and Tr3) that is parasitic inside the IC body 3. In order to evaluate the withstand current of the display driver IC by measuring a limit current value (latch-up trigger current value) that causes a so-called latch-up phenomenon, the circuit configuration can be simplified. Measurement can be performed easily.

Further, a pulse current can be easily generated in synchronization with a change in an arbitrary period, pulse width, and duty ratio. Therefore, measurement can be performed under environmental conditions close to actual driving conditions of a color plasma display panel. This makes it possible to accurately measure the withstand pulse current of the display driver IC body.

Next, the present invention will be described in detail with reference to specific examples.

The display driver IC shown in FIG. 1 has a low voltage power supply voltage VDD1 (= 5 V)
Then, a high power supply voltage VDD2 (= 90 V) is supplied.

The display driver IC as the device to be measured shown in FIG. 1 includes a base-emitter (PN junction) of the NPN bipolar transistor Tr1 intentionally formed in parallel with the output NchMOS transistor 5 of the IC body 3. Diode 7) or the N parasitic in the IC body 3
A forward current is applied between the base and the emitter of the PN bipolar transistor Tr1 (parasitic PN junction diode 7), and the display state of the color plasma display is maintained from the output terminals O1, O2,. Driver IC for generating a driving current for the display.

The withstand voltage measuring device according to one embodiment of the present invention shown in FIG.
1 has an external constant current pulse supply unit 11 connected between the base and the emitter (PN junction diode 7).
The constant current pulse supply unit 11 is configured to supply a current between the base and the emitter (PN junction diode 7) of the bipolar transistor Tr1 in the forward direction.

Specifically, the constant current pulse supply unit 11
Changes the current value of the constant current for the withstand current test to change the base current of the NPN bipolar transistor Tr1.
A constant current generator 10 that supplies between the emitter (PN junction diode 7) and an externally connected in parallel between the base and emitter (PN junction diode 7) of the bipolar transistor Tr1 and connects between the base and emitter of the bipolar transistor Tr1. A switching MOS transistor 8 for bypassing the constant current for withstand current test supplied to (PN junction diode 7);
A pulsed voltage is applied to the gate terminal VG of the transistor 8 to turn on the switching MOS transistor 8 to secure a bypass for the constant current for the withstand current test, and to connect the base-emitter (PN) of the bipolar transistor Tr1. A pulse generator 9 for controlling the supply of the constant current for the withstand current test to the junction diode 7) and setting the measurement timing of the withstand current test between the base and the emitter of the bipolar transistor Tr1 (PN junction diode 7). Including.

An NchMOS field effect transistor (FET) is used as the switching MOS transistor 8, and the NchMOS transistor 8 is inserted in parallel with a constant current generator (DC current source) 10 for supplying a constant current. The drain terminal D of the NchMOS transistor 8 is connected to the + terminal side of the constant current generator 10, and the source terminal S of the NchMOS transistor 8 is connected to the − terminal side of the constant current generator 10.

Source terminal S of NchMOS transistor 8
And a gate terminal VG, a pulse voltage unit 9 is connected, and Nc
A predetermined pulse current (amplitude,
The pulse current waveform (see FIG. 2) of the pulse voltage unit 9 is adjusted so as to generate the cycle and pulse width Iout.

Further, the n output terminals O1,
O2,... On are all fixed to a low level state (0 V), and all the output terminals O1, O2,.
The NchMOS transistor 8 is connected in parallel so that a pulse current can be supplied.

Output terminals O1, O2,... On of the IC body 3
And the base of the NPN bipolar transistor Tr1.
A pulse current Iin is supplied from the NchMOS transistor 8 between the emitters (PN junction diodes 7) to turn on the parasitic PNPN thyristor (consisting of the parasitic bipolar transistors Tr2 and Tr3) which is parasitic on the IC body 3, so-called so-called. A limit value (latch-up trigger current value) of a pulse current until a latch-up phenomenon is caused is measured.

In the present invention, while the output MOS transistor 5 is fixed in the ON state, the base-emitter (P) of the NPN bipolar transistor Tr1 is maintained.
A pulse current Iin is supplied to the N-junction diode 7). That is, in the IC body 3, the bundled output terminals O1, O
NchMOS transistor 8 inserted in parallel with 2,.
A pulse-like gate voltage as shown in FIG. 2 is applied to the gate terminal VG of FIG.
The current flows between the base and the emitter (PN junction diode 7) of the bipolar transistor Tr1.

In this case, the output terminals O1, O2,... On of the IC body 3, which are the devices to be measured, are fixed to a low level (0 V) in advance, that is, the output NchMOS transistor 5 is fixed to the on state.

When the voltage (see FIG. 2) applied to the gate terminal VG of the external NchMOS transistor 8 goes low, the NchMOS transistor 8 is turned off, and the current of the constant current generator 10 is the element to be measured. IC body 3
Of the NPN bipolar transistor Tr1
Electric current is applied between the emitters (PN junction diode 7) in the forward direction.

On the other hand, an external NchMOS transistor 8
When the voltage to the gate terminal VG (see FIG. 2) attains a high level, the NchMOS transistor 8 is turned on, and the current of the constant current generator 10 bypasses the NchMOS transistor 8 and flows through the NPN bipolar transistor. No current is conducted between the base and the emitter of the Tr1 (PN junction diode 7).

At this time, by adjusting the low-level pulse width and period of the waveform of the voltage (see FIG. 2) applied to the gate terminal VG of the external NchMOS transistor 8,
As shown in FIG. 2, a pulse current Iin having a predetermined pulse width and a predetermined period is supplied to the NPN of the IC body 3 as an element to be measured.
A current is applied in the forward direction between the base and the emitter (PN junction diode 7) of the bipolar transistor Tr1.

As described above, in the IC body 3 as the device to be measured, the pulse current until the latch-up phenomenon occurs is changed to the NPN bipolar transistor Tr1.
When the current flows between the base and the emitter (PN junction diode 7), the pulse current value and the waveform condition (period and pulse width) become the measured values of the pulse withstand current.

FIG. 2 shows a case where the pulse cycle is 4 to 12 μs, the pulse width is 250 to 350 ns, and the pulse current (total current) is 2.5 to 4.0 A.

As described above, according to the embodiment of the present invention,
A switching NchMOS transistor 8 for current bypass is inserted in parallel with the constant current generator 10 to generate a constant current pulse, and intentionally between the base and emitter (PN junction diode 7) of the built-in or parasitic bipolar transistor Tr1. Since the measurement is performed by applying current, the circuit configuration can be simplified, and the measurement itself can be easily performed.

Further, an external NchMOS for switching
As shown in FIG. 2, a pulse-like gate voltage waveform having an arbitrary period, pulse width, and duty ratio can be input to the gate terminal of the transistor 8, so that the gate terminal has the same period as the gate voltage waveform. It is possible to easily generate a constant current pulse having a pulse width and a duty ratio which are inverted with respect to the gate voltage waveform, perform measurement under conditions close to actual driving conditions, and perform PN measurement until a latch-up phenomenon occurs. The withstand current (latch-up trigger current) of the junction diode can be measured accurately.

Although the present invention has been described with reference to a color plasma display panel driving IC, the present invention is not limited to this.
Evaluation of withstand current of regenerative current that can flow in SIC and IC composed of CMOS transistors such as logic IC
Also, the present invention can be applied to the evaluation of latch-up withstand current by a constant current pulse application method in LSI.

[0063]

According to the present invention, as described above,
Further, it is possible to provide a method and an apparatus for measuring a withstand current of a diode using a pulse current application method capable of changing conditions.

[Brief description of the drawings]

FIG. 1 is a circuit configuration diagram showing an apparatus for implementing a withstand current measuring method according to the present invention.

FIG. 2 is a characteristic diagram showing a relationship between a gate voltage and a pulse current in a constant current pulse supply unit used in the withstand current measuring device according to the present invention.

FIG. 3 is a circuit configuration diagram showing an apparatus for performing a withstand current measuring method according to a conventional example.

FIG. 4 is a cross-sectional view showing a schematic structure of an output high-withstand-voltage CMOS transistor section in a display driver IC chip.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Low voltage source (logic circuit part) 2 High voltage source (high withstand voltage output circuit part) 3 Display driver IC main body 4 PchMOS transistor (output MOS transistor) 5 NchMOS transistor (output MOS transistor) 6,7 PN junction diode Tr1 , Tr2, Tr3 Parasitic bipolar transistor 8 NchMOS transistor 9 Pulse voltage section 10 Constant current generation section 11 Constant current pulse supply section

Claims (7)

[Claims] A bipolar transistor intentionally formed in parallel with an output MOS transistor of an IC body or a bipolar transistor (P) parasitic in the IC body.
N-junction diode), and when the output MOS transistor is on, a current flows between the base and emitter (junction diode) of the bipolar transistor;
In a display driver IC for generating a drive current for maintaining a lighting state of a color plasma display, a current value applied to the bipolar transistor (PN junction diode) is changed when the output MOS transistor is on, A method for measuring a withstand current, comprising measuring a limit current value (latch-up trigger current value) at which the bipolar transistor is turned on to cause a latch-up phenomenon. 2. A value of a current flowing through the bipolar transistor (PN junction diode) when the output MOS transistor is in an on state is set to a gate terminal of an external MOS transistor for setting a measurement timing of the withstand current test. 2. The withstand current measuring method according to claim 1, wherein the pulse current is changed in synchronization with a change in a period, a pulse width, or a duty ratio of the applied pulse voltage. 3. A bipolar transistor intentionally formed in parallel with an output MOS transistor of an IC body or a bipolar transistor (P
An N-junction diode) for supplying a current between the base and the emitter (PN junction diode) of the bipolar transistor when the output MOS transistor is in an on state, to maintain a lighting state of the color plasma display. In an IC for generating a drive current, a value of a current flowing between a base and an emitter of the bipolar transistor is changed when the output MOS transistor is in an on state, and a PNPN thyristor parasitic in the IC is turned on and latched. A withstand current measuring device having means for measuring a limit current value (latch-up / trigger current value) causing an up phenomenon. 4. A value of a current flowing through the bipolar transistor when the output MOS transistor is on is:
4. A pulse voltage applied to a gate terminal of an external MOS transistor for setting a measurement timing of the withstand current test is changed in synchronization with a change in a period, a pulse width, or a duty ratio of a pulse voltage. Current withstanding device. 5. A bipolar transistor intentionally formed in parallel with an output MOS transistor of an IC body or a bipolar transistor (P) parasitic in the IC body.
An N-junction diode) for supplying a current between the base and the emitter (PN junction diode) of the bipolar transistor when the output MOS transistor is in an on state, to maintain a lighting state of the color plasma display. In a display driver IC that generates a drive current, a base-emitter (P
An external constant current pulse supply unit connected to the N-junction diode). The constant current pulse supply unit measures the withstand current value between the base and the emitter (PN junction diode) of the bipolar transistor. Then, when the output MOS transistor is on, the value of the current flowing between the base and the emitter of the bipolar transistor (PN junction diode) is changed, and the PNPN thyristor parasitic inside the IC body is turned on. A withstand current measuring device for supplying a limit current (latch-up trigger current) causing a latch-up phenomenon. 6. The constant current pulse supply section changes a constant value of the constant current for the withstand current test to change a current value between a base and an emitter (PN) of the bipolar transistor.
A constant current generator for supplying a junction diode) and a base-emitter (P
A switching MOS transistor that is externally connected in parallel with the N-junction diode and bypasses the constant current for the withstand current test supplied between the base and the emitter of the bipolar transistor (PN junction diode); A pulse-like voltage is applied to the gate terminal to turn on the switching MOS transistor, secure a bypass for the constant current for the withstand current test, and connect the base and the base of the bipolar transistor.
And a pulse generator for controlling the supply of the constant current for the withstand current test between the emitters (PN junction diode) and setting the measurement timing of the withstand current test of the bipolar transistor (PN junction diode). The withstand current measuring device according to claim 5, wherein 7. A value of a current flowing through the bipolar transistor (PN junction diode) when the output MOS transistor is in an ON state is determined by a period and a pulse width of a pulse voltage applied to a gate terminal of the switching MOS transistor. 8. The withstand current measuring device according to claim 5, wherein the change is performed in synchronization with a change in the duty ratio. 9.