JP2001292185A - Encoder, encoding method, recording medium with encoding program recorded thereon, and decoder, decoding method, recording medium with decoding program recorded thereon - Google Patents

Abstract

PROBLEM TO BE SOLVED: To efficiently performing error correcting encoding and decoding by a vertical-column concatenate encoding modulation. SOLUTION: An encoder 1 is provided with two folding encoders 10 and 30 for performing folding arithmetic, an interleaver 20, for replacing the order of inputted data and a multi level demodulation mapping circuit 40 for performing mapping of a signal pint, based on a prescribed modulation system. This encoder 1 performs vertical-column concatenate folding arithmetic where an encoding ratio is '2/3' to inputted 2-bit input data D1 to convert it to 3-bit coded data D4 and maps it to be the transmission symbol of a 8 PSK(8-Phase Shift Keying) modulation system to output it is one encoding transmission symbol D5 of three-bits.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an encoding apparatus for performing cascaded coded modulation on input data, a recording medium on which an encoding method and an encoding program are recorded, and cascaded coded modulation. The present invention relates to a decoding device that decodes decoded data, a decoding method, and a recording medium that stores a decoding program.

[0002]

2. Description of the Related Art In recent years, for example, communication fields such as mobile communication and deep space communication, broadcasting fields such as terrestrial or satellite digital broadcasting, and magnetic, optical or magneto-optical recording fields for recording and / or reproducing data on and from recording media. Although research has been remarkably advanced, coding theory has been actively studied for the purpose of improving the efficiency of error correction coding and decoding.

As a theoretical limit of code performance, a Shannon limit given by the so-called Shannon channel coding theorem is known. Shannon's channel coding theorem states that “when information is transmitted at a transmission rate R (bits / symbol) using a channel with a channel capacity C (bits / symbol), if R ≦ C, There is an encoding method that can make the error probability as close to "0" as possible. "
The Shannon limit is the theoretical limit of the transmission rate at which transmission is possible without error.

As an encoding method showing performance close to the Shannon limit, for example, “S. Benedetto, G. Montorsi,
D. Divsalar, F. Pollara, “Serial Concatenation of
Interleaved Codes: Performance Analysis, Design,
and Iterative Decoding ”, TDA Progress Report 42-1
26, Jet Propulsion Laboratory, Pasadena, Californi
a, Aug. 15, 1996 ", Serially Concatenated Convolutional Codes
Is known.

[0005] Coding by the cascade convolutional code is performed by a device configured by connecting two convolutional encoders and an interleaver in cascade. The decoding of the cascade convolutional code is performed by soft-output.
Is performed by a device configured by connecting two decoding circuits that output the data in a cascade, information is exchanged between the two decoding circuits, and a final decoding result is obtained.

Further, as an application of the encoding using the tandem concatenated convolutional code, for example, “D. Divsalar, F. Pollar
a, “Serial and Hybrid Concatenation Codes with Ap
replications ”, in Proc., Int. Symp. on Turbo Codes
and Related Topics, Brest, France, pp. 80-87, Sept.
1997, the tandem concatenated coded modulation (Serial
Concatenated Trellis Coded Modulation;
Notated as TCM. ) Schemes are also known. This SCTCM
The method is a combination of coding using cascade convolutional codes and multi-level modulation, and takes into account the arrangement of signal points of a modulated signal and the decoding characteristics of an error correction code.

[0007] The following describes an encoding device that performs encoding according to the SCTCM method and a decoding device that decodes codes according to the SCTCM method. In the following description, as shown in FIG. 19, digital information is cascade-concatenated and convolutionally encoded by an encoding device 201 included in a transmitting device (not shown), and the output is stored in a memoryless communication channel 2 having noise.
It is assumed that the data is input to a receiving device (not shown) via the second device 02, decoded by the decoding device 203 included in the receiving device, and observed.

[0008] As an encoding apparatus 201 for performing encoding according to the SCTCM method, for example, as shown in FIG.
(Hereinafter referred to as an outer code), a convolutional encoder 210 for rearranging the order of input data, and a second code (hereinafter referred to as an inner code). A convolutional encoder 230 for encoding;
Some include a multi-level modulation mapping circuit 240 that performs signal point mapping based on a predetermined modulation scheme, and a demultiplexer 250 that demultiplexes an output from the multi-level modulation mapping circuit 240. The encoding apparatus 201 performs a concatenated concatenation operation on the input 4-bit input data D201 with an encoding rate of “4/6 = 2/3”, and converts the 4-bit input data D201 into 6-bit encoded data D204. For example, the transmission symbol is mapped to a transmission symbol of an 8-PSK (8-Phase Shift Keying) modulation method, two transmission symbols D205 of 3 bits are obtained, and output as encoded transmission symbols D206 one by one.

When the convolutional encoder 210 receives 4-bit input data D201, it receives the input data D20.
1 and performs a convolution operation on the resulting interleaver 22 as 5-bit encoded data D202.
Output to 0. That is, the convolutional encoder 210
As a coding of the outer code, a convolution operation with a coding rate of “4/5” is performed, and the coded data D202 is output to the interleaver 220 at the subsequent stage.

[0010] Interleaver 220 receives encoded data D202 composed of five bit sequences output from convolutional encoder 210 and receives encoded data D202.
Are rearranged, and the generated interleaved data D203 composed of a 5-bit sequence is output to the subsequent convolutional encoder 230.

Upon receiving the 5-bit interleaved data D203, the convolutional encoder 230 performs a convolution operation on the interleaved data D203,
The operation result is output to the subsequent multi-level modulation mapping circuit 240 as 6-bit encoded data D204. That is, the convolutional encoder 230 performs a convolution operation with a coding rate of “5/6” as the encoding of the inner code, and outputs the encoded data D204 to the multi-level modulation mapping circuit 240 at the subsequent stage.

The multi-level modulation mapping circuit 240 encodes the encoded data D204 output from the convolutional encoder 230.
Is synchronized with a clock and mapped to a transmission symbol of, for example, an 8PSK modulation method. Since the signal point of one transmission symbol in the 8PSK modulation scheme is 3-bit data, the multi-level modulation mapping circuit 240 outputs 3 bits of the 6-bit encoded data D204 output from the convolutional encoder 230. Are mapped as one transmission symbol to generate two transmission symbols D205. Multi-level modulation mapping circuit 240
Outputs the generated transmission symbol D205 to the subsequent demultiplexer 250.

The demultiplexer 250 outputs the two transmission symbols D output from the multi-level modulation mapping circuit 240.
205 is demultiplexed. Demultiplexer 25
0 is output to the outside as a coded transmission symbol D206 one transmission symbol at a time in synchronization with a clock having a half cycle of the clock when the transmission symbol D205 is generated by the multi-level modulation mapping circuit 240.

The encoding apparatus 201 performs a convolution operation with an encoding rate of "4/5" as the encoding of the outer code by the convolutional encoder 210, and the convolutional encoder 2
The coding rate is “5/6” as the coding of the inner code by 30
, A cascade concatenation operation with a coding rate of “(4/5) × (5/6) = 4/6 = 2/3” is performed as a whole. The data encoded and modulated by the encoding device 201 is output to the receiving device via the non-storage channel 202.

On the other hand, SCTCM by the encoding device 201
As shown in FIG. 21, for example, as a decoding device 203 that decodes a code of the system, a multiplexer 260 that multiplexes a received word D207 received, a soft output decoding circuit 270 that decodes an inner code, , An interleaver 290 for rearranging the order of input data, and a soft output decoding circuit 300 for decoding an outer code. The decoding device 203 takes an analog value under the influence of noise generated on the memoryless communication path 202 and takes a soft input (so
ft-input) and the encoding device 20 from the received word D207
1 to estimate the input data D201
213 is output.

The multiplexer 260 outputs two received words corresponding to one transmission symbol among the soft-input received words D207 received by the receiving apparatus to the subsequent soft-output decoding circuit 270.

[0017] The soft output decoding circuit 270
1 is provided in correspondence with the convolutional encoder 230 in the so-called BCJR (Bahl, Cocke, Jelin
MAP (Maximum) based on the ek and Raviv algorithm
A Posteriori probability decoding and SOVA (Soft Out
put Viterbi Algorithm) decoding. The soft-output decoding circuit 270 receives two soft-input received words D208 supplied from the multiplexer 260, and receives prior probability information D209 for the soft-input information bits supplied from the interleaver 290, and receives them. Using the word D208 and the prior probability information D209,
Performs soft output decoding of the inner code. And the soft output decoding circuit 2
70 generates extrinsic information D210 for the information bits determined by the code constraint condition.
0 is output to the deinterleaver 280 at the subsequent stage as a soft output. The external information D210 is stored in the encoding device 20.
1 corresponds to the interleaved data D203 interleaved by the interleaver 220 in FIG.

The deinterleaver 280 is provided for the encoding device 2
01, the bit arrangement of the interleaved data D203 interleaved by the interleaver 220 in the soft input external information D210 output from the soft output decoding circuit 270 is returned to the original bit arrangement of the encoded data D202. Interleave. The deinterleaver 280 outputs the data obtained by deinterleaving as prior probability information D211 for the code bits in the soft output decoding circuit 300 at the subsequent stage.

The interleaver 290 performs interleaving based on the same permutation position information as the interleaver 220 in the encoding device 201 with respect to the external information D212 corresponding to the soft input code bit output from the soft output decoding circuit 300. Apply. The interleaver 290 converts the data obtained by the interleaving into a soft output decoding circuit 270.
Is output as prior probability information D209 for the information bit in.

The soft-output decoding circuit 300 includes the encoding device 20
1, the MAP decoding based on the BCJR algorithm and the SOVA as in the soft output decoding circuit 270.
It performs decryption. The soft output decoding circuit 300 inputs prior probability information D211 for the soft input code bits output from the deinterleaver 280, and also inputs prior probability information for information bits whose value is “0” (not shown). , Soft output decoding of the outer code is performed using the prior probability information. Then, the soft output decoding circuit 30
0 generates the external information D212 for the code bit determined by the code constraint condition.
To the interleaver 290 as a soft output. Although not shown, the soft output decoding circuit 300 generates extrinsic information for information bits determined by a code constraint condition, and based on the extrinsic information, generates a hard output (hard-outpu).
The decoded data D213 of t) is output.

The decoding device 203 receives the received word D2
07, the decoding operation of the soft output decoding circuits 270 to 300 is repeated a predetermined number of times, for example, several to several tens of times, and the soft output obtained as a result of the decoding operation of the predetermined number of times is obtained. , And outputs the decoded data D213 based on the external information.

As described above, in the system constituted by the encoding device 201 and the decoding device 203, the SC
It becomes possible to perform encoding by the TCM method and decoding of codes by the SCTCM method.

[0023]

By the way, the system constituted by the encoding device 201 and the decoding device 203 described above can perform error correction encoding and decoding by the SCTCM system, but still has a performance problem. In fact, there was room for improvement.

The present invention has been made in view of such circumstances, and has an encoding apparatus, an encoding method, and a recording medium on which an encoding program is recorded, which can perform encoding and decoding with high performance. And a recording medium on which a decoding device, a decoding method, and a decoding program are recorded.

[0025]

A coding apparatus according to the present invention for achieving the above-mentioned object is a coding apparatus for performing cascade concatenated modulation on input data. A first encoding unit that performs encoding on the data, and an order of each bit that constitutes data composed of a bit sequence encoded by the first encoding unit is changed by one time slot from the first encoding unit. And permutation means for permuting and rearranging in units of symbols, which is a set of data supplied by the above, and second encoding means for performing encoding that does not end in one time slot on the data supplied from this substitution means. Mapping means for mapping the data encoded by the second encoding means to transmission symbols of a predetermined modulation scheme.

The encoding apparatus according to the present invention has the following features.
The replacement unit replaces and rearranges the order of each bit constituting the data consisting of the bit sequence encoded by the first encoding unit in a symbol unit, and replaces the data supplied from the substitution unit with the second data. By the encoding means of
Encoding that does not end in a time slot is performed.

According to another aspect of the present invention, there is provided an encoding method for performing cascade concatenated modulation on input data. A first encoding step of performing
The order of each bit constituting the data consisting of the bit sequence encoded in the encoding step is replaced by a symbol unit which is a set of data encoded in one time slot in the first encoding step. And a second encoding step of performing encoding that does not end in one time slot on the data rearranged in the replacing step, and encoding in the second encoding step. And a mapping step of mapping the obtained data to transmission symbols of a predetermined modulation scheme.

The encoding method according to the present invention is as follows.
In the replacement step, the order of each bit constituting the data consisting of the bit sequence encoded in the first encoding step is replaced and rearranged in symbol units, and the data rearranged in the replacement step is Then, in the second encoding step, encoding that does not end in one time slot is performed.

Further, the recording medium on which the encoding program according to the present invention for achieving the above-mentioned object is recorded has recorded thereon a computer-controllable encoding program for performing cascaded encoding modulation on input data. Recording medium, wherein the encoding program comprises: a first encoding step of encoding input data; and data comprising a bit sequence encoded in the first encoding step. A replacement step in which the order of the constituent bits is replaced and rearranged in a symbol unit, which is a set of data encoded in one time slot in the first coding step, and a rearrangement in the replacement step. A second encoding step of encoding data that does not end in one time slot, and transmitting the encoded data in the second encoding step to a transmission symbol of a predetermined modulation scheme. It is characterized in that it comprises a mapping step of mapping.

In the recording medium on which the encoding program according to the present invention is recorded, in the replacement step, the order of each bit constituting the data consisting of the bit sequence encoded in the first encoding step is determined. Are rearranged in units of symbols, and rearranged.
In the encoding step, an encoding program for performing encoding that does not end in one time slot is provided.

Furthermore, a decoding apparatus according to the present invention that achieves the above-described object has a first encoding unit that encodes input data, and a first encoding unit that encodes the input data. First replacing means for replacing and rearranging the order of each bit constituting data comprising a bit sequence, and second encoding means for performing encoding on the data supplied from the first replacing means. And a mapping device for mapping data coded by the second coding device to transmission symbols of a predetermined modulation scheme. In addition, soft output decoding is performed using external information for each symbol, which is a set of data output in one time slot from the first encoding unit.

In the decoding apparatus according to the present invention, when performing soft output decoding, the symbol which is a set of data which is encoded by the first encoding means of the encoding device and output in one time slot is used. Use external information for each.

Further, according to the decoding method of the present invention which achieves the above-mentioned object, a first encoding step of encoding input data, and an encoding process performed in the first encoding step. A first permutation step of permuting and rearranging the order of each bit constituting the data composed of the bit sequence, and a second code for encoding the data rearranged in the first permutation step Decoding for decoding a code concatenated and cascaded by a coding method including a coding step and a mapping step of mapping the data coded in the second coding step to transmission symbols of a predetermined modulation scheme. The method is characterized in that soft output decoding is performed using external information for each symbol, which is a set of data encoded in one time slot in the first encoding step.

The decoding method according to the present invention is a set of data that is encoded in the first encoding step and output in one time slot when performing soft output decoding. External information for each symbol is used.

Further, the recording medium on which the decoding program according to the present invention for achieving the above-mentioned object is recorded, comprises a first encoding step of encoding input data,
A first permutation step of permuting and rearranging the order of each bit constituting the data consisting of the bit sequence encoded in the first encoding step, and a permutation in the first permutation step; The encoding method includes a second encoding step of encoding data, and a mapping step of mapping the data encoded by the second encoding step to transmission symbols of a predetermined modulation scheme. A recording medium on which a computer-controllable decoding program for decoding a concatenated-coded modulation code is recorded, wherein the decoding program is a set of data encoded in one time slot in a first encoding step. The soft output decoding is performed using the external information for each symbol.

The recording medium on which the decoding program according to the present invention is recorded is encoded in the first encoding step of the encoding method and output in one time slot when performing soft output decoding. Provided is a decoding program that uses external information for each symbol, which is a data set.

[0037]

Embodiments of the present invention will be described below in detail with reference to the drawings.

In this embodiment, as shown in FIG. 1, digital information is encoded by an encoding device 1 provided in a transmitting device (not shown), and the output thereof is transmitted via a memoryless communication path 2 with noise to a receiving device (not shown). This is a data transmission / reception system applied to a communication model that is input to a device and is decoded by a decoding device 3 included in the receiving device.

In this data transmission / reception system, the decoding device 3 uses the coding device 1 to perform tandem concatenated coding modulation (Se
rial Concatenated Trellis Coded Modulation;
Notated as SCTCM. ) Decoding a code that has been encoded according to the external information (extr
It performs iterative decoding using insic information). The encoding device 1 performs encoding according to the SCTCM method, and performs a convolution operation with an encoding rate of “２” as encoding of a first code (hereinafter, referred to as an outer code). , And a second code (hereinafter referred to as an inner code) is a convolution operation with a coding rate of “3/3 = 1”. In particular, as will be described later, the encoding device 1 uses a code that does not end in one time slot as the inner code and a code of the outer code in order for the decoding device 3 to repeatedly perform decoding using the external information for each symbol. A set of a plurality of bits of data output from a convolutional encoder which is an elementary encoder for performing encoding is used as a symbol, and an interleaver for performing interleaving in symbol units is provided at a stage subsequent to the convolutional encoder.

As shown in FIG. 2, the encoding device 1 includes two convolutional encoders 10 and 30, which are a first encoding unit and a second encoding unit for performing a convolution operation, and input data, It includes an interleaver 20 as a (first) replacement means for rearranging the order, and a multi-level modulation mapping circuit 40 as a mapping means for mapping signal points based on a predetermined modulation scheme. The encoding device 1 performs a cascade convolution operation with an encoding rate of “2/3” on the input 2-bit input data D1 to convert it into 3-bit encoded data D4, for example, 8PSK ( 8-Phase
Shift Keying) is mapped to a transmission symbol of a modulation scheme, and is output as one encoded transmission symbol D5 of 3 bits.

As shown in FIG. 3, the convolutional encoder 10 has three shift registers 11, 12, and 13 and three exclusive OR circuits 14, 15, and 16.

The shift register 11 continues to supply the held 1-bit data to the exclusive OR circuit 15.
Then, the shift register 11 is synchronized with the clock, the input data D1 ₁ for one bit of the 2-bit input data D1 newly held, new the input data D1 ₁ to the exclusive OR circuit 15 Supply.

The shift register 12 continues to supply the held 1-bit data to the shift register 13 and the exclusive OR circuit 14. Then, the shift register 12
Is synchronized with the clock, and the 2-bit input data D1
Newly held one bit of the input data D1 ₂ of,
Newly supplies the input data D1 ₂ to the shift register 13 and an exclusive OR circuit 14.

The shift register 13 continues to supply the held 1-bit data to the exclusive OR circuits 14 and 16. Then, the shift register 13 newly holds the 1-bit data supplied from the shift register 12 in synchronization with the clock, and newly supplies this data to the exclusive OR circuits 14 and 16.

The exclusive OR circuit 14 performs the input data D1 ₁ for one bit of the two bits of the input data D1, the exclusive OR operation by using the data supplied from the shift register 12, 13 , and outputs it to the subsequent stage interleaver 20 of the operation result as encoded data D2 ₁ of 1 bit of the 3 bits of the encoded data D2.

The exclusive OR circuit 15 performs an exclusive OR operation by using 1-bit input data D12 of the _2- bit input data D1 and data supplied from the shift register 11, and results output to the subsequent stage interleaver 20 as encoded data D2 ₂ 1 bit of the 3 bits of the encoded data D2.

The exclusive OR circuit 16 performs an exclusive OR operation using the 2-bit input data D1 and the data supplied from the shift register 13, and outputs the operation result to the 3-bit encoded data D2. output to the subsequent stage interleaver 20 as 1 bit of the encoded data D2 ₃ of out.

[0048] the convolutional encoder 10 inputs the 2-bit input data D1 _1, D1 _2, convolution performs an operation on these input data D1 _1, D1 _2,
Calculation results of 3-bit coded data D2 _1, D2 _2, D2
_{As 3} is output to the interleaver 20 at the subsequent stage. That is, the convolutional encoder 10 performs a convolution operation with a coding rate of “2/3” as the encoding of the outer code, and outputs the encoded data D2 to the interleaver 20 at the subsequent stage.

The interleaver 20 sets a set of 3-bit encoded data D2 ₁ , D2 ₂ , D2 ₃ supplied from the convolutional encoder 10 in one time slot as one symbol.
The symbol is interleaved. That is, the interleaver 20, for example, as shown in FIG. 4, to hold the 3 coded data D2 ₁ bit, D2 _2, D2 ₃ combinations of sequentially input, the 3-bit coded data D2 _1, D2 ₂ and D2 ₃ are 1
The symbol is interleaved. In the following description, such interleaving is referred to as “pair wise” interleaving.

As shown in FIG. 5, such an interleaver 20 includes an input data holding memory 21 for holding input data, a data replacement circuit 22 for rearranging (replacement) the order of input data, Replacement data ROM (Read Only Memory) 2 for storing data replacement position information
3 and an output data holding memory 24 for holding data to be output.

The input data holding memory 21 receives and holds the encoded data D2 composed of three bit sequences output from the convolutional encoder 10 and holds the encoded data D2.
2 is supplied to the data replacement circuit 22 at a predetermined timing.

The data replacement circuit 22 includes a replacement data ROM
The order of the coded data D2 supplied from the input data holding memory 21 is rearranged based on the replacement position information of the data stored in 23. Data replacement circuit 22
Supplies the rearranged data to the output data holding memory 24.

The replacement data ROM 23 stores, for example, replacement position information of data determined based on the generated random numbers. Of course, replacement data ROM23 stores a replacement location information substitution in symbol units to hold a combination of 3-bit encoded data _{D2 1, D2 2, D2 3} . The replacement position information stored in the replacement data ROM 23 is read by the data replacement circuit 22 as needed.

The output data holding memory 24 holds the data supplied from the data replacing circuit 22 and converts the data into interleaved data D consisting of three bit sequences.
3 _1, as D3 _2, D3 _3, and outputs to the subsequent convolutional coder 30 at a predetermined timing.

The interleaver 20 performs pairwise interleaving on the encoded data D2 output from the convolutional encoder 10 and outputs the result to the convolutional encoder 30 at the subsequent stage.

More specifically, the input data holding memory 2
1, the coded data D2 ₁ that is output from the encoder 10 convolutional, D2 _2, D2 ₃ to sequentially input hold. Then, the input data holding memory 21 sequentially holds, for example, each bit constituting the encoded data D2 ₁ , D2 ₂ , D2 ₃ at a predetermined timing, and stores _three bits of N bits (N is an arbitrary natural number). The held data is supplied to the data replacement circuit 22 at the timing when the bit sequence is generated.

Subsequently, the data replacement circuit 22 determines the order of the N symbols constituting the three bit sequences supplied from the input data holding memory 21 based on the replacement position information stored in the replacement data ROM 23. Sort. The data replacement circuit 22 supplies a new bit sequence obtained by the rearrangement to the output data holding memory 24.

[0058] Then, the output data holding memory 24 holds each bit constituting the bit sequence supplied from the data replacement circuit 22, the held data as interleave data _{D3 1, D3 2, D3 3} , a predetermined timing Output to the subsequent convolutional encoder 30.

As described above, the interleaver 20 receives the coded data D2 ₁ , D2 ₂ , and D2 ₃ consisting of three bit sequences output from the convolutional coder 10, and inputs these coded data D2 ₁ , The order of each bit constituting D2 ₂ and D2 ₃ is rearranged on a symbol basis based on the replacement position information stored in advance, and the interleaved data D
3 _1, to produce a D3 _2, D3 _3.

As shown in FIG. 6, the convolutional encoder 30 has two shift registers 31, 33 and two exclusive OR circuits 32, 34.

The shift register 31 continues to supply the held 1-bit data to the exclusive OR circuit 32.
Then, the shift register 31 newly holds 1-bit data supplied from the exclusive OR circuit 34 in synchronization with the clock, and stores this data in the exclusive OR circuit 3.
2 is newly supplied.

[0062] exclusive OR circuit 32, 3 and 1 bit interleaved data D3 ₂ of the bits of the interleaved data D3, and the data supplied from the shift register 31, data supplied from the exclusive OR circuit 34 And an exclusive-OR operation is performed using the and, and the operation result is supplied to the shift register 33.

The shift register 33 continues to supply the held 1-bit data to the exclusive OR circuit 34.
Then, the shift register 33 newly holds the 1-bit data supplied from the exclusive OR circuit 32 in synchronization with the clock, and stores this data in the exclusive OR circuit 3.
4 is newly supplied.

The exclusive OR circuit 34 performs an exclusive OR operation using the 1-bit interleaved data D33 of the _3- bit interleaved data D3 and the data supplied from the shift register 33. The result is supplied to the shift register 31, and one-bit encoded data D43 of the _3- bit encoded data D4 is supplied.
Is output to the multi-level modulation mapping circuit 40 at the subsequent stage.

[0065] the convolutional encoder 30 inputs the 3-bit interleaved data D3 _1, D3 _2, D3 _3, the interleave data D3 _1, D3 _2, respectively, of the 3-bit encoded data D4 as a 2-bit encoded data D4 _1, D4 ₂ of directly to output to the subsequent multi-level modulation mapping circuit 40 performs a recursive convolutional operation on the interleaved data D3 _2, D3 _3, 3-bit operation result It is output as one bit of the encoded data D4 ₃ of the encoded data D4 to the subsequent multi-level modulation mapping circuit 40. That is, the convolutional encoder 30 encodes the inner code as “3 /
3 = 1 "is performed, and the encoded data D
4 is output to the multi-level modulation mapping circuit 40 at the subsequent stage.

The convolutional encoder 30 is configured not to be terminated in one time slot, which will be described in detail later.

The multi-level modulation mapping circuit 40 synchronizes the encoded data D4 output from the convolutional encoder 30 with a clock, for example, as shown in FIG.
It maps to the transmission symbol of a modulation system. That is,
The multi-level modulation mapping circuit 40 includes the convolutional encoder 30
Is mapped as one transmission symbol to generate one encoded transmission symbol D5. The multi-level modulation mapping circuit 40
The generated encoded transmission symbol D5 is output to the outside.

In such an encoding device 1, the convolutional encoder 10 encodes the outer code as an encoding of an outer code of “2 /
3 ", and the convolutional encoder 30 performs a convolution operation with an encoding rate of" 1 "as the encoding of the inner code, so that the encoding rate is" (2/3) × 1 =
2/3 "tandem convolution operation is performed. The data encoded and modulated by the encoding device 1 is output to the receiving device via the memoryless communication path 2.

On the other hand, as shown in FIG.
Two soft-output decoding circuits 50 and 80, which are first soft-output decoding means and second soft-output decoding means for performing soft-output decoding, and reverse permutation means for returning the order of input data to its original state , An interleaver 70 as a second replacement unit for rearranging the order of input data, and a binarization circuit 90 as a binarization unit for binarizing the input data. . The decoding device 3 estimates an input data D1 in the encoding device 1 from a received word D6 which is taken as a soft-input by taking an analog value under the influence of noise generated on the memoryless communication channel 2, and decodes the data. Output as data D13.

The soft output decoding circuit 50 is provided corresponding to the convolutional encoder 30 in the encoding device 1. As shown in FIG. 9, the soft output decoding circuit 50 has a maximum posterior probability (Maximum A Posteriori) based on the so-called BCJR (Bahl, Cocke, Jelinek and Raviv) algorithm.
probability; hereinafter, referred to as MAP. ) MA performing decryption
A P decoder 51 and eight differentiators 52 ₁ , 52 ₂ , 52 ₃ ,
52 ₄ , 52 ₅ , 52 ₆ , 52 ₇ , 52 ₈ .

The MAP decoder 51 outputs a priori probability information (a pr) for the received word D 6 as a soft input and the 8-bit information symbol as a soft input supplied from the interleaver 70.
_{ioriprobability information) D7 1, D7 2} , D7 3,
_{D7 4, D7 5, D7 6} , D7 7, D7 inputs the _8, BC
MAP decoding is performed based on the JR algorithm, and the received word D
6, posteriori probability information D14 ₁ for an 8-bit information symbol,
_{D14 2, D14 3, D14 4} , D14 5, D14 6, D1
Generating a 4 _7, D14 _8. MAP decoder 51 supplies the posteriori probability information D14 ₁ to generated the differentiator 52 ₁ supplies the generated posteriori probability information D14 ₂ to the differentiator 52 _2, generated posteriori probability information D14 ₃ to differentiator 52 is supplied to the _3, generated posteriori probability information D1
4 ₄ supplies to the differentiator 52 ₄ supplies the posteriori probability information D14 ₅ that generated the differentiator 52 ₅ supplies a posteriori probability information D14 ₆ generated to the differentiator 52 _6, resulting posterior probabilities supplies information D14 ₇ to the differentiator 52 ₇ supplies the posteriori probability information D14 ₈ which generated the differentiator 52 _8.

[0072] The differentiator 52 ₁ obtains a difference value between priori probability information D7 ₁ that is posteriori probability information D14 ₁ and soft-input are soft-input, 8-bit calculated the difference value by the code constraint condition and outputs as a soft output to the subsequent deinterleaver 60 as the external information D8 ₁ of one bit of the external data D8 to the information symbols.

[0073] The differentiator 52 ₂ obtains a difference value between priori probability information D7 ₂ that is posteriori probability information D14 ₂ and soft-input are soft-input, external information the difference values for 8-bit information symbol D8 and outputs as a soft output to the subsequent deinterleaver 60 as the external information D8 ₂ of 1 bit of.

[0074] The differentiator 52 ₃ obtains a difference value between priori probability information D7 ₃ that is posteriori probability information D14 ₃ and soft-input are soft-input, external information the difference values for 8-bit information symbol D8 and outputs as a soft output to the subsequent deinterleaver 60 as a 1-bit external data D8 ₃ of.

[0075] The differentiator 52 ₄ obtains a difference value between priori probability information D7 ₄ which are posteriori probability information D14 ₄ and soft-input are soft-input, external information the difference values for 8-bit information symbol D8 and outputs as a soft output to the subsequent deinterleaver 60 as a 1-bit external data D8 ₄ of.

[0076] The differentiator 52 ₅ obtains a difference value between priori probability information D7 ₅ that is posteriori probability information D14 ₅ and soft-input are soft-input, external information the difference values for 8-bit information symbol D8 and outputs as a soft output to the subsequent deinterleaver 60 as the external information D8 ₅ of one bit of the.

[0077] The differentiator 52 ₆ obtains a difference value between priori probability information D7 ₆ which are posteriori probability information D14 ₆ and the soft-input are soft-input, external information the difference values for 8-bit information symbol D8 and outputs as a soft output to the subsequent deinterleaver 60 as the external information D8 ₆ of one bit of the.

[0078] The differentiator 52 ₇ calculates a difference value between the a priori probability information D7 ₇ which are posteriori probability information D14 ₇ and soft-input are soft-input, external information the difference values for 8-bit information symbol D8 and outputs as a soft output to the subsequent deinterleaver 60 as a 1-bit external data D8 ₇ of the.

[0079] The differentiator 52 ₈ calculates a difference value between the a priori probability information D7 ₈ which are posteriori probability information D14 ₈ and soft-input are soft-input, external information the difference values for 8-bit information symbol D8 and outputs as a soft output to the subsequent deinterleaver 60 as a 1-bit external data D8 ₈ of.

The soft-output decoding circuit 50 receives the soft-input received word D6 received by the receiving device, and inputs the prior probability information D7 for the soft-input information symbol supplied from the interleaver 70. MAP decoding based on the BCJR algorithm is performed using the received word D6 and the prior probability information D7, and soft output decoding of the inner code is performed. The soft-output decoding circuit 50 generates the external information D8 obtained according to the code constraint condition.
8 is output to the subsequent deinterleaver 60 as a soft output.

For a specific description, if the information symbol is u, the code symbol is c, and the received word D6 is y, the soft output decoding circuit 50 sends the received word D6 (y) to the MAP decoder 51. At the same time, prior probability information D7 (L (u)) expressed by the following equation (1) is input.

[0082]

(Equation 1)

That is, the soft output decoding circuit 50
The received word D6 (y) is input to the decoder 51, and the probability P that the information symbol u is “000” is
(U = 000), the probability P (u = 001) that the information symbol u is “001”, and the information symbol u is “01”
0 ", the probability P (u = 010), the information symbol u
Is the probability P (u = 011) that is “011”, the probability P (u = 100) that the information symbol u is “100”,
The probability P (u = 1) that the information symbol u is “101”
01), the probability P that the information symbol u is “110”
(U = 110) and the information symbol u is "111"
Prior probability information D7 (L) having no constraint condition of the code represented by the natural logarithm of the probability P (u = 111)
(U)).

Subsequently, the soft-output decoding circuit 50 uses the MAP decoder 51 to execute the MA based on the BCJR algorithm.
P decoding and posterior probability information D1 expressed by the following equation (2)
4 (L ^* (u)).

[0085]

(Equation 2)

That is, the soft output decoding circuit 50
When the decoder 51 receives the received word D6 (y), the probability P (u) that the information symbol u is “000”
= 000), the probability P (u = 001) that the information symbol u is “001”, the probability P (u = 010) that the information symbol u is “010”, and the probability that the information symbol u is “0”.
11 ”, the probability P (u = 100) that the information symbol u is“ 100 ”, and the probability P (u = 10) that the information symbol u is“ 101 ”.
1) The probability P that the information symbol u is "110"
(U = 110) and the information symbol u is "111"
Posterior probability information D14 based on the constraint condition of the sign expressed by the natural logarithm of the probability P (u = 111)
(L ^* (u)).

Then, the soft output decoding circuit 50
21 ₁ , 52 ₂ , 52 ₃ , 52 ₄ , 52 ₅ , 52 ₆ , 52 ₇ , 5
By each of 2 _8, as represented by the following formula (3), the external information is a difference value between the posteriori probability information D14 (L ^* (u)) and a priori probability information D7 (L (u)) D8
(L _e (u)) is obtained.

[0088]

(Equation 3)

The soft output decoding circuit 50 generates the external information D8 in this manner, and outputs the external information D8 to the subsequent deinterleaver 60 as a soft output. The external information D8 is transmitted to the interleaver 2 in the encoding device 1.
Interleave data D interleaved with 0
This corresponds to No. 3.

The deinterleaver 60 converts the bit arrangement of the interleaved data D3 interleaved by the interleaver 20 in the encoding device 1 into
In order to return to the original bit array of the encoded data D2, that is, to return the symbol array composed of the set of encoded data D3 interleaved by the interleaver 20 to the symbol array composed of the original set of encoded data D2. ,
Soft-input external information D output from soft-output decoding circuit 50
8 is deinterleaved. Deinterleaver 60
Outputs the data obtained by deinterleaving as prior probability information D9 for the code symbol in the subsequent soft output decoding circuit 80.

The interleaver 70 has a soft output decoding circuit 8
For the external information D12 for the soft input code symbol output from 0, this 8-bit external information D12
While performing the interleaving based on the same replacement position information as the interleaver 20 in the encoding device 1. The interleaver 70 outputs the data obtained by the interleaving as prior probability information D7 for the information symbol in the soft output decoding circuit 50.

The soft output decoding circuit 80 is provided corresponding to the convolutional encoder 10 in the encoding device 1. As shown in FIG. 10, the soft output decoding circuit 80 includes a MAP decoder 81 that performs MAP decoding based on the above-described BCJR algorithm, and ten differentiators 82 ₁ , 82 ₂ , and 8.
3 _1, 83 _2, 83 _3, 83 _4, 83 _5, 83 _6, 83 _7, 8
And a 3 _8.

The MAP decoder 81 has a deinterleaver 6
Priori probability information for 8-bit code symbol is a soft-input output from _{0 D9 1, D9 2, D9} 3, D9 4, D
9 ₅ , D 9 ₆ , D 9 ₇ , D 9 _8, and prior probability information D 10 ₁ , D 10 ₂ for two information bits whose value is “0”
MAP decoding based on the BCJR algorithm, and posterior probability information D for two information bits
15 ₁ , D 15 ₂ and posterior probability information D 16 ₁ , D 16 ₂ , D 16 for an 8-bit code symbol
_3, D16 _4, D16 _5, to produce a _{D16 6, D16 7, D16 8} . The MAP decoder 81 generates the posterior probability information D
15 ₁ is supplied to the differentiator 82 ₁ , and the generated posterior probability information D15 ₂ is supplied to the differentiator 82 ₂ . Also, MA
P decoder 81 supplies the posteriori probability information D16 ₁ to generated the differentiator 83 _1, generated posteriori probability information D
16 ₂ is supplied to the differentiator 83 ₂ , the generated posterior probability information D 16 ₃ is supplied to the differentiator 83 ₃ , the generated posterior probability information D 16 ₄ is supplied to the differentiator 83 ₄ , and the generated posterior probability is generated. supplies information D16 ₅ to the differentiator 83 ₅ supplies a posteriori probability information D16 ₆ which generated the differentiator 83 ₆ supplies the posteriori probability information D16 ₇ that generated the differentiator 83 _7, resulting post supplying the probability information D16 ₈ to the differentiator 83 _8.

[0094] The differentiator 82 _1, the difference value between the a priori probability information D10 ₁ is a posteriori probability information D15 ₁ and value "0" which is soft-input, i.e., a posteriori probability information D15 ₁ by the code constraint condition As one bit of external information D11 ₁ of the external information D11 corresponding to the obtained two information bits, the external information is output to the subsequent binarization circuit 90 as a soft output.

[0095] The differentiator 82 _2, a difference value between the a priori probability information D10 ₂ is a posteriori probability information D15 ₂ and value "0" which is soft-input, i.e., the information bits of two bits posteriori probability information D15 ₂ and outputs as a soft output to the subsequent binarizing circuit 90 as the external information D11 ₂ of one bit of the external data D11 for.

[0096] The differentiator 83 ₁ obtains a difference value between priori probability information D9 ₁ which is the posterior probability information D16 ₁ and soft-input are soft-input, external information the difference values for 8-bit code symbols D12 1-bit external information D12 of
_{As 1} it is output to the interleaver 70 as a soft output.

[0097] The differentiator 83 ₂ obtains a difference value between the priori probability information D9 ₂ that is the posterior probability information D16 ₂ and soft-input are soft-input, external information the difference values for 8-bit code symbols D12 1-bit external information D12 of
_{As 2} is output to the interleaver 70 as a soft output.

[0098] The differentiator 83 ₃ obtains a difference value between priori probability information D9 ₃ that is posteriori probability information D16 ₃ and soft-input are soft-input, external information the difference values for 8-bit code symbols D12 1-bit external information D12 of
_{As 3} is output as a soft output to the interleaver 70.

[0099] The differentiator 83 ₄ obtains a difference value between priori probability information D9 ₄ which are posteriori probability information D16 ₄ and soft-input are soft-input, external information the difference values for 8-bit code symbols D12 1-bit external information D12 of
₄ and output to the interleaver 70 as a soft output.

[0100] The differentiator 83 ₅ obtains a difference value between priori probability information D9 ₅ which is the posterior probability information D16 ₅ and soft-input are soft-input, external information the difference values for 8-bit code symbols D12 1-bit external information D12 of
_{As 5} , output to the interleaver 70 as a soft output.

[0102] The differentiator 83 ₆ calculates a difference value between the a priori probability information D9 ₆ which are posteriori probability information D16 ₆ and the soft-input are soft-input, external information the difference values for 8-bit code symbols D12 1-bit external information D12 of
₆ and output to the interleaver 70 as a soft output.

The differentiator 83 ₇ calculates a difference value between the posterior probability information D16 _{7 which} is a soft input and the prior probability information D97 ₇ which is a soft input, and calculates the difference value by using the external information D12 for an 8-bit code symbol. 1-bit external information D12 of
₇ and output to the interleaver 70 as a soft output.

[0103] The differentiator 83 ₈ calculates a difference value between the a priori probability information D9 ₈ which are posteriori probability information D16 ₈ and soft-input are soft-input, external information the difference values for 8-bit code symbols D12 1-bit external information D12 of
₈ and output to the interleaver 70 as a soft output.

The soft output decoding circuit 80 receives the prior probability information D9 for the soft input code symbol output from the deinterleaver 60 and the prior probability information D10 for the information bit whose value is "0". And using these prior probability information D9, D10,
MAP decoding based on the BCJR algorithm is performed, and soft output decoding of the outer code is performed. The soft output decoding circuit 80 generates the external information D11 and D12 determined by the code constraint condition, outputs the external information D11 to the subsequent binarization circuit 90 as a soft output, and outputs the external information D12 to the interleaver 70. Output as soft output.

For a specific description, if the information bits are u and the code symbol is c, the soft output decoding circuit 80
Is given to the MAP decoder 81 by the prior probability information D10 (L (u)) expressed by the following equation (4) and the prior probability information D9 (L (c)) expressed by the following equation (5). Enter

[0106]

(Equation 4)

[0107]

(Equation 5)

That is, the soft output decoding circuit 80
For the decoder 81, the probability P (u = 1) that the information bit u is "1" and the probability P that the information bit u is "0"
Prior probability information D10 (L (u)) based on the constraint condition of the code represented by the natural logarithm of the ratio to (u = 0) is input, and the probability P that the code symbol c is “000” is input.
(C = 000), the probability P (c = 001) that the code symbol c is “001”, and the code symbol c is “01”
0 ", P (c = 010), code symbol c
Is "011", the probability P (c = 100) that the code symbol c is "100",
The probability P (c = 1) that the code symbol c is “101”
01), the probability P that the code symbol c is “110”
(C = 110) and the code symbol c is "111"
Prior probability information D9 (L) based on the constraint condition of the code expressed by the natural logarithm of the probability P (c = 111)
Enter (c)). Note that the constraint condition of the code to be written on the right side in the above equations (4) and (5) is
It is omitted here. Here, the prior probability information D
10 (L (u)) is “0”, which means that the probability that the information bit u is “0” or “1” is １ ／.
It is nothing more than showing that

Subsequently, the soft-output decoding circuit 80 uses the MAP decoder 81 to execute the MA based on the BCJR algorithm.
P decoding and posterior probability information D1 expressed by the following equation (6)
5 (L ^* (u)) and posterior probability information D16 (L ^* (c)) expressed by the following equation (7).

[0110]

(Equation 6)

[0111]

(Equation 7)

That is, the soft-output decoding circuit 80
The probability that the information bit u is “1” by the decoder 81
P (u = 1) and the probability P that the information bit u is "0"
Constraint condition of code expressed by natural logarithm of ratio to (u = 0)
Posterior probability information D15 (L^*(U))
And the probability P that the code symbol c is "000"
(C = 000) and the code symbol c is “001”
Probability P (c = 001) and the code symbol c is "01"
0 ", P (c = 010), code symbol c
Is “011”, the probability P (c = 011),
The probability P (c = 100) that the vol c is “100”,
The probability P (c = 1) that the code symbol c is “101”
01), the probability P that the code symbol c is “110”
(C = 110) and the code symbol c is "111"
Is the natural logarithm of the probability P (c = 111)
Posterior probability information D16 based on the constraint condition of the represented code
(L^*(C)) is generated. Note that the above equation (6) and
The constraint condition of the code to be written on the right side in equation (7)
Is omitted here. In addition, posterior probability information D15
(L ^*(U)) is the log likelihood rati
o), which here indicate the likelihood of the information bit u
Things.

Then, the soft output decoding circuit 80
As represented by the following equation (8), an external value which is a difference value between the posterior probability information D15 (L ^* (u)) and the prior probability information D10 (L (u)) by each of 2 ₁ and 82 _2. Information D1
1 (L _e (u)) and differentiators 83 ₁ , 83
_2, 83 _3, 83 _4, 83 _5, 83 _6, 83 _7, 83 by the respective _8, as represented by the following formula (9), priori probability information and a posteriori probability information D16 (L ^* (c)) D9 (L
(C)) and the external information D12 (L
_e (c)) is obtained.

[0114]

(Equation 8)

[0115]

(Equation 9)

The soft output decoding circuit 80 generates the external information D11 and D12 in this way, outputs the external information D11 to the subsequent binarization circuit 90 as a soft output, and outputs the external information D12 to the interleaver 70. Output as soft output.

Note that the soft output decoding circuit 80 determines that the prior probability information D10 for the information bit is "0".
It is not always necessary to provide the differentiators 82 ₁ and 82 ₂ .

The binarizing circuit 90 converts the external information D11 supplied from the soft output decoding circuit 80 into two based on the soft output external information D11 generated by the soft output decoding circuit 80, that is, the posterior probability information D15. And hard output (hard-o
utput) as decoded data D13.

Since the decoding device 3 includes the soft output decoding circuits 50 and 80 corresponding to the convolutional encoders 30 and 10 in the encoding device 1, the decoding device 3 converts a code having a high decoding complexity into a code having a high decoding complexity. By decomposing into small elements, the characteristics can be sequentially improved by the interaction between the soft output decoding circuits 50 and 80. When receiving the received word D6, the decoding device 3 repeats the decoding operation of the soft output decoding circuits 50 to 80 a predetermined number of times, for example, several to several tens of times, and performs the decoding operation a predetermined number of times. The decoded data D13 is output based on the soft output external information D11 obtained as a result of the above, that is, the posterior probability information D15. In particular, since the decoding device 3 performs decoding using external information for each symbol, high-performance decoding can be realized.

The encoding apparatus 1 performs pairwise interleaving as described above in order to perform iterative decoding using the external information for each symbol by the decoding apparatus 3, but in a normal encoding apparatus, pairwise interleaving is performed. , A large number of short termination patterns such that the inner code terminates in one time slot appear, and the performance may be degraded. Therefore, it is desirable to use a convolutional encoder that does not terminate in one time slot as the convolutional encoder that encodes the inner code. Hereinafter, this will be described.

In the encoding apparatus, when performing pairwise interleaving, whether or not an inner code ends in one time slot is determined by a convolutional encoder that encodes an outer code and a convolutional encoder that encodes an inner code. There is not less relation to the combination with the encoder.

Here, as shown in FIG. 11, another encoding apparatus 1 'different from the encoding apparatus 1 is considered. This encoding device 1 'includes convolutional encoders 10' and 30 ', an interleaver 20', and a multi-level modulation mapping circuit 40 ', and performs encoding by the SCTCM method.

As shown in FIG. 12, the convolutional encoder 10 'comprises four exclusive OR circuits 11', 13 ', 1
5 ', 17' and three shift registers 12 ', 1
4 ′, 16 ′.

The exclusive OR circuit 11 'performs an exclusive OR operation using 2-bit input data D1', and supplies the operation result to the shift register 12 '.

The shift register 12 'holds 1
The bit data continues to be supplied to the exclusive OR circuit 13 '. Then, the shift register 12 'newly holds the 1-bit data supplied from the exclusive OR circuit 11' in synchronization with the clock, and newly supplies the data to the exclusive OR circuit 13 '. .

The exclusive-OR circuit 13 ′ is a 1-bit input data D 1 ₂ ′ of the _2- bit input data D 1 ′.
And an exclusive OR operation is performed using the data supplied from the shift register 12 ′ and the operation result is supplied to the shift register 14 ′.

The shift register 14 'holds 1
The bit data is continuously supplied to the exclusive OR circuit 15 '. Then, the shift register 14 'newly holds 1-bit data supplied from the exclusive OR circuit 13' in synchronization with the clock, and newly supplies this data to the exclusive OR circuit 15 '. .

The exclusive-OR circuit 15 'outputs 1-bit input data D1 ₁ ' of 2-bit input data D1 '.
And the data supplied from the shift register 14 'to perform an exclusive OR operation, and supply the operation result to the shift register 16'.

The shift register 16 'holds 1
The bit data is continuously supplied to the exclusive OR circuit 17 '. Then, the shift register 16 ′ newly holds the 1-bit data supplied from the exclusive OR circuit 15 ′ in synchronization with the clock, and newly supplies this data to the exclusive OR circuit 17 ′. .

The exclusive OR circuit 17 'performs an exclusive OR operation using the 2-bit input data D1' and the data supplied from the shift register 16 ', and encodes the operation result into a 3-bit code. As the 1-bit encoded data D2 ₃ 'of the data D2', the interleaver 20 '
Output to

Such a convolutional encoder 10 ′
When the input data D1 ₁ ′ and D1 ₂ ′ are input, the input data D1 ₁ ′ and D1 ₂ ′ are respectively converted into the encoded data of the 2-bit tissue component of the encoded data D2 ′ of 3 bits. D2 ₁ ′ and D2 ₂ ′ are output directly to the interleaver 20 ′ at the subsequent stage, and the input data D1 ₁ ′ and D1 ₂ ′ are subjected to a systematic convolution operation.
The operation result is output to the interleaver 20 'at the subsequent stage as 1-bit encoded data D2 ₃ ' of the _3- bit encoded data D2 '. That is, the convolutional encoder 1
0 ′ performs a convolution operation with a coding rate of “2/3” as the outer code, as in the convolutional encoder 10,
The coded data D2 'is output to the interleaver 20' at the subsequent stage.

As shown in FIG. 13, the interleaver 20 'includes an input data holding memory 21', a data replacement circuit 22 ', a replacement data ROM 23', and an output data holding memory 24 '. Like 20,
The input 3-bit encoded data D2 ₁ ′, D2 ₂ ′, D
The set of 2 ₃ ′ is defined as one symbol, and this symbol is subjected to pair-wise interleaving.
The interleaver 20 ′, like the interleaver 20, encodes data D2 ₁ ′, D2 ₂ ′, D2 composed of three bit sequences output from the convolutional encoder 10 ′.
2 ₃ ′, and these encoded data D 2 ₁ ′, D 2
The order of each bit constituting 2 ₂ ′ and D 2 ₃ ′ is rearranged on a symbol basis based on replacement position information stored in advance, and interleaved data D 3 ₁ ′, D 3 ₂ ′ and D _{3 3} ′ are arranged.
Generate The interleaver 20 ′ outputs the generated interleave data D3 ₁ ′, D3 ₂ ′, D3 ₃ ′ to the subsequent convolutional encoder 30 ′.

As shown in FIG. 14, the convolutional encoder 30 'includes an exclusive OR circuit 31' and a shift register 3 '.
2 ′.

The exclusive OR circuit 31 'performs an exclusive OR operation using the 3-bit interleaved data D3', supplies the operation result to the shift register 32 ', and outputs the 3-bit encoded data D4'. output to 'subsequent multi-level modulation mapping circuit 40 as a' 1-bit encoded data D4 ₃ of.

The shift register 32 'holds 1
The bit data is continuously supplied to the exclusive OR circuit 31 '. Then, the shift register 32 'newly holds the 1-bit data supplied from the exclusive OR circuit 31' in synchronization with the clock, and newly supplies this data to the exclusive OR circuit 31 '. .

Such a convolutional encoder 30 ′
Bit interleaved data D3 ₁ ′, D3 ₂ ′, D3
_{When 3} 'is input, the interleaved data D3 ₂ ', D3
₃ ′ as 2-bit encoded data D4 ₁ ′ and D4 ₂ ′ of 3-bit encoded data D4 ′, respectively.
The data is output as it is to the subsequent multi-level modulation mapping circuit 40 ', and the interleaved data D3 ₁ ', D3 ₂ ',
D3 ₃ 'performs the recursive convolution operation on the operation result 3-bit encoded data D4' output to 'subsequent multi-level modulation mapping circuit 40 as a' 1-bit encoded data D4 ₃ of. That is, the convolutional encoder 3
0 ′ performs a recursive convolution operation with an encoding rate of “3/3 = 1” as the encoding of the inner code, similarly to the convolutional encoder 30, and converts the encoded data D 4 ′ into the subsequent multi-level modulation mapping. Output to the circuit 40 '.

The multi-level modulation mapping circuit 40 ′, like the multi-level modulation mapping circuit 40,
The coded data D4 'output from 0' is mapped to a transmission symbol of, for example, an 8PSK modulation system in synchronization with a clock to generate one coded transmission symbol D5 '. Specifically, the multi-level modulation mapping circuit 40 '
For example, as shown in FIG. 15, signal point mapping is performed. The multi-level modulation mapping circuit 40 'outputs the generated encoded transmission symbol D5' to the outside.

[0138] Such an encoding device 1 'performs a cascade convolution operation with an encoding rate of "(2/3) x 1 = 2/3", similarly to the encoding device 1. The data encoded and modulated by the encoding device 1 ′
Is output to the receiving device provided with the decoding device 3 via the.

FIG. 16 shows the trellis of the convolutional encoder 30 'in the encoding device 1'. In the figure, the labels attached between the states are as follows:
Each shows an input / output. For example, in the trellis shown in the figure, four branches indicating “0” → “1” have “001”, “100”, and “0” in the state “0”.
When "10" and "111" are input,
"011", "001", "101", and "111" are output to indicate that the state transits to the state "1".

[0140] As can be seen from the trellis, the convolutional encoder 30 ', when the states, for example "0", 3-bit interleaved data D3 _1', D3 ₂ ', D3 _3' as, "D3 ₁ 'D3 ₂ 'D3 ₃ ' = 110 'or' D3 ₁ '
If D3 ₂ 'D3 ₃ ' = 010 "is input, the processing ends as it is. That is, the convolutional encoder 30 '
There is a high possibility that one time slot ends. Therefore, in order not to terminate the convolutional encoder 30 'in one time slot, the interleaved data D
The condition is that “110” or “010” should not be input as 3 ′.

Based on this, when examining the relationship between the input data D1 ', the encoded data D2', and the interleaved data D3 ', the convolutional encoder 10' recognizes that the input data D1 ₁ 'and D1 ₂ ' are "D1 If you enter a ₁ 'D1 _2' = 11 _{"or" D1 1 'D1 2' =} 10 ", the encoded data D2 ₁ ', D2 _2', as D2 ₃ ', respectively,
"D2 ₁ 'D2 ₂ ' D2 ₃ '= 110" or "D2 ₁ ' D2
₂ 'D2 ₃ ' = 010 "is output.
These encoded data D2 'are transmitted to the interleaver 20'.
Is interleaved in symbol units by
The convolutional encoder 30 'includes the interleaved data D
'As, "D3 _1' 3 so that _{D3 2 'D3 3' = 110} " Ya _{"D3 1 'D3 2' D3} 3 '= 010" is input.

As described above, in the encoding device 1 ',
Since the interleaved data D3 'for terminating the convolutional encoder 30' in one time slot appears in two time slots, and the interleaved data D3 'terminates the convolutional encoder 30', the minimum weight pattern is It will appear very often.

On the other hand, the encoding apparatus 1 has a very low possibility that interleaved data D3 for terminating the convolutional encoder 30 in one time slot appears, and a short termination pattern hardly appears. Can be realized.

Actually, a performance curve in a data transmission / reception system constituted by using the encoding apparatus 1 and the decoding apparatus 3, that is, a logarithmic representation (log) of the bit error rate
₁₀ BER) and the signal to noise power ratio per bit (E
When determining the performance curves shown in relation to the _b / N _0), for example, as shown in FIG. 17 the curve C _A. In the figure, for the sake of comparison, the performance curve of a system constituted by using the encoding device 1 ′ and the decoding device 3 is represented by a curve C _B.
As shown.

[0145] As apparent from the figure, the curve C _B is, E _b
It can be seen that the bit error rate shows a tendency to be almost flat regardless of the increase in / N ₀ . On the other hand, curve C
_A indicates that the bit error rate tends to decrease monotonically with an increase in E _b / N ₀ . Therefore, data transmission and reception system, as compared to the system performance curve is shown by the curve C _B, it can be seen that there is a significant coding gain.

As described above, the data transmission / reception system configured using the encoding device 1 and the decoding device 3
In the encoding device 1, the inner code that does not end in one time slot is used, the pair code is interleaved with the outer code, and the decoding device 3 performs iterative decoding using external information for each symbol. High performance encoding / decoding can be performed.

That is, the data transmission / reception system configured by using the encoding device 1 and the decoding device 3 realizes high-performance tandem concatenated convolutional coding and decoding, and is highly user-friendly. It can provide reliability.

The present invention is not limited to the above-described embodiment. For example, as an encoding device,
The present invention is applicable to any coding rate. In this case, of course, the encoding device performs the pair-wise interleaving using the encoded data of a plurality of bits output from the convolutional encoder that encodes the outer code as one symbol.

In the above-described embodiment, the prior probability information for the information symbols or code symbols input to the soft output decoding circuit in the decoding apparatus and the posterior probability information for the information symbols output from the soft output decoding circuit are used as information. The prior probability information, the posterior probability information, and the external information are represented as eight types of information as a natural logarithm of the probability that can be taken as a symbol or a code symbol. For example, as shown in the following equation (10), The ratio of the probability of each symbol to the probability of one symbol may be expressed as a natural logarithm. By doing so, the decoding device can represent the prior probability information, the posterior probability information, and the external information as seven types of information, and the circuit scale is further reduced.

[0150]

(Equation 10)

Further, in the above-described embodiment, a description has been given of a case where the MAP decoding based on the BCJR algorithm is performed as the soft output decoding circuit in the decoding apparatus.
The present invention relates to a so-called SOVA (Soft Output Vite
The present invention can be applied to other soft-output decoding such as decoding by rbi algorithm).

Furthermore, in the above-described embodiment, the encoding device and the decoding device are applied to the transmitting device and the receiving device in the data transmitting / receiving system, but the present invention is applied to, for example, a floppy (registered trademark) disk and a CD. -R
The present invention can also be applied to a recording and / or reproducing apparatus that performs recording and / or reproduction on a recording medium such as a magnetic, optical, or magneto-optical disk such as OM or MO (Magneto Optical). In this case, the data encoded by the encoding device is recorded on a recording medium equivalent to a memoryless communication channel,
The data is decoded and reproduced by the decoding device.

Further, in the above-described embodiment, the encoding device and the decoding device are described as devices constituted by hardware. However, both the encoding device and the decoding device are, for example, a workstation or a personal computer. It can be realized as software executable on a computer device such as Hereinafter, this example will be described with reference to FIG.

As shown in the figure, the computer device 150 has a CPU (Central Procedures) that controls all the components.
sing unit) 151, a read-only ROM 152 for storing information including various programs, and a RAM (Random Access Memory) 153 functioning as a work area.
An HDD (Hard Disk Drive) 154 for recording and / or reproducing various programs and data;
PU 151, ROM 152, RAM 153, and HDD1
, A CPU 155 and a ROM 1
52, a RAM 153, an HDD 154, and a display unit 157, an input unit 158, a communication unit 159, and a drive 16 which will be described later.
And an input / output interface 156 for inputting / outputting data to / from a display unit 157, and a display unit 157 for displaying various information.
And an input unit 158 for receiving an operation by a user, a communication unit 159 for communicating with the outside, and a drive 160 for recording and / or reproducing various information on a removable recording medium 170.

The CPU 151 executes the RO
M152, RAM 153, and HDD 154, and these ROM 152, RAM 153, and HDD 1
54 is controlled. Further, the CPU 151 is connected to the input / output interface 156 via the bus 155,
The display unit 157, the input unit 158, the communication unit 159, and the drive 160 connected to the input / output interface 156 are controlled. Further, the CPU 151 stores in the ROM 1
52, to execute various programs recorded on the recording medium 170 mounted on the HDD 154 or the drive 160.

The ROM 152 stores information including various programs. The information stored in the ROM 152 is read out under the control of the CPU 151.

The RAM 153 functions as a work area when the CPU 151 executes various programs.
Various data are temporarily stored under the control of U151.

The HDD 154 records and / or reproduces various programs and data on the hard disk under the control of the CPU 151.

The bus 155 transmits various data and the like read from the ROM 152, the RAM 153, and the HDD 154 under the control of the CPU 151.
153 and various data to be recorded in the HDD 154 are transmitted.

The input / output interface 156 has a CPU
An interface for displaying various information on the display unit 157 under the control of the user;
A control signal indicating the content operated via the CPU 151
Interface for transmitting data to the CPU 1
An interface for inputting and outputting data to and from the outside via the communication unit 159 under the control of 51, and for recording and / or reproducing various information on the recording medium 170 mounted on the drive 160 Interface, and displays data from the CPU 151, the ROM 152, the RAM 153, and the HDD 154 on the display unit 157, the input unit 15
8, output to the communication unit 159 and the drive 160, and data from the display unit 157, the input unit 158, the communication unit 159 and the drive 160 to the CPU 151 and the ROM 15
2, input to RAM 153 and HDD 154.

The display unit 157 is, for example, an LCD (Liquid C
and various information such as data recorded in the HDD 154 under the control of the CPU 151.

The input unit 158 receives, for example, a keyboard or mouse operation by the user, and outputs a control signal indicating the contents of the operation to the CPU 151.

Under the control of the CPU 151, the communication section 159 functions as an interface for communicating with the outside via, for example, a network line or a satellite line.

The drive 160 attaches and detaches a recording medium 170 such as a magnetic, optical or magneto-optical disk such as a floppy disk, CD-ROM or MO.
Recording and / or reproduction of various types of information on the loaded recording medium 170 are performed under the control of.

Such a computer device 150 is
The PU 151 implements the above-described encoding process in the encoding device 1 and / or the decoding process in the decoding device 3 by executing a program.

First, an encoding process in the computer device 150 will be described. Computer device 150
For example, when the user performs a predetermined operation for executing the encoding program, the input unit 158 supplies a control signal indicating the operation content to the CPU 151. In response, computer device 150 causes CPU 151 to load the encoded program into RAM 153, execute the encoded program, output the encoded transmission symbol obtained through encoding to the outside via communication unit 159, and execute , The processing result or the like is displayed on the display unit 157.

The encoding program is provided, for example, by the recording medium 170,
Under one control, the data may be read directly from the recording medium 170, or the data recorded once on the hard disk may be read. Also, the encoding program is a ROM
152 may be stored in advance. Further, it is assumed that the data to be encoded is recorded on a hard disk here. This data corresponds to the input data D1 described above.

More specifically, the computer device 150
When the encoding program is executed by the CPU 151, C
Under the control of the PU 151, desired data recorded on the hard disk is read out, and convolution operation of the data is performed, for example, at a coding rate of “2/3” as an outer code, thereby obtaining the encoded data described above. Generate encoded data corresponding to D2.

Subsequently, the computer device 150 executes the CP
Under the control of U151, the generated coded data is subjected to pairwise interleaving to generate interleaved data corresponding to the above-described interleaved data D3.

Subsequently, the computer device 150 executes the CP
Under the control of U151, the coding rate of the generated interleaved data is set to “1” as the coding of the inner code.
Is performed to generate encoded data corresponding to the encoded data D4 described above.

Then, the computer device 150
Under the control of U151, the generated coded data is mapped to, for example, a transmission symbol of the 8PSK modulation scheme, and a coded transmission symbol corresponding to the coded transmission symbol D5 described above is generated.

The computer device 150 includes a CPU 151
After the generated encoded transmission symbol is once recorded on a hard disk or the like under the control of, the encoded transmission symbol is read out at a desired timing, output to the outside via the communication unit 159, and if necessary, , The processing result is displayed on the display unit 157. Note that the generated encoded transmission symbol can also be recorded on the recording medium 170 or the like.

As described above, the computer device 150
The encoding process in the encoding device 1 described above can be realized by executing an encoding program.

Next, the decoding process in the computer device 150 will be described. Computer device 150
For example, when the user performs a predetermined operation for executing the decryption program, the input unit 158 supplies a control signal indicating the operation content to the CPU 151. In response, the computer device 150 loads the decryption program into the RAM 153 by the CPU 151, executes the decryption program, receives the decryption program from the outside via the communication unit 159, and records the decryption program on the hard disk or the like corresponding to the above-described received word D6. Decrypts the received word, and, if necessary,
The display unit 157 displays a processing result and the like.

The decoding program, like the encoding program, is provided by, for example, the recording medium 170, and may be directly read from the recording medium 170 under the control of the CPU 151. May be read out once. Further, the decryption program may be stored in the ROM 152 in advance.

More specifically, the computer device 150
When the decryption program is executed by the CPU 151, the CP
Under the control of U151, MAP decoding based on, for example, the BCJR algorithm is performed on the received word read from the hard disk or the received word received via the communication unit 159, thereby performing soft output decoding of the inner code. The external information corresponding to the obtained external information D8 is generated.

Subsequently, the computer device 150 executes the CP
Under the control of U151, the generated external information is deinterleaved to generate prior probability information corresponding to the above-described prior probability information D9.

Subsequently, the computer device 150 executes the CP
Under the control of U151, the generated prior probability information is subjected to MAP decoding based on, for example, the BCJR algorithm to perform soft-output decoding of the outer code and generate external information corresponding to the above-described external information D11 and D12. Then, interleaving is performed on the external information corresponding to the above-described external information D12 to generate prior probability information corresponding to the above-described prior probability information D7.

Then, the computer device 150
Under the control of U151, such a decoding operation is repeatedly performed a predetermined number of times, for example, several to several tens of times, and the soft operation obtained as a result of the predetermined number of decoding operations corresponding to the above-described external information D11 is performed. The hard-output decoded data is output based on the external information of the output.

The computer device 150 includes a CPU 151
Under the control of, the obtained decoded data is recorded on a hard disk or the like, and a processing result or the like is displayed on the display unit 157 as necessary. The obtained decrypted data is stored in the recording medium 17.
It can also be recorded as 0 or the like.

As described above, the computer device 150
The decoding process in the decoding device 3 described above can be realized by executing a decoding program.

As described above, it goes without saying that the present invention can be appropriately changed without departing from the spirit of the present invention.

[0183]

As described in detail above, the encoding apparatus according to the present invention is an encoding apparatus for performing cascade concatenated modulation on input data, First encoding means for performing encoding;
The order of each bit constituting the data consisting of the bit sequence encoded by the encoding means is replaced and rearranged in a symbol unit which is a set of data supplied in one time slot from the first encoding means. Replacement means, second coding means for performing coding which does not end in one time slot on the data supplied from the replacement means, and data coded by the second coding means in a predetermined manner. Mapping means for mapping to a transmission symbol of a modulation scheme.

Therefore, in the encoding apparatus according to the present invention, the permutation means rearranges and rearranges the order of each bit constituting the data consisting of the bit sequence encoded by the first encoding means in symbol units. By performing encoding that does not end in one time slot on the data supplied from the replacement means by the second encoding means, high-performance tandem concatenated modulation can be performed.

The encoding method according to the present invention is a coding method for performing cascade concatenated modulation on input data, wherein a first code for performing coding on input data is provided. Encoding step and the order of each bit constituting the data consisting of the bit sequence encoded in the first encoding step are defined as a set of data encoded in one time slot in the first encoding step. And a second encoding step of performing encoding that does not end in one time slot on the data sorted in the replacing step, And a mapping step of mapping the data encoded in the encoding step to transmission symbols of a predetermined modulation scheme.

Therefore, in the encoding method according to the present invention, in the replacement step, the order of each bit constituting the data consisting of the bit sequence encoded in the first encoding step is replaced in symbol units. In the second encoding step, by performing encoding that does not end in one time slot on the data rearranged in the rearrangement and substitution step, it is possible to perform high-performance tandem concatenated encoding modulation. Make it possible.

Further, the recording medium on which the encoding program according to the present invention is recorded is a recording medium on which a computer-controllable encoding program for performing cascaded encoding modulation on input data is recorded. , The encoding program performs first encoding for the input data.
And the order of each bit constituting the data consisting of the bit sequence encoded in the first encoding step is expressed by the data encoded in one time slot in the first encoding step. A permutation step of permuting and rearranging in units of symbols, a second encoding step of performing encoding that does not end in one time slot on the data rearranged in this permutation step; And a mapping step of mapping the data encoded in the second encoding step to transmission symbols of a predetermined modulation scheme.

Therefore, in the recording medium on which the encoding program according to the present invention is recorded, in the replacement step, the order of each bit constituting the data consisting of the bit sequence encoded in the first encoding step is changed. It is possible to provide an encoding program for performing, in the second encoding step, encoding that does not end in one time slot with respect to the data rearranged and rearranged in the symbol unit and in the substitution step. . Therefore, the apparatus provided with this encoding program can perform high-performance tandem concatenated encoding modulation.

Furthermore, the decoding device according to the present invention
A first encoding unit that encodes the input data; and a second encoding unit that replaces and rearranges the order of each bit that constitutes data including a bit sequence encoded by the first encoding unit. 1 replacement means, second coding means for coding data supplied from the first replacement means, and data encoded by the second coding means in a predetermined modulation scheme. A decoding device for decoding a code subjected to tandem concatenated coding modulation by a coding device having mapping means for mapping to a transmission symbol of
The soft output decoding is performed using external information for each symbol, which is a set of data output in one time slot from the encoding means.

Therefore, the decoding device according to the present invention
When performing soft output decoding, cascaded concatenated coded modulation is performed by using external information for each symbol, which is a set of data encoded by the first encoding means in the encoding device and output in one time slot. It is possible to perform decoding of the obtained code with high performance.

Also, the decoding method according to the present invention comprises a first encoding step of encoding input data,
A first permutation step of permuting and rearranging the order of each bit constituting the data consisting of the bit sequence encoded in the first encoding step, and a permutation in the first permutation step; The encoding method includes a second encoding step of encoding data, and a mapping step of mapping the data encoded by the second encoding step to transmission symbols of a predetermined modulation scheme. A decoding method for decoding a concatenated coded modulated code, wherein soft output decoding is performed using external information for each symbol, which is a set of data coded in one time slot in a first coding step. Do.

Therefore, the decoding method according to the present invention
When soft output decoding is performed, tandem concatenated coding is performed by using external information for each symbol, which is a set of data encoded in the first encoding step of the encoding method and output in one time slot. It is possible to perform decoding of a modulated code with high performance.

Further, the recording medium on which the decoding program according to the present invention is recorded has a first encoding step of encoding the input data, and the encoded data is encoded in the first encoding step. A first permutation step of permuting and rearranging the order of each bit constituting data consisting of the bit sequence,
A second encoding step of encoding the data rearranged in the first substitution step, and converting the data encoded in the second encoding step into transmission symbols of a predetermined modulation scheme. And a mapping step for performing a mapping step. The decoding method comprises the steps of: decoding a code concatenated in tandem concatenated coding modulation by an encoding method including a mapping step; Soft output decoding is performed using external information for each symbol, which is a set of data encoded in one time slot.

Therefore, the recording medium on which the decoding program according to the present invention has been recorded is encoded in the first encoding step of the encoding method to perform the soft output decoding.
It is possible to provide a decoding program that uses external information for each symbol, which is a set of data output in a time slot. Therefore, the apparatus provided with the decoding program can perform decoding of the code subjected to the tandem concatenated coding modulation with high performance.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a communication model to which a data transmission / reception system shown as an embodiment of the present invention is applied.

FIG. 2 is a block diagram illustrating a configuration of an encoding device in the data transmission / reception system.

FIG. 3 is a block diagram illustrating a configuration of a convolutional encoder that encodes an outer code included in the encoding device.

FIG. 4 is a diagram illustrating an operation of an interleaver included in the encoding device.

FIG. 5 is a block diagram illustrating a configuration of an interleaver shown in FIG.

FIG. 6 is a block diagram illustrating a configuration of a convolutional encoder that encodes an inner code included in the encoding device.

FIG. 7 is a diagram illustrating a signal point arrangement based on an 8PSK modulation scheme by a multi-level modulation mapping circuit included in the encoding device.

FIG. 8 is a block diagram illustrating a configuration of a decoding device in the data transmission / reception system.

FIG. 9 is a block diagram illustrating a configuration of a soft-output decoding circuit included in the decoding device that performs soft-output decoding of an inner code.

FIG. 10 is a block diagram illustrating a configuration of a soft-output decoding circuit included in a decoding device that performs soft-output decoding of an outer code.

11 is a block diagram illustrating a configuration of another encoding device different from the encoding device illustrated in FIG.

12 is a block diagram illustrating a configuration of a convolutional encoder that performs encoding of an outer code included in the encoding device illustrated in FIG.

13 is a block diagram illustrating a configuration of an interleaver included in the encoding device illustrated in FIG.

14 is a block diagram illustrating a configuration of a convolutional encoder that encodes an inner code included in the encoding device illustrated in FIG.

FIG. 15 is a diagram illustrating a signal point arrangement based on an 8PSK modulation scheme by a multi-level modulation mapping circuit included in the encoding device illustrated in FIG. 11;

16 is a diagram illustrating a trellis of the convolutional encoder illustrated in FIG.

17 is a diagram illustrating a performance curve in the data transmission / reception system and a performance curve in a system configured using the encoding device illustrated in FIG. 11 and the decoding device illustrated in FIG. 8;

FIG. 18 is a block diagram illustrating a configuration of a computer device.

FIG. 19 is a block diagram illustrating a configuration of a communication model.

FIG. 20 is a block diagram illustrating a configuration of a conventional encoding device.

FIG. 21 is a block diagram illustrating a configuration of a conventional decoding device.

[Explanation of symbols]

Reference Signs List 1 encoding device, 3 decoding device, 10, 30 convolutional encoder, 20, 70 interleaver, 40
Multi-level modulation mapping circuit, 50, 80 soft output decoding circuit, 60 deinterleaver, 90 binarization circuit, 150 computer device, 151 CPU,
170 Recording medium

 ──────────────────────────────────────────────────の Continued on the front page F term (reference) 5J065 AA01 AB01 AC02 AC03 AD10 AE06 AG06 AH02 AH05 AH06 AH21 5K004 AA05 FA06 FD05

Claims (32)

[Claims] 1. An encoding device for performing cascade concatenated modulation on input data, comprising: first encoding means for encoding input data; That replaces the order of each bit constituting the data consisting of the bit sequence encoded by the encoding means in a symbol unit which is a set of data supplied in one time slot from the first encoding means. Means, second encoding means for encoding the data supplied from the replacement means, which does not end in one time slot, and a predetermined modulation of the data encoded by the second encoding means. And a mapping unit for mapping to a transmission symbol of the scheme. 2. The encoding apparatus according to claim 1, wherein each of the first encoding unit and the second encoding unit performs a convolution operation on the input data. 3. The encoding apparatus according to claim 2, wherein at least said second encoding means performs a recursive convolution operation. 4. The encoding apparatus according to claim 1, wherein said mapping means performs modulation by an eight-phase modulation scheme. 5. A coding method for performing tandem concatenated coding modulation on input data, comprising: a first coding step of coding input data; The order of each bit constituting the data consisting of the bit sequence encoded in the encoding step is replaced by a symbol unit which is a set of data encoded in one time slot in the first encoding step. A permutation step of rearranging, a second encoding step of performing encoding that does not end in one time slot on the data rearranged in the permutation step, and a second encoding step of encoding in the second encoding step And a mapping step of mapping the converted data to transmission symbols of a predetermined modulation scheme. 6. The encoding method according to claim 5, wherein in the first encoding step and the second encoding step, a convolution operation is performed on the input data. 7. At least in the second encoding step,
7. The encoding method according to claim 6, wherein a recursive convolution operation is performed. 8. The encoding method according to claim 5, wherein in the mapping step, modulation is performed by an eight-phase modulation scheme. 9. A recording medium on which a computer-controllable encoding program for performing cascade concatenated encoding modulation on input data is recorded, wherein the encoding program encodes the input data A first encoding step of performing encoding, and the order of each bit constituting data consisting of the bit sequence encoded in the first encoding step is changed by one time slot in the first encoding step. A permutation step of permuting and rearranging in a symbol unit, which is a set of data encoded in step (a), and a second code for performing encoding that does not end in one time slot on the data rearranged in the permutation step And a mapping step of mapping the data encoded in the second encoding step to transmission symbols of a predetermined modulation scheme. Recorded recording medium. 10. A first encoding means for encoding input data, and the order of each bit constituting data consisting of a bit sequence encoded by said first encoding means is replaced. First permutation means for rearranging the data, second encoding means for encoding the data supplied from the first substitution means, and data encoded by the second encoding means. And a mapping means for mapping the symbols into transmission symbols of a predetermined modulation scheme. The decoding apparatus decodes a code subjected to cascade concatenated and coded modulation by a coding device comprising: A decoding apparatus for performing soft output decoding using external information for each symbol, which is a set of output data. 11. The first replacement means replaces and rearranges the order of each bit constituting data consisting of a bit sequence encoded by the first encoding means on a symbol-by-symbol basis. The decoding device according to claim 10, wherein: 12. The data processing apparatus according to claim 10, wherein said second encoding means encodes the data supplied from said first substitution means so as not to end in one time slot. The decoding device as described in the above. 13. A first unit which is provided corresponding to the second encoding unit and performs soft output decoding using an input received word and prior probability information for an input information symbol which is a soft input. And a symbol array consisting of a set of data connected in tandem with the first soft output decoding means and rearranged by the first replacement means is encoded by the first encoding means. Reverse permuting means for rearranging input soft-input data so as to return to a symbol array consisting of a set of encoded data; and tandemly provided in the reverse permuting means provided corresponding to the first encoding means. , And performs a soft output decoding using the prior probability information for the soft input code symbol output from the inverse permutation means and the input soft input information bits. Output decryption And stage, based on the same substitution position information and the first replacement means,
A second permutation unit that permutates the order of each bit constituting the data consisting of the bit sequence of the soft input output from the second soft output decoding unit in units of symbols and rearranges them, and The decoding device according to claim 10, wherein the output decoding means inputs the soft input data output from the second replacement means as prior probability information for the information symbol. 14. The apparatus according to claim 13, further comprising a binarizing unit for binarizing the soft-output external information generated by the second soft-output decoding unit and outputting the binarized data as hard-output decoded data. Decoding device. 15. The decoding apparatus according to claim 13, wherein said first soft output decoding means and said second soft output decoding means respectively perform maximum a posteriori probability decoding based on a BCJR algorithm. 16. The decoding apparatus according to claim 13, wherein the prior probability information for the information symbol or the code symbol is represented as a natural logarithm of a probability that can be taken as the information symbol or the code symbol, respectively. 17. The method according to claim 13, wherein the prior probability information for the information symbol or the code symbol is expressed as a natural logarithm of a ratio of a probability of each symbol to a probability of any one symbol. Decoding device. 18. The apparatus according to claim 1, wherein said first encoding means and said second encoding means each perform a convolution operation on input data.
0. The decoding device according to item 0. 19. At least the second encoding means includes:
19. The decoding device according to claim 18, wherein a recursive convolution operation is performed. 20. The decoding apparatus according to claim 10, wherein said mapping means performs modulation by an eight-phase modulation scheme. 21. A first encoding step for encoding input data, and the order of each bit constituting data consisting of a bit sequence encoded in the first encoding step is defined as follows. A first permutation step of permuting and rearranging, a second encoding step of encoding data rearranged in the first permutation step, and encoding by the second encoding step. And a mapping step of mapping the obtained data to transmission symbols of a predetermined modulation scheme. A decoding method characterized by performing soft-output decoding using external information for each symbol, which is a set of data encoded in one time slot. 22. In the first replacing step, the order of each bit constituting data consisting of the bit sequence encoded in the first encoding step is replaced and rearranged in a symbol unit. The decoding method according to claim 21, characterized in that: 23. In the second encoding step, the first encoding step
22. The decoding method according to claim 21, wherein the data rearranged in the replacement step is subjected to encoding that does not end in one time slot. 24. A first apparatus which is provided corresponding to the second encoding step and performs soft output decoding using an input received word and prior probability information for an input information symbol as a soft input. And the symbol arrangement consisting of the data set rearranged in the first replacement step is returned to the symbol arrangement consisting of the data set encoded in the first encoding step. like,
A reverse permutation step of rearranging the soft input data generated in the first soft output decoding step; and a soft permutation apparatus provided corresponding to the first encoding step and rearranged in the reverse permutation step. A second soft output decoding step of performing soft output decoding using prior probability information for the input code symbol and prior probability information for the input soft input information bits, the same as the first replacement step Based on the replacement position information of
A second permutation step of permuting and rearranging the order of each bit constituting the data consisting of the soft input bit sequence generated in the second soft output decoding step in units of symbols, 22. The decoding method according to claim 21, wherein in the soft output decoding step, the soft input data rearranged in the second replacement step is input as prior probability information for the information symbol. 25. The method according to claim 24, further comprising the step of binarizing the soft-output external information generated in the second soft-output decoding step and outputting it as hard-output decoded data. The decoding method described. 26. The decoding method according to claim 24, wherein in the first soft output decoding step and the second soft output decoding step, maximum a posteriori probability decoding is performed based on a BCJR algorithm. 27. The decoding method according to claim 24, wherein the prior probability information for the information symbol or the code symbol is expressed as a natural logarithm of a probability that can be taken as the information symbol or the code symbol, respectively. 28. The method according to claim 24, wherein the prior probability information for the information symbol or the code symbol is expressed as a natural logarithm of a ratio of a probability of each symbol to a probability of any one symbol. Decryption method. 29. The method according to claim 21, wherein in the first encoding step and the second encoding step, a convolution operation is performed on the input data.
The decoding method described. 30. The decoding method according to claim 29, wherein a recursive convolution operation is performed at least in the second encoding step. 31. The decoding method according to claim 21, wherein in the mapping step, modulation is performed by an 8-phase phase modulation method. 32. A first encoding step of encoding input data, and the order of each bit constituting data consisting of a bit sequence encoded in the first encoding step is determined. A first permutation step of permuting and rearranging, a second encoding step of encoding data rearranged in the first permutation step, and encoding by the second encoding step. And a mapping step of mapping the obtained data to transmission symbols of a predetermined modulation scheme. The decoding program performs soft-output decoding using external information for each symbol, which is a set of data encoded in one time slot in the first encoding step. Recording medium in which the program is recorded.