JP4505953B2 - Encoding apparatus and encoding method, and decoding apparatus and decoding method - Google Patents

Description

【００６６】
すなわち、軟出力復号回路４０は、ＭＡＰ復号器４２に対して、受信語Ｄ５（ｙ）と、情報ビットｕが“１”である確率Ｐｒ｛ｕ＝１｝と情報ビットｕが“０”である確率Ｐｒ｛ｕ＝０｝との比の自然対数で表される符号の拘束条件がない事前確率情報Ｄ６（Ｌ（ｕ））とを入力する。
【００６７】
続いて、軟出力復号回路４０は、ＭＡＰ復号器４２によりＭＡＰ復号を行い、次式（１０）で表される事後確率情報Ｄ１５（Ｌ^*（ｕ））を生成する。
【００６８】
【数１０】

【００６９】
すなわち、軟出力復号回路４０は、ＭＡＰ復号器４２によって、受信語Ｄ５（ｙ）を受信した際に情報ビットｕが“１”である確率Ｐｒ｛ｕ＝１｜ｙ｝と、受信語Ｄ５（ｙ）を受信した際に情報ビットｕが“０”である確率Ｐｒ｛ｕ＝０｜ｙ｝との比の自然対数で表される符号の拘束条件に基づく事後確率情報Ｄ１５（Ｌ^*（ｕ））を生成する。なお、この事後確率情報Ｄ１５（Ｌ^*（ｕ））は、ここでは、受信語Ｄ５（ｙ）を受信した際の情報ビットｕの尤度を示すものである。
【００７０】
そして、軟出力復号回路４０は、差分器４３，４４，４５のそれぞれによって、次式（１１）で表されるように、事後確率情報Ｄ１５（Ｌ^*（ｕ））と事前確率情報Ｄ６（Ｌ（ｕ））との差分値である外部情報Ｄ７（Ｌ_e（ｕ））を求める。
【００７１】
【数１１】

【００７２】
軟出力復号回路４０は、このようにして外部情報Ｄ７を生成し、この外部情報Ｄ７を後段のデインターリーバ５０に軟出力として出力する。なお、この外部情報Ｄ７は、符号化装置１におけるインターリーバ２０によりインターリーブされたインターリーブデータＤ３に対応するものである。
【００７３】
デインターリーバ５０は、符号化装置１におけるインターリーバ２０によりインターリーブされたインターリーブデータＤ３のビット配列を、それぞれ、元の符号化データＤ２のビット配列に戻すように、軟出力復号回路４０から供給された軟入力の外部情報Ｄ７にデインターリーブを施す。デインターリーバ５０は、デインターリーブして得られたデータＤ８を後段のレート変換回路７０に供給する。
【００７４】
インターリーバ６０は、レート変換回路８０から供給されたデータＤ１２に対して、符号化装置１におけるインターリーバ２０と同一の置換位置情報に基づいたインターリーブを施す。インターリーバ６０は、インターリーブして得られたデータを軟出力復号回路４０における情報ビットに対する事前確率情報Ｄ６として出力する。
【００７５】
レート変換回路７０は、軟出力復号回路４０と軟出力復号回路９０との動作速度の違いを吸収するために、デインターリーバ５０から供給されたデータＤ８のクロックレートを変換する。具体的には、レート変換回路７０は、図示しないメモリから構成され、例えば軟出力復号回路４０の動作速度が軟出力復号回路９０の動作速度の４倍であった場合には、入力したデータＤ８をメモリに保持することによって、クロックレートを１／４倍にするといったように、入力したデータＤ８を軟出力復号回路４０と軟出力復号回路９０との動作速度の違いに応じてメモリに保持することによって、クロックレートを変換する。レート変換回路７０は、クロックレートの変換後のデータを後段の軟出力復号回路９０における符号ビットに対する事前確率情報Ｄ９として出力する。
【００７６】
レート変換回路８０は、レート変換回路７０と同様に、軟出力復号回路４０と軟出力復号回路９０との動作速度の違いを吸収するためのものであり、軟出力復号回路９０から供給された軟入力である符号ビットに対する外部情報Ｄ１１のクロックレートを変換する。レート変換回路８０は、クロックレートの変換後のデータＤ１２を後段のインターリーバ６０に供給する。
【００７７】
軟出力復号回路９０は、符号化装置１におけるパリティ検査符号化器１０に対応して備えられるものである。軟出力復号回路９０は、データ変換回路７０から出力された３ビットからなる軟入力の符号ビットに対する事前確率情報Ｄ９を入力するとともに、図示しないが、値が“０”である２ビットの情報ビットに対する事前確率情報を入力し、これらの事前確率情報を用いてＭＡＰ復号を行い、外符号、すなわち、符号化装置１におけるパリティ検査符号化器１０により符号化された符号の軟出力復号を行う。実際には、軟出力復号回路９０は、次のような動作を行うことによって、ＭＡＰ復号を行う。ここでは、説明の簡略化のため、２元符号を例として説明する。すなわち、軟出力復号回路９０は、符号化装置１におけるアキュムレータ３０による符号から与えられる外部情報を事前確率情報とし、パリティ検査符号毎に事後確率情報を合計３ビットの各符号語シンボルに対して算出する。
【００７８】
ここで、軟出力復号回路９０は、事前確率情報Ｄ９を対数尤度表記して対数尤度の形式で扱う場合には、図８に示すように、演算手段である３つの演算回路９１，９２，９３と、２つの加算器９４，９５とを有するものとして実現することができる。なお、演算回路９１，９２，９３は、それぞれ、「Robert G. Gallager, “Low-density parity-check codes”, MIT Press, 1963」に記載されている演算を行うものであり、演算子を“＄”と表すものとすると、変数Ａ，Ｂ∈Ｒ→Ｒに対して、次式（１２）及び次式（１３）のように定義される演算を行うものである。なお、次式（１２）及び次式（１３）におけるｌｏｇは、ネピヤの数ｅを底とする自然対数を示している。
【００７９】
【数１２】

【００８０】
【数１３】

【００８１】
演算回路９１は、３ビットの事前確率情報Ｄ９のうち、２ビット目の事前確率情報Ｄ９₂と、３ビット目の事前確率情報Ｄ９₃とを用いて、演算子“＄”で表される演算を行い、得られた結果を加算器９４に供給するとともに、３ビットの符号ビットに対する外部情報Ｄ１１のうちの１ビット目の外部情報Ｄ１１₁として、レート変換回路８０に軟出力として供給する。
【００８２】
演算回路９２は、３ビットの事前確率情報Ｄ９のうち、１ビット目の事前確率情報Ｄ９₁と、３ビット目の事前確率情報Ｄ９₃とを用いて、演算子“＄”で表される演算を行い、得られた結果を加算器９５に供給するとともに、３ビットの符号ビットに対する外部情報Ｄ１１のうちの２ビット目の外部情報Ｄ１１₂として、レート変換回路８０に軟出力として供給する。
【００８３】
演算回路９３は、３ビットの事前確率情報Ｄ９のうち、１ビット目の事前確率情報Ｄ９₁と、２ビット目の事前確率情報Ｄ９₂とを用いて、演算子“＄”で表される演算を行い、得られた結果を３ビットの符号ビットに対する外部情報Ｄ１１のうちの３ビット目の外部情報Ｄ１１₃として、レート変換回路８０に軟出力として供給する。
【００８４】
加算器９４は、図示しない値が“０”である情報ビットに対する事前確率情報と、事前確率情報Ｄ９₁と、演算回路９１から供給される外部情報Ｄ１１₁とを加算し、得られた結果を２ビットの情報ビットに対する外部情報Ｄ１０のうちの１ビット目の外部情報Ｄ１０₁として、後段の２値化回路１００に軟出力として供給する。
【００８５】
加算器９５は、図示しない値が“０”である情報ビットに対する事前確率情報と、事前確率情報Ｄ９₂と、演算回路９２から供給される外部情報Ｄ１１₂とを加算し、得られた結果を２ビットの情報ビットに対する外部情報Ｄ１０のうちの２ビット目の外部情報Ｄ１０₂として、後段の２値化回路１００に軟出力として供給する。
【００８６】
このような軟出力復号回路９０は、図示しない値が“０”である情報ビットに対する事前確率情報と、レート変換回路７０から供給された軟入力の事前確率情報Ｄ９とを入力し、これらの事前確率情報を用いてＭＡＰ復号を行うことによって、符号の拘束条件により求められる外部情報Ｄ１０，Ｄ１１を生成し、外部情報Ｄ１０を２値化回路１００に軟出力として供給するとともに、外部情報Ｄ１１をレート変換回路８０に軟出力として供給する。
【００８７】
すなわち、軟出力復号回路９０は、生成する符号ビットに対する外部情報の各ビットとして、レート変換回路７０から供給された軟入力の事前確率情報のうち、自己のビットに対応する入力以外のビットとの間で演算子“＄”で表される演算を行い、生成する情報ビットに対する外部情報として、レート変換回路７０から供給された軟入力の事前確率情報のうち、自己のビットに対応する入力以外のビットとの間で行われた演算子“＄”で表される演算の結果と、自己のビットに対応する入力と、値が“０”である情報ビットに対する事前確率情報とを加算する。換言すれば、外符号の軟出力復号を行う軟出力復号回路は、情報ビットに対する事前確率情報を“ＡＰＰ”とし、符号ビットに対する事前確率情報を“Ｒ_k”とすると、符号化装置１においてパリティを付加する単位に応じて、次式（１４）に示す演算を行い、符号ビットに対する外部情報（ＥＸ）を生成し、次式（１５）に示す演算を行い、情報ビットに対する外部情報（ＤＥＣ）を生成する。
【００８８】
【数１４】

【００８９】
【数１５】

【００９０】
ところで、上述した演算子“＄”については、次式（１６）に示す定理が成立する。ただし、次式（１６）における関数ｆは、正数ｘを変数として、次式（１７）で表される。
【００９１】
【数１６】

【００９２】
【数１７】

【００９３】
なお、上式（１６）における“ｓｇｎ”は、変数Ａ_iの符号であり、“｜Ａ_i｜”は、変数Ａ_iの絶対値を示している。
【００９４】
このように、演算子“＄”で表される演算は、関数ｆによる変換と加算とにより実現することができる。ここで、関数ｆは、図９に示すように、第１象限で与えられ、変数ｘの増加にともない０に漸近する減少関数であり、変数ｘとの関係を例えばＲＯＭ等にテーブルとして予め記憶させておいたり、変数ｘとの関係をいわゆる線形近似又は閾値近似等により近似するといったように、各種方法により実装することができる。また、関数ｆは、変数Ａ_iを符号と絶対値との組み合わせ（signed magnitude形式）で例えばＲＡＭ（Random Access Memory）等に保持することによって、計算量の少ないより簡便な実装とすることも可能である。
【００９５】
このことから、演算回路９１，９２，９３は、それぞれ、上述した関数ｆと変数ｘとの関係を、図示しないＲＯＭに記憶されたテーブルを参照することにより求め、上式（１６）に示した演算を行うものであってもよく、若しくは、関数ｆと変数ｘとの関係を、線形近似又は閾値近似等により近似する構成であってもよい。また、演算回路９１，９２，９３は、それぞれ、図示しないＲＡＭに保持された関数ｆにおける変数Ａ_iの符号と絶対値との組み合わせを用いて、上式（１６）に示した演算を行うものであってもよい。
【００９６】
２値化回路１００は、軟出力復号回路９０から供給された外部情報Ｄ１０を２値化し、硬出力（hard-output）の復号データＤ１３として出力する。
【００９７】
このような復号装置３は、符号化装置１におけるアキュムレータ３０及びパリティ検査符号化器１０のそれぞれに対応する軟出力復号回路４０，９０を備えることによって、復号複雑度が高い符号を複雑度の小さい要素に分解し、軟出力復号回路４０，９０の間の相互作用により特性を逐次的に向上させることができる。復号装置３は、受信値Ｄ５を入力すると、軟出力復号回路４０乃至軟出力復号回路９０の復号動作を例えば数回乃至数十回といった所定の回数だけ反復して行い、所定の回数の復号動作の結果得られた軟出力の外部情報Ｄ１０に基づいて、復号データＤ１３を出力する。
【００９８】
このように、復号装置３は、符号化装置１により符号化されたＰＡ符号を繰り返し復号により高精度に復号することができる。
【００９９】
つぎに、第２の実施の形態として示すデータ送受信システムについて図１０乃至図１５を用いて説明する。
【０１００】
このデータ送受信システムは、上述した符号化装置１の代わりに、図１０に示す符号化装置１’を備え、この符号化装置１’により符号化された符号を後述する復号装置３’により復号するものである。このデータ送受信システムにおいて、符号化装置１’は、上述したＰＡ符号による符号化をさらに改良し、パリティを付加する情報の単位を任意の分布にしたがって変化させるものである。
【０１０１】
なお、図１０に示す符号化装置１’は、基本構成を図２に示した符号化装置１と同様とし、設定器１１０を備えたことに特徴を有している。したがって、先に図２に示した符号化装置１と同様の構成については同一符号を付して詳細な説明を省略する。
【０１０２】
符号化装置１’は、図１０に示すように、上述したインターリーバ２０と、アキュムレータ３０との他に、パリティ検査符号化器１０’と、パリティ検査符号化器１０’においてパリティを付加する情報の単位の分布を設定する設定手段である設定器１１０とを備える。
【０１０３】
パリティ検査符号化器１０’は、上述したパリティ検査符号化器１０と同様に、入力したデータに対して所定のビット単位で１ビットのパリティを付加する。具体的には、パリティ検査符号化器１０’は、入力データＤ１を入力すると、設定器１１０から供給される制御信号Ｓに基づいて、入力データＤ１に対して所定のビット単位で１ビットのパリティを付加し、符号化データＤ２として後段のインターリーバ２０に出力する。ここで、パリティを付加する単位は、設定器１１０から供給される制御信号Ｓに応じて変化する。この単位については、後に詳述する。
【０１０４】
設定器１１０は、パリティ検査符号化器１０’においてパリティを付加する単位の分布を設定し、設定内容を示す制御信号Ｓをパリティ検査符号化器１０’に供給する。設定器１１０は、具体的には、符号化データＤ２のビット総数に対して、入力データＤ１のｉビット単位で１ビットのパリティを付加する比率をλ_iとすると、次式（１８）及び次式（１９）を満足するように、入力データＤ１に対してパリティを付加する単位の分布を設定する。
【０１０５】
【数１８】

【０１０６】
【数１９】

【０１０７】
より具体的に説明するために、パリティ検査符号化器１０’により符号化率Ｒが“４／５”の符号化を行う場合を考える。ここで、例えば図１１（Ａ）に示すように、パリティ検査符号化器１０’により生成される符号化データＤ２の総ビット数を５００００ビットとすると、入力データＤ１の総ビット数は、符号化率Ｒが“４／５”であることから、同図（Ｂ）に示すように、４００００ビットとなる。
【０１０８】
このとき、パリティ検査符号化器１０’は、ｉ＝３ビット単位で１ビットのパリティを付加する符号化と、ｉ＝５ビット単位で１ビットのパリティを付加する符号化とを行うものとすると、同図（Ａ）に示すように、５００００ビットの符号化データＤ２のうち、２／５のビット、すなわち、２００００ビットを３ビット単位でパリティ検査符号化して生成するとともに、残りの３／５のビット、すなわち、３００００ビットを５ビット単位でパリティ検査符号化して生成すればよい。
【０１０９】
ここで、同図（Ｂ）に示すように、符号化データＤ２のうちの２００００ビットを３ビット単位でパリティ検査符号化して生成するには、入力データＤ１のうちの２００００×３／（３＋１）＝１５０００ビットを必要とし、符号化データＤ２のうちの３００００ビットを５ビット単位でパリティ検査符号化して生成するには、入力データＤ１のうちの３００００×５／（５＋１）＝２５０００ビットを必要とすることになる。
【０１１０】
したがって、設定器１１０は、パリティ検査符号化器１０’に対して、４００００ビットの入力データＤ１のうち、１５０００ビットを３ビット単位でパリティ検査符号化するとともに、２５０００ビットを５ビット単位でパリティ検査符号化する旨を示す制御信号Ｓを供給する。
【０１１１】
このように、設定器１１０は、入力データＤ１の総ビット数、パリティ検査符号化器１０’で行わせるべき符号化の符号化率及びパリティを付加する単位に応じて、入力データＤ１に対してパリティを付加する単位の分布を設定し、その設定内容を示す制御信号Ｓをパリティ検査符号化器１０’に供給する。
【０１１２】
なお、パリティを付加する単位の分布は、入力データＤ１の総ビットに対して任意であってよく、例えば、図１１の例の場合には、入力データＤ１の最初の１５０００ビットを３ビット単位でパリティ検査符号化し、残りの２５０００ビットを５ビット単位でパリティ検査符号化してもよく、その他の組み合わせであってもよい。
【０１１３】
このような符号化装置１’は、パリティ検査符号化器１０’により外符号の符号化として符号化率が任意の“Ｒ（＜１）”のパリティ検査符号化を行い、アキュムレータ３０により内符号の符号化として符号化率が“１”の再帰的畳み込み演算を行うことによって、全体として、符号化率が“Ｒ×１＝Ｒ”の符号による縦列連接符号化を行う。この符号化装置１により符号化されたデータは、図示しない変調器により所定の変調方式に基づいて信号点のマッピングが行われ、無記憶通信路２を介して受信装置に出力される。
【０１１４】
このように、符号化装置１’は、パリティ検査符号化器１０’においてパリティを付加する単位を任意の分布にしたがって変化させることによって、第１の実施の形態として示したＰＡ符号であれば符号化率に応じて一意に決定されるパリティ付加の単位を、入力データＤ１の任意の単位毎に異なるものとすることができることから、符号化率を“１”に近い所望の値とすることができ、この所望の高い符号化率の下に、より高性能の符号化を行うことができる。設定器１１０により設定されるパリティ付加の単位の分布を決定する方法としては、種々のものが考えられ、例えば、通常のＰＡ符号の場合からパリティ付加の単位の分布を変化させていき、最適な性能が得られる分布を探索するようにしてもよい。
【０１１５】
一方、復号装置３’は、図１２に示すように、いわゆる繰り返し復号を行うものとして構成される。なお、ここでは、説明を簡略化するために、符号化装置１’におけるパリティ検査符号化器１０’によって、ｉ＝３ビット単位で１ビットのパリティを付加する符号化と、ｉ＝５ビット単位で１ビットのパリティを付加する符号化とを行い、符号化率が“４／５”の符号化を行うものに対応するものを示す。
【０１１６】
また、同図に示す復号装置３’は、基本構成を図６に示した復号装置３と同様とし、符号化装置１’におけるパリティ検査符号化器１０’によるパリティを付加する単位に応じた複数の軟出力復号回路を備えたことに特徴を有している。したがって、先に図６に示した復号装置３と同様の構成については同一符号を付して詳細な説明を省略する。
【０１１７】
復号装置３’は、図１２に示すように、上述した軟出力復号回路４０と、デインターリーバ５０と、インターリーバ６０と、２値化回路１００との他に、クロックレートの変換等を行う第１のレート変換手段及び分配手段であるレート変換回路７０’と、同じくクロックレートの変換を行う第２のレート変換手段であるレート変換回路８０’と、パリティ検査符号化器１０’によるパリティを付加する単位に応じた軟出力復号を行う第２の軟出力復号手段である２つの軟出力復号回路９０₁，９０₂と、これらの軟出力復号回路９０₁，９０₂から供給されたデータを切り換えて出力するための切換スイッチ１２０とを備える。この復号装置３’は、無記憶通信路２上で発生したノイズの影響によりアナログ値をとり軟入力とされる受信値Ｄ５から符号化装置１’における入力データＤ１を推定し、復号データＤ２３として出力する。
【０１１８】
レート変換回路７０’は、軟出力復号回路４０と軟出力復号回路９０₁，９０₂との動作速度の違いを吸収するために、デインターリーバ５０から供給されたデータＤ８のクロックレートを変換する。また、レート変換回路７０’は、クロックレートの変換後のデータを後段の軟出力復号器９０₁，９０₂に分配する機能も併せて備える。
【０１１９】
具体的には、レート変換回路７０’は、図１３に示すように、クロックレートを変換させるためにデータＤ８を保持するメモリ７１と、後述する切換スイッチ７３の動作を制御する制御部７２と、メモリ７１から供給されたクロックレートが変換されたデータを選択する切換スイッチ７３と、この切換スイッチ７３により選択されたデータをラッチする１０個のラッチ７４₁，７４₂，７４₃，７４₄，７４₅，７４₆，７４₇，７４₈，７４₉，７４₁₀とを有する。
【０１２０】
このようなレート変換回路７０’は、例えば軟出力復号回路４０の動作速度が軟出力復号回路９０₁，９０₂の動作速度の４倍であった場合には、入力したデータＤ８をメモリ７１に保持することによって、クロックレートを１／４倍にするといったように、入力したデータＤ８を軟出力復号回路４０と軟出力復号回路９０₁，９０₂との動作速度の違いに応じてメモリ７１に保持することによって、クロックレートを変換する。続いて、レート変換回路７０’は、制御部７２によって、メモリ７１に保持されているデータが、符号化装置１’におけるパリティ検査符号化器１０’によりｉビット単位でパリティが付加されて生成されたｉ＋１個のビットのうち、どのビットに相当するかを判別し、この制御部７２の制御の下に切換スイッチ７３を動作させ、メモリ７１から供給されたデータを各ラッチ７４₁，７４₂，７４₃，７４₄，７４₅，７４₆，７４₇，７４₈，７４₉，７４₁₀に分配する。そして、レート変換回路７０’は、パリティ検査符号化器１０’におけるパリティを付加する単位がｉ＝３の場合には、ラッチ７４₁，７４₂，７４₃，７４₄のそれぞれによって、４ビットのデータを１ビットずつラッチし、各ビットを後段の軟出力復号回路９０₁における符号ビットに対する事前確率情報Ｄ１６₁，Ｄ１６₂，Ｄ１６₃，Ｄ１６₄として出力する。また、レート変換回路７０’は、パリティ検査符号化器１０’におけるパリティを付加する単位がｉ＝５の場合には、ラッチ７４₅，７４₆，７４₇，７４₈，７４₉，７４₁₀のそれぞれによって、６ビットのデータを１ビットずつラッチし、各ビットを後段の軟出力復号回路９０₂における符号ビットに対する事前確率情報Ｄ１７₁，Ｄ１７₂，Ｄ１７₃，Ｄ１７₄，Ｄ１７₅，Ｄ１７₆として出力する。
【０１２１】
レート変換回路８０’は、レート変換回路７０’と同様に、軟出力復号回路４０と軟出力復号回路９０₁，９０₂との動作速度の違いを吸収するためのものであり、軟出力復号回路９０₁から供給された軟入力である符号ビットに対する外部情報Ｄ１９又は軟出力復号回路９０₂から供給された軟入力である符号ビットに対する外部情報Ｄ２１のクロックレートを変換する。レート変換回路８０’は、クロックレートの変換後のデータＤ１２を後段のインターリーバ６０に供給する。
【０１２２】
軟出力復号回路９０₁は、符号化装置１におけるパリティ検査符号化器１０’に対応して備えられるものであり、ｉ＝３ビット単位で１ビットのパリティを付加してパリティ検査符号化された符号を復号するものである。軟出力復号回路９０₁は、データ変換回路７０’から出力された軟入力の符号ビットに対する事前確率情報Ｄ１６を入力するとともに、図示しないが、値が“０”である情報ビットに対する事前確率情報を入力し、これらの事前確率情報を用いてＭＡＰ復号を行い、外符号の軟出力復号を行う。
【０１２３】
ここで、軟出力復号回路９０₁は、事前確率情報Ｄ１６を対数尤度表記して対数尤度の形式で扱う場合には、図１４に示すように、演算手段である４つの演算回路９１₁，９２₁，９３₁，９４₁と、３つの加算器９５₁，９６₁，９７₁とを有するものとして実現することができる。なお、演算回路９１₁，９２₁，９３₁，９４₁は、それぞれ、上式（１２）及び上式（１３）のように定義される演算を行うものである。
【０１２４】
演算回路９１₁は、４ビットの事前確率情報Ｄ１６のうち、２ビット目の事前確率情報Ｄ１６₂と、３ビット目の事前確率情報Ｄ１６₃と、４ビット目の事前確率情報Ｄ１６₄とを用いて、演算子“＄”で表される演算を行い、得られた結果を加算器９５₁に供給するとともに、４ビットの符号ビットに対する外部情報Ｄ１９のうちの１ビット目の外部情報Ｄ１９₁として、レート変換回路８０’に軟出力として供給する。
【０１２５】
演算回路９２₁は、４ビットの事前確率情報Ｄ１６のうち、１ビット目の事前確率情報Ｄ１６₁と、３ビット目の事前確率情報Ｄ１６₃と、４ビット目の事前確率情報Ｄ１６₄とを用いて、演算子“＄”で表される演算を行い、得られた結果を加算器９６₁に供給するとともに、４ビットの符号ビットに対する外部情報Ｄ１９のうちの２ビット目の外部情報Ｄ１９₂として、レート変換回路８０’に軟出力として供給する。
【０１２６】
演算回路９３₁は、４ビットの事前確率情報Ｄ１６のうち、１ビット目の事前確率情報Ｄ１６₁と、２ビット目の事前確率情報Ｄ１６₂と、４ビット目の事前確率情報Ｄ１６₄とを用いて、演算子“＄”で表される演算を行い、得られた結果を加算器９７₁に供給するとともに、４ビットの符号ビットに対する外部情報Ｄ１９のうちの３ビット目の外部情報Ｄ１９₃として、レート変換回路８０’に軟出力として供給する。
【０１２７】
演算回路９４₁は、４ビットの事前確率情報Ｄ１６のうち、１ビット目の事前確率情報Ｄ１６₁と、２ビット目の事前確率情報Ｄ１６₂と、３ビット目の事前確率情報Ｄ１６₃とを用いて、演算子“＄”で表される演算を行い、得られた結果を４ビットの符号ビットに対する外部情報Ｄ１９のうちの４ビット目の外部情報Ｄ１９₄として、レート変換回路８０’に軟出力として供給する。
【０１２８】
加算器９５₁は、図示しない値が“０”である情報ビットに対する事前確率情報と、事前確率情報Ｄ１６₁と、演算回路９１₁から供給される外部情報Ｄ１９₁とを加算し、得られた結果を３ビットの情報ビットに対する外部情報Ｄ１８のうちの１ビット目の外部情報Ｄ１８₁として、被選択端子ａに軟出力として供給する。
【０１２９】
加算器９６₁は、図示しない値が“０”である情報ビットに対する事前確率情報と、事前確率情報Ｄ１６₂と、演算回路９２₁から供給される外部情報Ｄ１９₂とを加算し、得られた結果を３ビットの情報ビットに対する外部情報Ｄ１８のうちの２ビット目の外部情報Ｄ１８₂として、被選択端子ａに軟出力として供給する。
【０１３０】
このような軟出力復号回路９０₁は、図示しない値が“０”である情報ビットに対する事前確率情報と、レート変換回路７０’から供給された軟入力の事前確率情報Ｄ１６とを入力し、これらの事前確率情報を用いてＭＡＰ復号を行うことによって、符号の拘束条件により求められる外部情報Ｄ１８，Ｄ１９を生成し、外部情報Ｄ１８を被選択端子ａに軟出力として供給するとともに、外部情報Ｄ１９をレート変換回路８０’に軟出力として供給する。
【０１３１】
軟出力復号回路９０₂は、符号化装置１におけるパリティ検査符号化器１０’に対応して備えられるものであり、ｉ＝５ビット単位で１ビットのパリティを付加してパリティ検査符号化された符号を復号するものである。軟出力復号回路９０₂は、データ変換回路７０’から出力された軟入力の符号ビットに対する事前確率情報Ｄ１７を入力するとともに、図示しないが、値が“０”である情報ビットに対する事前確率情報を入力し、これらの事前確率情報を用いてＭＡＰ復号を行い、外符号の軟出力復号を行う。
【０１３２】
ここで、軟出力復号回路９０₂は、事前確率情報Ｄ１７を対数尤度表記して対数尤度の形式で扱う場合には、図１５に示すように、演算手段である６つの演算回路９１₂，９２₂，９３₂，９４₂，９５₂，９６₂と、５つの加算器９７₁，９８₁，９９₁，１００₁，１０１₁とを有するものとして実現することができる。なお、演算回路９１₂，９２₂，９３₂，９４₂，９５₂，９６₂は、それぞれ、上式（１２）及び上式（１３）のように定義される演算を行うものである。
【０１３３】
演算回路９１₂は、６ビットの事前確率情報Ｄ１７のうち、２ビット目の事前確率情報Ｄ１７₂と、３ビット目の事前確率情報Ｄ１７₃と、４ビット目の事前確率情報Ｄ１７₄と、５ビット目の事前確率情報Ｄ１７₅と、６ビット目の事前確率情報Ｄ１７₆とを用いて、演算子“＄”で表される演算を行い、得られた結果を加算器９７₂に供給するとともに、６ビットの符号ビットに対する外部情報Ｄ２１のうちの１ビット目の外部情報Ｄ２１₁として、レート変換回路８０’に軟出力として供給する。
【０１３４】
演算回路９２₂は、６ビットの事前確率情報Ｄ１７のうち、１ビット目の事前確率情報Ｄ１７₁と、３ビット目の事前確率情報Ｄ１７₃と、４ビット目の事前確率情報Ｄ１７₄と、５ビット目の事前確率情報Ｄ１７₅と、６ビット目の事前確率情報Ｄ１７₆とを用いて、演算子“＄”で表される演算を行い、得られた結果を加算器９８₂に供給するとともに、６ビットの符号ビットに対する外部情報Ｄ２１のうちの２ビット目の外部情報Ｄ２１₂として、レート変換回路８０’に軟出力として供給する。
【０１３５】
演算回路９３₂は、６ビットの事前確率情報Ｄ１７のうち、１ビット目の事前確率情報Ｄ１７₁と、２ビット目の事前確率情報Ｄ１７₂と、４ビット目の事前確率情報Ｄ１７₄と、５ビット目の事前確率情報Ｄ１７₅と、６ビット目の事前確率情報Ｄ１７₆とを用いて、演算子“＄”で表される演算を行い、得られた結果を加算器９９₂に供給するとともに、６ビットの符号ビットに対する外部情報Ｄ２１のうちの３ビット目の外部情報Ｄ２１₃として、レート変換回路８０’に軟出力として供給する。
【０１３６】
演算回路９４₂は、６ビットの事前確率情報Ｄ１７のうち、１ビット目の事前確率情報Ｄ１７₁と、２ビット目の事前確率情報Ｄ１７₂と、３ビット目の事前確率情報Ｄ１７₃と、５ビット目の事前確率情報Ｄ１７₅と、６ビット目の事前確率情報Ｄ１７₆とを用いて、演算子“＄”で表される演算を行い、得られた結果を加算器１００₂に供給するとともに、６ビットの符号ビットに対する外部情報Ｄ２１のうちの４ビット目の外部情報Ｄ２１₄として、レート変換回路８０’に軟出力として供給する。
【０１３７】
演算回路９５₂は、６ビットの事前確率情報Ｄ１７のうち、１ビット目の事前確率情報Ｄ１７₁と、２ビット目の事前確率情報Ｄ１７₂と、３ビット目の事前確率情報Ｄ１７₃と、４ビット目の事前確率情報Ｄ１７₄と、６ビット目の事前確率情報Ｄ１７₆とを用いて、演算子“＄”で表される演算を行い、得られた結果を加算器１０１₂に供給するとともに、６ビットの符号ビットに対する外部情報Ｄ２１のうちの５ビット目の外部情報Ｄ２１₅として、レート変換回路８０’に軟出力として供給する。
【０１３８】
演算回路９６₂は、６ビットの事前確率情報Ｄ１７のうち、１ビット目の事前確率情報Ｄ１７₁と、２ビット目の事前確率情報Ｄ１７₂と、３ビット目の事前確率情報Ｄ１７₃と、４ビット目の事前確率情報Ｄ１７₄と、５ビット目の事前確率情報Ｄ１７₅とを用いて、演算子“＄”で表される演算を行い、得られた結果を６ビットの符号ビットに対する外部情報Ｄ２１のうちの６ビット目の外部情報Ｄ２１₆として、レート変換回路８０’に軟出力として供給する。
【０１３９】
加算器９７₂は、図示しない値が“０”である情報ビットに対する事前確率情報と、事前確率情報Ｄ１７₁と、演算回路９１₂から供給される外部情報Ｄ２１₁とを加算し、得られた結果を５ビットの情報ビットに対する外部情報Ｄ２０のうちの１ビット目の外部情報Ｄ２０₁として、被選択端子ｂに軟出力として供給する。
【０１４０】
加算器９８₂は、図示しない値が“０”である情報ビットに対する事前確率情報と、事前確率情報Ｄ１７₂と、演算回路９２₂から供給される外部情報Ｄ２１₂とを加算し、得られた結果を５ビットの情報ビットに対する外部情報Ｄ２０のうちの２ビット目の外部情報Ｄ２０₂として、被選択端子ｂに軟出力として供給する。
【０１４１】
加算器９９₂は、図示しない値が“０”である情報ビットに対する事前確率情報と、事前確率情報Ｄ１７₃と、演算回路９３₂から供給される外部情報Ｄ２１₃とを加算し、得られた結果を５ビットの情報ビットに対する外部情報Ｄ２０のうちの３ビット目の外部情報Ｄ２０₃として、被選択端子ｂに軟出力として供給する。
【０１４２】
加算器１００₂は、図示しない値が“０”である情報ビットに対する事前確率情報と、事前確率情報Ｄ１７₄と、演算回路９４₂から供給される外部情報Ｄ２１₄とを加算し、得られた結果を５ビットの情報ビットに対する外部情報Ｄ２０のうちの４ビット目の外部情報Ｄ２０₄として、被選択端子ｂに軟出力として供給する。
【０１４３】
加算器１０１₂は、図示しない値が“０”である情報ビットに対する事前確率情報と、事前確率情報Ｄ１７₅と、演算回路９５₂から供給される外部情報Ｄ２１₅とを加算し、得られた結果を５ビットの情報ビットに対する外部情報Ｄ２０のうちの５ビット目の外部情報Ｄ２０₅として、被選択端子ｂに軟出力として供給する。
【０１４４】
このような軟出力復号回路９０₂は、図示しない値が“０”である情報ビットに対する事前確率情報と、レート変換回路７０’から供給された軟入力の事前確率情報Ｄ１７とを入力し、これらの事前確率情報を用いてＭＡＰ復号を行うことによって、符号の拘束条件により求められる外部情報Ｄ２０，Ｄ２１を生成し、外部情報Ｄ２０を被選択端子ｂに軟出力として供給するとともに、外部情報Ｄ２１をレート変換回路８０’に軟出力として供給する。
【０１４５】
切換スイッチ１２０は、図示しない制御部の制御の下に動作し、軟出力復号回路９０₁から出力された外部情報Ｄ１８に基づいて復号データＤ２３を出力する場合には、被選択端子ａと接続し、外部情報Ｄ１８を外部情報Ｄ２２として２値化回路１００に供給する。また、切換スイッチ１２０は、軟出力復号回路９０₂から出力された外部情報Ｄ２０に基づいて復号データＤ２３を出力する場合には、被選択端子ｂと接続し、外部情報Ｄ２０を外部情報Ｄ２２として２値化回路１００に供給する。
【０１４６】
このような復号装置３’は、受信値Ｄ５を入力すると、軟出力復号回路４０乃至軟出力復号回路９０₁，９０₂の復号動作を例えば数回乃至数十回といった所定の回数だけ反復して行い、所定の回数の復号動作の結果得られた軟出力の外部情報Ｄ２２に基づいて、復号データＤ２３を出力する。
【０１４７】
このように、復号装置３’は、パリティを付加する単位が変化されたパリティ検査符号化器１０’による符号を復号することができ、符号化装置１’により符号化された符号を繰り返し復号により高精度に復号することができる。
【０１４８】
以上説明したように、符号化装置と復号装置とを用いて構成されるデータ送受信システムは、符号化装置において、パリティ検査符号化器によるパリティ検査符号化を行うことによって、ｋ／（ｋ＋１）で表される所望の高い符号化率の下に、高性能の符号化を行うことができ、復号装置において、パリティ検査符号化器による符号の復号を行うことができる。
【０１４９】
また、データ送受信システムは、符号化装置において、パリティ検査符号化器におけるパリティ付加の単位を任意の分布にしたがって変化させることによって、“１”に近い所望の高い符号化率の下に、より高性能の符号化を行うことができ、復号装置において、パリティ検査符号化器におけるパリティ付加の単位に応じた復号を行うことができる。
【０１５０】
すなわち、これらの符号化装置と復号装置とを用いて構成されるデータ送受信システムは、高性能の符号化及び復号システムを実現するものであり、ユーザに高い信頼性を提供することができるものである。
【０１５１】
なお、本発明は、上述した実施の形態に限定されるものではなく、例えば、符号化装置におけるアキュムレータとしては、図１６に示すように、２つの排他的論理和回路３１₁’，３１₂’と、２つのシフトレジスタ３２₁’，３２₂’とを有するアキュムレータ３０’といったように、ステート数が“２”以外のものであってもよい。
【０１５２】
また、上述した実施の形態では、符号化装置において、内符号の要素符号化器としてアキュムレータを備えるものとして説明したが、本発明は、必ずしもアキュムレータである必要はなく、任意の符号化を行う符号化器であっても適用可能である。
【０１５３】
さらに、上述した実施の形態では、符号化装置において、外符号の符号化を行う要素符号化器としてパリティ検査符号化器を備えるものとして説明したが、パリティ検査符号化器を内符号の符号化を行う要素符号化器として備えてもよい。
【０１５４】
すなわち、本発明は、少なくともパリティ検査符号化器を備える符号化装置であれば適用できるものである。勿論この場合には、復号装置としては、符号化装置に対応したものを用いることはいうまでもない。
【０１５５】
さらにまた、上述した第１の実施の形態では、復号装置における外符号の軟出力復号を行う軟出力復号回路として、符号化率が“２／３”の場合に対応するものを備えるものとして説明し、第２の実施の形態では、外符号の軟出力復号を行う軟出力復号回路として、パリティをｉ＝３ビット単位で付加して符号化する場合に対応するものと、パリティをｉ＝５ビット単位で付加して符号化する場合に対応するものとを備えるものとして説明したが、本発明は、符号化装置におけるパリティ付加の単位がいかなるものであっても適用できるものであり、それにともない、復号装置における軟出力復号回路も、パリティ検査符号化のパリティ付加の単位に応じた数及び構成とするだけで適用できるものである。
【０１５６】
また、上述した実施の形態では、復号装置における外符号の軟出力復号を行う軟出力復号回路として、パリティ検査符号化のパリティ付加の単位ｉを用いて“ｉ＋１”個の演算回路とｉ個の加算器とを有するものとして説明したが、本発明は、例えばこれらの演算回路及び加算器をそれぞれ共用するといったように、他の構成であってもよく、演算回路及び加算器をそれぞれ共用した場合には、回路規模の削減を図ることもできる。
【０１５７】
さらに、上述した実施の形態では、符号化装置におけるアキュムレータに対応する軟出力復号回路として、ＢＣＪＲアルゴリズムや、Ｍａｘ−Ｌｏｇ−ＢＣＪＲアルゴリズム若しくはＬｏｇ−ＢＣＪＲアルゴリズムに基づくＭＡＰ復号を行うものについて説明したが、本発明は、例えばいわゆるＳＯＶＡ（Soft Output Viterbi Algorithm）による復号を行うといったように、他の軟出力復号にも適用可能である。
【０１５８】
以下では、この具体例として、確率を対数尤度表記して対数尤度の形式で扱うＢＣＪＲアルゴリズムを改良した新規のアルゴリズムについて説明する。
【０１５９】
このアルゴリズムは、いわゆる時刻ｔにおける確率α_t，β_t，γ_t、及び軟出力λ_tを自然対数を用いて対数尤度表記した確率対数尤度Ｉα_t，Ｉβ_t，Ｉγ_t、及び対数軟出力Ｉλ_tを求めるものであり、少なくとも各ステートにおける確率対数尤度Ｉα_t，Ｉβ_tの値の差分値を用いて復号を行うものである。このアルゴリズムが適用される軟出力復号回路は、回路規模が削減され、処理の高速化を図ることができる。
【０１６０】
なお、以下では、対数尤度表記した確率対数尤度Ｉα_t，Ｉβ_t，Ｉγ_tは、それぞれ、確率の比の対数尤度表記である確率対数尤度比であるものとして説明する。また、以下では、上述した符号化装置１におけるアキュムレータ３０による符号を軟出力復号回路４０により復号する場合について説明する。
【０１６１】
確率を対数尤度表記して対数尤度の形式で扱うＢＣＪＲアルゴリズムにおいては、ｍを時刻ｔにおけるステートとすると、確率対数尤度Ｉα_t（ｍ），Ｉβ_t（ｍ）を算出する際に本質的に必要となるのは、確率対数尤度Ｉα_t（ｍ），Ｉβ_t（ｍ）の値そのものではなく、確率対数尤度Ｉα_t（ｍ），Ｉβ_t（ｍ）を各ステートにおける値の総和で正規化した場合の値、すなわち、各ステートにおける値の差分値である。
【０１６２】
そこで、軟出力復号回路４０は、アキュムレータ３０における２つのステートＳ₀，Ｓ₁に対する確率対数尤度Ｉα_t（ｍ），Ｉβ_t（ｍ）の反復演算を行うのではなく、ステートＳ₀，Ｓ₁における値の差分値に着目して演算を行う。ここで、ステートＳ₀における時刻ｔでの確率対数尤度Ｉα_t（Ｓ₀）を“Ｕ_t”と置き換え、ステートＳ₁における時刻ｔでの確率対数尤度Ｉα_t（Ｓ₁）を“Ｖ_t”と置き換え、ステートＳ₀における時刻ｔでの確率対数尤度Ｉβ_t（Ｓ₀）を“Ｗ_t”と置き換え、ステートＳ₁における時刻ｔでの確率対数尤度Ｉβ_t（Ｓ₁）を“Ｚ_t”と置き換える。
【０１６３】
このとき、上述した事前確率情報Ｄ６に対応するものであり、インターリーブデータＤ３として入力されるビットが“１”である確率と“０”である確率との比の自然対数値である事前確率情報をＡ_tとし、受信値Ｄ５のみから決定される符号化データＤ４の１シンボルの符号ビットに対する事後確率情報をｙ_tとすると、各ステートにおける確率対数尤度Ｉα_t（ｍ）、すなわち、確率対数尤度Ｕ_t,Ｖ_tは、それぞれ、次式（２０）及び次式（２１）で表される。なお、次式（２０）及び次式（２１）における演算子“＃”は、いわゆるｌｏｇ−ｓｕｍ演算を示すものであり、以下、ｌｏｇ−ｓｕｍ演算は、演算子“＃”により表すものとする。
【０１６４】
【数２０】

【０１６５】
【数２１】

【０１６６】
したがって、各ステートにおける確率対数尤度Ｉα_t（ｍ）の値の差分値、すなわち、確率対数尤度Ｕ_t,Ｖ_tの差分値Ｕ_t−Ｖ_tは、上述した演算子“＄”を用いて次式（２２）に示すように展開される。
【０１６７】
【数２２】

【０１６８】
一方、各ステートにおける確率対数尤度Ｉβ_t（ｍ）、すなわち、確率対数尤度Ｗ_t,Ｚ_tは、それぞれ、事前確率情報Ａ_t及び事後確率情報ｙ_tを用いて、次式（２３）及び次式（２４）で表される。
【０１６９】
【数２３】

【０１７０】
【数２４】

【０１７１】
したがって、各ステートにおける確率対数尤度Ｉβ_t（ｍ）の値の差分値、すなわち、確率対数尤度Ｗ_t,Ｚ_tの差分値Ｗ_t−Ｚ_tは、次式（２５）に示すように展開される。
【０１７２】
【数２５】

【０１７３】
このように、上式（２２）及び上式（２５）、すなわち、各ステートにおける確率対数尤度Ｉα_t（ｍ），Ｉβ_t（ｍ）の値の差分値は、ともに、演算子“＄”で与えられる演算と加算とを用いて表現することができる。
【０１７４】
したがって、対数軟出力Ｉλ_tは、確率対数尤度Ｕ_t，Ｖ_t，Ｗ_t，Ｚ_t、事前確率情報Ａ_t及び事後確率情報ｙ_tを用いて、次式（２６）で表される。
【０１７５】
【数２６】

【０１７６】
この上式（２６）において、演算子“＄”で表される右辺第２項及び第３項は、上述した外部情報Ｄ７に対応する外部情報を示している。このように、上式（２６）、すなわち、対数軟出力Ｉλ_tも、各ステートにおける確率対数尤度Ｉα_t（ｍ），Ｉβ_t（ｍ）の値の差分値と同様に、演算子“＄”で与えられる演算と加算とを用いて表現することができる。
【０１７７】
したがって、確率を対数尤度表記して対数尤度の形式で扱う通常のＢＣＪＲアルゴリズムにおいては、確率対数尤度Ｉα，Ｉβのそれぞれを求める反復演算を行う際に、ステート数分の値を保持する必要があったが、このアルゴリズムにおいては、差分値Ｕ_t−Ｖ_t，Ｗ_t−Ｚ_tを求めればよく、それぞれ、“ステート数−１”分の値を保持すればよい。
【０１７８】
また、このアルゴリズムにおいては、差分値を用いることから、通常のＢＣＪＲアルゴリズムのように、保持している値のオーバーフローを生じることがなく、正規化を行う必要がない。
【０１７９】
さらに、このアルゴリズムにおいては、ｌｏｇ−ｓｕｍ演算を行う必要がないことにも注目すべきである。このアルゴリズムにおいては、差分値Ｕ_t−Ｖ_t，Ｗ_t−Ｚ_t及び対数軟出力Ｉλ_tを求める際に、演算子“＄”で表される演算をそれぞれ１回ずつ行えばよい。
【０１８０】
さらにまた、演算子“＄”で表される演算は、上式（１６）及び上式（１７）に示したように、関数ｆによる変換と加算とにより実現することができることから、計算量の少ないより簡便な実装とすることも可能である。
【０１８１】
以上の議論から、回路規模を削減することができ、処理の高速化を図ることができる軟出力復号回路４０の実装が期待できる。
【０１８２】
さて、このようなアルゴリズムを実装する軟出力復号回路４０は、図１７乃至図１９に示すような各部を備えるものとなる。ここで、図１７には、軟出力復号回路４０の各部のうち、確率対数尤度Ｉα_tを算出する部分を示し、図１８には、確率対数尤度Ｉβ_tを算出する部分を示し、図１９には、対数軟出力Ｉλ_tを算出する部分を示している。
【０１８３】
なお、確率対数尤度Ｉγ_tは、事後確率情報ｙ_tと事前確率情報Ａ_tとにより決定されるものである。すなわち、確率対数尤度Ｉγ_tは、事後確率情報ｙ_tと事前確率情報Ａ_tとを用いて、事後確率情報ｙ_t毎に、すなわち、受信値毎に、符号の出力パターンと事後確率情報により決定される確率γの自然対数値である。換言すれば、軟出力復号回路４０は、図２０に示すマトリックスで表される確率対数尤度Ｉγ_tを算出することになる。
【０１８４】
図１７に示す軟出力復号回路４０は、確率対数尤度Ｉα_tを算出するＩα算出回路として、上述した演算子“＄”で表される演算を行う演算手段である演算回路１３１と、加算器１３２と、データを保持するレジスタ１３３とを備える。
【０１８５】
演算回路１３１は、事前確率情報Ａ_tと、レジスタ１３３から供給された１時刻前の確率対数尤度の差分値Ｕ_t-1−Ｖ_t-1とを用いて、演算子“＄”で表される演算を行う。演算回路１３１は、演算して得られたデータを加算器１３２に供給する。なお、この演算回路１３１は、上述した関数ｆと変数ｘとの関係を、図示しないＲＯＭに記憶されたテーブルを参照することにより求め、上式（１６）に示した演算を行うものであってもよく、若しくは、関数ｆと変数ｘとの関係を、線形近似又は閾値近似等により近似する構成であってもよい。また、演算回路１３１は、図示しないＲＡＭに保持された関数ｆにおける変数Ａ_iの符号と絶対値との組み合わせを用いて、上式（１６）に示した演算を行うものであってもよい。
【０１８６】
加算器１３２は、事後確率情報ｙ_tと、演算回路１３１から供給されたデータとを加算し、得られたデータをレジスタ１３３に供給する。
【０１８７】
レジスタ１３３は、加算器１３２から供給されたデータ、すなわち、確率対数尤度の差分値Ｕ_t−Ｖ_tを保持する。このレジスタ１３３に保持された確率対数尤度の差分値Ｕ_t−Ｖ_tは、図示しない記憶回路に供給される。
【０１８８】
また、軟出力復号回路４０は、図１８に示すように、確率対数尤度Ｉβ_tを算出するＩβ算出回路として、加算器１３４と、演算子“＄”で表される演算を行う演算手段である演算回路１３５と、レジスタ１３６とを備える。
【０１８９】
加算器１３４は、図示しない記憶回路から読み出された事後確率情報ｙ_tと、レジスタ１３６から供給された１時刻前の確率対数尤度の差分値Ｗ_t-1−Ｚ_t-1とを加算し、得られたデータを演算回路１３５に供給する。
【０１９０】
演算回路１３５は、図示しない記憶回路から読み出された事前確率情報Ａ_tと、加算器１３４から供給されたデータとを用いて、演算回路１３１と同様の演算を行う。演算回路１３５は、演算して得られたデータをレジスタ１３６に供給する。
【０１９１】
レジスタ１３６は、演算回路１３５から供給されたデータ、すなわち、確率対数尤度の差分値Ｗ_t−Ｚ_tを保持する。このレジスタ１３６に保持された確率対数尤度の差分値Ｗ_t−Ｚ_tは、図示しない記憶回路に供給される。
【０１９２】
このような軟出力復号回路４０は、事前確率情報Ａ_tと事後確率情報ｙ_tとを用い、少なくとも各ステートにおける確率対数尤度Ｉα_t，Ｉβ_tを変数の一部として、上式（２２）及び上式（２５）に示した演算を行い、各ステートＳ₀，Ｓ₁における確率対数尤度Ｉα_t（Ｓ₀），Ｉα_t（Ｓ₁）の差分値Ｉα_t（Ｓ₀）−Ｉα_t（Ｓ₁）（＝Ｕ_t−Ｖ_t）及び各ステートＳ₀，Ｓ₁における確率対数尤度Ｉβ_t（Ｓ₀），Ｉβ_t（Ｓ₁）の差分値Ｉβ_t（Ｓ₀）−Ｉβ_t（Ｓ₁）（＝Ｗ_t−Ｚ_t）を算出する。すなわち、軟出力復号回路４０は、事前確率情報Ａ_t及び事後確率情報ｙ_tに基づいて、事後確率情報ｙ_t毎に、符号化開始ステートから時系列順に各ステートに至る確率αの自然対数値である確率対数尤度Ｉαの各ステートにおける値の差分値を算出するとともに、打ち切りステートから時系列の逆順に各ステートに至る確率βの自然対数値である確率対数尤度Ｉβの各ステートにおける値の差分値を算出する。そして、軟出力復号回路４０は、レジスタ１３３に保持した差分値Ｕ_t−Ｖ_t及びレジスタ１３６に保持した差分値Ｗ_t−Ｚ_tを、図示しない記憶回路に供給する。
【０１９３】
また、軟出力復号回路４０は、図１９に示すように、対数軟出力Ｉλ_tを算出する部分として、２つの加算器１３７，１３９と、演算子“＄”で表される演算を行う演算手段である演算回路１３８とを備える。
【０１９４】
加算器１３７は、図示しない記憶回路から読み出された事後確率情報ｙ_tと、図示しない記憶回路から読み出された差分値Ｗ_t−Ｚ_tとを加算し、得られたデータを演算回路１３８に供給する。
【０１９５】
演算回路１３８は、図示しない記憶回路から読み出された差分値Ｕ_t−Ｖ_tと、加算器１３７から供給されたデータとを用いて、演算回路１３１と同様の演算を行う。演算回路１３８は、演算して得られたデータを加算器１３９に供給する。
【０１９６】
加算器１３９は、図示しない記憶回路から読み出された事前確率情報Ａ_tと、演算回路１３８から供給されたデータとを加算し、得られたデータを対数軟出力Ｉλ_tとして外部に出力する。
【０１９７】
このような軟出力復号回路４０は、図示しない記憶回路から読み出された事前確率情報Ａ_t、事後確率情報ｙ_t及び差分値Ｕ_t−Ｖ_t，Ｗ_t−Ｚ_tを用い、少なくとも各ステートにおける差分値Ｕ_t−Ｖ_t，Ｗ_t−Ｚ_tを変数の一部として、上式（２６）に示した演算を行い、各時刻における対数軟出力Ｉλ_tを算出する。そして、軟出力復号回路４０は、算出した対数軟出力Ｉλ_tを時系列順に並べ替えた後、外部に出力する。
【０１９８】
このように、軟出力復号回路４０は、通常のＢＣＪＲアルゴリズムを改良し、各ステートにおける確率対数尤度Ｉα_t，Ｉβ_tの値の差分値を用いて復号を行うアルゴリズムを適用した軟出力復号を行うことができる。
【０１９９】
この軟出力復号回路４０は、差分値Ｕ_t−Ｖ_t，Ｗ_t−Ｚ_tのそれぞれを算出するために、“ステート数−１”、ここでは１つずつの演算回路１３１，１３５を備えるとともに、対数軟出力Ｉλ_tを算出するために、同じく１つの演算回路１３８を備えればよい。これらの演算回路１３１，１３５，１３８は、それぞれ、上述したように、簡便な構成とされることから、軟出力復号回路４０は、回路規模が削減されるとともに、処理時間の短縮化を図ることができる。
【０２００】
また、軟出力復号回路４０は、通常のＢＣＪＲアルゴリズムを実装する軟出力復号回路のように、正規化回路を備える必要がなく、さらに、差分値Ｕ_t−Ｖ_t，Ｗ_t−Ｚ_tのそれぞれを算出するために必要なレジスタの数も、“ステート数−１”、ここでは１つずつで済むことから、回路規模が削減され、処理の高速化を図ることができる。
【０２０１】
なお、この軟出力復号回路４０は、アキュムレータ３０に限らず、ステートの遷移が状態遷移図であるトレリスで表される線形のトレリス符号であれば、いかなる符号化率の符号化を行う要素符号化器による符号を復号することができる。例えば、ステート数が４の符号を復号する場合には、軟出力復号回路４０としては、“ステート数−１”、すなわち、３つの差分値を任意に選択して用いればよい。特に、この軟出力復号回路４０は、ステート数が小さい符号に対して有効に作用するものであり、アキュムレータ３０による符号の復号を行う際には、顕著な効果を奏するものである。
【０２０２】
このように、軟出力復号回路４０は、各ステートにおける確率対数尤度Ｉα_t，Ｉβ_tの値の差分値を用いて復号を行うことによって、簡便且つ少ない演算処理で済み、性能を劣化させることなく、回路規模の削減とともに処理の高速化を図ることができる。
【０２０３】
本発明は、符号化装置におけるアキュムレータに対応する軟出力復号回路として、このようなアルゴリズムをはじめとする種々の軟出力復号を適用することができる。
【０２０４】
さらにまた、上述した実施の形態では、符号化装置及び復号装置をデータ送受信システムにおける送信装置及び受信装置に適用して説明したが、本発明は、例えばフロッピーディスク、ＣＤ−ＲＯＭ又はＭＯ（Magneto Optical）といった磁気、光又は光磁気ディスク等の記録媒体に対する記録及び／又は再生を行う記録及び／又は再生装置に適用することもできる。この場合、符号化装置により符号化されたデータは、無記憶通信路に等価とされる記録媒体に記録され、復号装置により復号されて再生される。
【０２０５】
以上のように、本発明は、その趣旨を逸脱しない範囲で適宜変更が可能であることはいうまでもない。
【０２０６】
【発明の効果】
以上詳細に説明したように、本発明にかかる符号化装置は、入力されたデータに対して縦列連接符号化を行う符号化装置であって、入力されたデータに対して第１の符号の符号化を行う第１の符号化手段と、この第１の符号化手段により符号化されたデータを構成する各ビットの順序を置換して並べ替える置換手段と、この置換手段から供給されたデータに対して第２の符号の符号化を行う第２の符号化手段とを備え、第１の符号化手段又は第２の符号化手段のうち、少なくとも一方の符号化手段は、入力されたデータに対して所定の単位毎に１ビットのパリティを付加するパリティ検査符号化を行う。
【０２０７】
したがって、本発明にかかる符号化装置は、第１の符号化手段又は第２の符号化手段のうち、少なくとも一方の符号化手段によって、パリティ検査符号化を行うことによって、所望の高い符号化率の下に、高性能の符号化を行うことができる。
【０２０８】
また、本発明にかかる符号化方法は、入力されたデータに対して縦列連接符号化を行う符号化方法であって、入力されたデータに対して第１の符号の符号化を行う第１の符号化工程と、この第１の符号化工程にて符号化されたデータを構成する各ビットの順序を置換して並べ替える置換工程と、この置換工程にて並べ替えられたデータに対して第２の符号の符号化を行う第２の符号化工程とを備え、第１の符号化工程又は第２の符号化工程のうち、少なくとも一方の符号化工程では、入力されたデータに対して所定の単位毎に１ビットのパリティを付加するパリティ検査符号化を行う。
【０２０９】
したがって、本発明にかかる符号化方法は、第１の符号化工程又は第２の符号化工程のうち、少なくとも一方の符号化工程にて、パリティ検査符号化を行うことによって、所望の高い符号化率の下に、高性能の符号化を行うことを可能とする。
【０２１０】
さらに、本発明にかかる復号装置は、入力されたデータに対して第１の符号の符号化を行う第１の符号化手段と、この第１の符号化手段により符号化されたデータを構成する各ビットの順序を置換して並べ替える第１の置換手段と、この第１の置換手段から供給されたデータに対して第２の符号の符号化を行う第２の符号化手段とを備え、第１の符号化手段又は第２の符号化手段のうち、少なくとも一方の符号化手段は、入力されたデータに対して所定の単位毎に１ビットのパリティを付加するパリティ検査符号化を行う符号化機器により縦列連接符号化された符号の復号を行う復号装置であって、第２の符号化手段に対応して備えられ、入力された軟入力である受信値と、入力された軟入力である情報ビットに対する事前確率情報とを用いて軟出力復号を行う第１の軟出力復号手段と、この第１の軟出力復号手段に縦列に連接し、第１の置換手段により並べ替えられたデータのビット配列を、第１の符号化手段により符号化されたデータのビット配列に戻すように、入力された軟入力のデータを並べ替える逆置換手段と、第１の符号化手段に対応して備えられ且つ逆置換手段に縦列に連接し、逆置換手段から出力された軟入力である符号ビットに対する事前確率情報と、入力された軟入力である情報ビットに対する事前確率情報とを用いて軟出力復号を行う第２の軟出力復号手段と、第１の置換手段と同一の置換位置情報に基づいて、第２の軟出力復号手段から出力された軟入力のデータを構成する各ビットの順序を置換して並べ替える第２の置換手段とを備え、第１の軟出力復号手段は、情報ビットに対する事前確率情報として、第２の置換手段から出力された軟入力のデータを入力する。
【０２１１】
したがって、本発明にかかる復号装置は、符号化機器が備える第１の符号化手段又は第２の符号化手段のうち、少なくとも一方の符号化手段によって、パリティ検査符号化がなされた符号を高精度に復号することができる。
【０２１２】
さらにまた、本発明にかかる復号方法は、入力されたデータに対して第１の符号の符号化を行う第１の符号化工程と、この第１の符号化工程にて符号化されたデータを構成する各ビットの順序を置換して並べ替える第１の置換工程と、この第１の置換工程にて並べ替えられたデータに対して第２の符号の符号化を行う第２の符号化工程とを備え、第１の符号化工程又は第２の符号化工程のうち、少なくとも一方の符号化工程では、入力されたデータに対して所定の単位毎に１ビットのパリティを付加するパリティ検査符号化を行う符号化方法により縦列連接符号化された符号の復号を行う復号方法であって、第２の符号化工程に対応して備えられ、入力された軟入力である受信値と、入力された軟入力である情報ビットに対する事前確率情報とを用いて軟出力復号を行う第１の軟出力復号工程と、この第１の置換工程にて並べ替えられたデータのビット配列を、第１の符号化工程にて符号化されたデータのビット配列に戻すように、入力された軟入力のデータを並べ替える逆置換工程と、第１の符号化工程に対応して備えられ、逆置換工程にて並べ替えられた軟入力である符号ビットに対する事前確率情報と、入力された軟入力である情報ビットに対する事前確率情報とを用いて軟出力復号を行う第２の軟出力復号工程と、第１の置換工程と同一の置換位置情報に基づいて、第２の軟出力復号工程にて生成された軟入力のデータを構成する各ビットの順序を置換して並べ替える第２の置換工程とを備え、第１の軟出力復号工程では、情報ビットに対する事前確率情報として、第２の置換工程にて並べ替えられた軟入力のデータを入力する。
【０２１３】
したがって、本発明にかかる復号方法は、符号化方法が備える第１の符号化工程又は第２の符号化工程のうち、少なくとも一方の符号化工程にて、パリティ検査符号化がなされた符号を高精度に復号することを可能とする。
【図面の簡単な説明】
【図１】本発明の実施の形態として示すデータ送受信システムを適用する通信モデルの構成を説明するブロック図である。
【図２】本発明の第１の実施の形態として示すデータ送受信システムにおける符号化装置の構成を説明するブロック図である。
【図３】符号化装置が備えるインターリーバの構成を説明するブロック図である。
【図４】符号化装置が備えるアキュムレータの構成を説明するブロック図である。
【図５】図４に示すアキュムレータにおけるトレリスを説明する図である。
【図６】同データ送受信システムにおける復号装置の構成を説明するブロック図である。
【図７】復号装置が備える内符号の復号を行う軟出力復号回路の構成を説明するブロック図である。
【図８】復号装置が備える外符号の復号を行う軟出力復号回路の構成を説明するブロック図である。
【図９】関数ｆを説明する図である。
【図１０】本発明の第２の実施の形態として示すデータ送受信システムにおける符号化装置の構成を説明するブロック図である。
【図１１】符号化装置が備える設定器における動作を説明するための入力データと符号化データとを説明する図であって、（Ａ）は、符号化装置が備えるパリティ検査符号化器から出力される符号化データを示し、（Ｂ）は、パリティ検査符号化器に入力される入力データを示す図である。
【図１２】同データ送受信システムにおける復号装置の構成を説明するブロック図である。
【図１３】復号装置が備えるレート変換回路の構成を説明するブロック図である。
【図１４】復号装置が備える外符号の復号を行う軟出力復号回路の構成を説明するブロック図であって、パリティを３ビット単位で付加してパリティ検査符号化された符号を復号する軟出力復号回路の構成を説明するブロック図である。
【図１５】復号装置が備える外符号の復号を行う軟出力復号回路の構成を説明するブロック図であって、パリティを５ビット単位で付加してパリティ検査符号化された符号を復号する軟出力復号回路の構成を説明するブロック図である。
【図１６】符号化装置が備えるアキュムレータの構成を説明するブロック図であって、図４に示すアキュムレータとは異なるアキュムレータの構成を説明するブロック図である。
【図１７】復号装置が備える軟出力復号回路の構成を説明するブロック図であって、確率対数尤度Ｉα_tを算出する部分を示すブロック図である。
【図１８】復号装置が備える軟出力復号回路の構成を説明するブロック図であって、確率対数尤度Ｉβ_tを算出する部分を示すブロック図である。
【図１９】復号装置が備える軟出力復号回路の構成を説明するブロック図であって、対数軟出力Ｉλ_tを算出する部分を示すブロック図である。
【図２０】確率対数尤度Ｉγ_tを示すマトリックスを説明する図である。
【図２１】通信モデルの構成を説明するブロック図である。
【図２２】従来の符号化装置の構成を説明するブロック図である。
【図２３】従来の復号装置の構成を説明するブロック図である。
【符号の説明】
１，１’ 符号化装置、 ３，３’ 復号装置、 １０，１０’ パリティ検査符号化器、 ２０，６０ インターリーバ、 ３０，３０’ アキュムレータ、 ４０，９０，９０₁，９０₂ 軟出力復号回路、 ５０ デインターリーバ、７０，７０’，８０，８０’ レート変換回路、 １００ ２値化回路、 １１０ 設定器、 ９１，９２，９３，９１₁，９２₁，９３₁，９４₁，９１₂，９２₂，９３₂，９４₂，９５₂，９６₂，１３１，１３５，１３８ 演算回路、 １３３，１３６ レジスタ[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an encoding apparatus and encoding method for performing column concatenated encoding on input data, and a decoding apparatus and decoding method for decoding data subjected to column concatenated encoding.
[0002]
[Prior art]
In recent years, research in the field of communication such as mobile communication and deep space communication, the field of broadcasting such as terrestrial or satellite digital broadcasting, and the field of magnetic, optical, or magneto-optical recording that performs recording and / or reproduction on recording media has been significantly advanced. However, along with this, research on coding theory has been actively conducted for the purpose of improving the efficiency of error correction coding and decoding.
[0003]
As the theoretical limit of the code performance, the Shannon limit given by the so-called Shannon channel coding theorem is known. Shannon's channel coding theorem is: “When information is transmitted at a transmission rate R (bit / symbol) using a channel of channel capacity C (bit / symbol), if R ≦ C, The theorem is that there exists an encoding method that can make the error probability as close to “0” as possible. The Shannon limit is a theoretical limit of a transmission rate that can be transmitted without error.
[0004]
For example, “S. Benedetto, G. Montorsi, D. Divsalar, F. Pollara,“ Serial Concatenation of Interleaved Codes: Performance Analysis, Design, and Iterative Decoding ”, TDA. An encoding method using serially concatenated convolutional codes described in “Progress Report 42-126, Jet Propulsion Laboratory, Pasadena, California, Aug. 15, 1996” is known.
[0005]
The encoding by the column concatenated convolutional code is performed by an apparatus configured by connecting two convolutional encoders and an interleaver in a column. The decoding of the column concatenated convolutional code is performed by an apparatus configured by connecting two decoding circuits that output a soft-output in a column, and exchanges information between the two decoding circuits. A final decoding result is obtained.
[0006]
In addition, as a further simplification of the encoding by this cascade concatenated convolutional code, “Hui Jin and Robert J. McEliece,“ RA codes achieve AWGN channel capacity ”, pp. 10-18, in Proc. 13th International Symposium on Applied There is an RA (Repeat-Accumulate) code described in “Algebra, Algebraic Algorithms, and Error-Correcting Codes” (Springer Lecture Notes in Computer Science no. 1719). This RA code is generated by a device in which an encoder for performing repetitive encoding and an accumulator for accumulating input data are connected in series via an interleaver, and the number of repetitions is infinite. The performance reaches the Shannon limit.
[0007]
Hereinafter, an encoding apparatus that performs encoding using RA codes and a decoding apparatus that performs decoding of RA codes will be described. In the following description, as shown in FIG. 21, digital information is encoded by an encoding device 201 provided in a transmission device (not shown), and the output is received via a no-memoryless communication path 202 with noise. Let us consider a case in which the data is input to and received by the decoding device 203 provided in the receiving device.
[0008]
As shown in FIG. 22, an encoding apparatus 201 that performs encoding by RA code includes a repetitive encoder 210 that performs repetitive encoding as encoding of a first code (hereinafter referred to as an outer code), and an input. An interleaver 220 that rearranges the order of the data, and an accumulator 230 that performs convolutional encoding by cumulative addition as encoding of the second code (hereinafter referred to as inner code). The encoding device 201 performs RA encoding with an encoding rate of “k / qk = 1 / q” on the input k-bit input data D201, and converts the input data into qk-bit encoded data D204. Output to the outside via a modulator (not shown).
[0009]
When the k-bit input data D201 is input, the repetitive encoder 210 performs repetitive encoding of the repetitive number q on the input data D201, and outputs it to the subsequent interleaver 220 as qk-bit encoded data D202. . That is, iterative encoder 210 performs iterative encoding with a coding rate of “k / qk = 1 / q” as outer code encoding, and outputs encoded data D202 to subsequent interleaver 220. Note that a small value is usually selected as the number of repetitions q. For example, about q = 3 is generally used.
[0010]
The interleaver 220 receives the qk-bit encoded data D202 output from the iterative encoder 210, and performs interleaving with a predetermined length. That is, the interleaver 220 rearranges the order of each bit constituting the input encoded data D202, and outputs the generated qk-bit interleaved data D203 to the accumulator 230 at the subsequent stage.
[0011]
When the accumulator 230 receives the qk-bit interleaved data D203, the accumulator 230 performs a recursive convolution operation on the interleaved data D203, thereby accumulating each bit of the sequentially input interleaved data D203, and the operation result is qk bits. The encoded data D204 is output to the outside. That is, the accumulator 230 performs a recursive convolution operation with an encoding rate of “1” as the encoding of the inner code, and outputs the encoded data D204 to the outside.
[0012]
In such an encoding apparatus 201, the iterative encoder 210 performs repetitive encoding with an encoding rate of “1 / q” as encoding of the outer code, and the accumulator 230 sets the encoding rate as encoding of the inner code. By performing a recursive convolution operation of “1”, cascade concatenated encoding is performed using an RA code having an encoding rate of “(1 / q) × 1 = 1 / q” as a whole. The data encoded by the encoding device 201 is subjected to signal point mapping by a modulator (not shown) based on a predetermined modulation method, and is output to the receiving device via the memoryless communication path 202.
[0013]
On the other hand, as a decoding device 203 that performs decoding of the RA code by the encoding device 201, for example, as shown in FIG. 23, a soft output decoding circuit 240 that decodes the inner code, and a decoder that restores the order of the input data. Some include an interleaver 250, an interleaver 260 that rearranges the order of input data, and a soft output decoding circuit 270 that decodes an outer code. The decoding device 203 estimates the input data D201 in the encoding device 201 from the received value D205, which is an analog value taken as a soft-input under the influence of noise generated on the memoryless communication path 202, and is decoded. Output as data D210.
[0014]
The soft output decoding circuit 240 is provided corresponding to the accumulator 230 in the encoding device 201, and is based on a so-called BCJR (Bahl, Cocke, Jelinek and Raviv) algorithm, MAP (Maximum A Posteriori probability) decoding, SOVA (Soft Output Viterbi Algorithm) Decoding. The soft output decoding circuit 240 receives the soft input reception value D205 received by the receiving device, and also inputs the prior probability information D206 for the soft input information bits supplied from the interleaver 260, and receives these reception values D205. And prior probability information D206 are used to perform soft output decoding of the inner code. Then, the soft output decoding circuit 240 generates external information D207 for the information bits obtained by the code constraint condition, and outputs the external information D207 to the subsequent deinterleaver 250 as a soft output. The external information D207 corresponds to the interleaved data D203 interleaved by the interleaver 220 in the encoding device 201.
[0015]
The deinterleaver 250 is output from the soft output decoding circuit 240 so that the bit arrangement of the interleaved data D203 interleaved by the interleaver 220 in the encoding apparatus 201 is returned to the original bit arrangement of the encoded data D202. Deinterleaving is applied to the external information D207 of soft input. The deinterleaver 250 outputs the data obtained by deinterleaving as prior probability information D208 for the code bit in the soft output decoding circuit 270 at the subsequent stage.
[0016]
The interleaver 260 performs interleaving based on the same replacement position information as that of the interleaver 220 in the encoding device 201 with respect to the external information D209 for the code bit that is the soft input output from the soft output decoding circuit 270. The interleaver 260 outputs the data obtained by the interleaving as prior probability information D206 for the information bits in the soft output decoding circuit 240.
[0017]
The soft output decoding circuit 270 is provided corresponding to the iterative encoder 210 in the encoding device 201, and performs MAP decoding and SOVA decoding. The soft output decoding circuit 270 inputs the prior probability information D208 for the soft input code bit output from the deinterleaver 250, and inputs the prior probability information for the information bit whose value is “0” (not shown). Using these prior probability information, soft output decoding of the outer code is performed. Then, the soft output decoding circuit 270 generates external information D209 for the code bit obtained by the code constraint condition, and outputs the external information D209 to the interleaver 260 as a soft output. Also, although not shown, the soft output decoding circuit 270 generates external information for information bits obtained by code constraint conditions, and outputs hard-output decoded data D210 based on the external information. .
[0018]
Upon receiving the received value D205, the decoding device 203 repeatedly performs the decoding operation of the soft output decoding circuit 240 to the soft output decoding circuit 270 a predetermined number of times, for example, several times to several tens times, Based on the soft output external information obtained as a result of the decoding operation, decoded data D210 is output.
[0019]
As described above, in the system configured by the encoding device 201 and the decoding device 203, it is possible to perform encoding by RA code and decoding of RA code.
[0020]
[Problems to be solved by the invention]
By the way, although the above-mentioned RA code can make both the encoding device and the decoding device simple, high performance cannot be obtained unless the number of repetitions of the outer code is increased. There was a problem that was low. For this reason, the RA code still has room for improvement in terms of performance.
[0021]
The present invention has been made in view of such circumstances, and an encoding device, an encoding method, and a decoding device capable of realizing high-performance encoding and decoding at a high encoding rate. It is an object of the present invention to provide a decoding method.
[0022]
[Means for Solving the Problems]
  An encoding apparatus according to the present invention that achieves the above-described object is an encoding apparatus that performs cascade concatenated encoding on input data, and encodes a first code on the input data. A first encoding means for performing, a replacement means for rearranging the order of each bit constituting the data encoded by the first encoding means, and a second for the data supplied from the replacement means Second encoding means for encoding the code of at least one of the first encoding means and the second encoding means, wherein at least one of the encoding means is predetermined for the input data Parity check encoding that adds 1-bit parity for each unitOf the first encoding means or the second encoding means, the encoding means for performing parity check encoding includes a setting means for setting a distribution of units for adding parity, and the first encoding means or Of the second encoding means, the encoding means for performing parity check encoding changes the unit for adding parity to the input data in accordance with the setting contents of the setting means.It is characterized by that.
[0023]
Such an encoding apparatus according to the present invention performs parity check encoding by at least one of the first encoding unit and the second encoding unit.
[0024]
  An encoding method according to the present invention that achieves the above-described object is an encoding method for performing serially concatenated encoding on input data, wherein the first code is encoded on the input data. A first encoding step that performs encoding, a replacement step that replaces and rearranges the order of each bit that constitutes the data encoded in the first encoding step, and the data that is rearranged in the replacement step A second encoding step for encoding the second code with respect to the input data in at least one of the first encoding step and the second encoding step. Parity check coding to add 1-bit parity for each predetermined unitOf the first encoding process or the second encoding process, in the encoding process for performing parity check encoding, the distribution of units to which parity is added is set and input according to this setting content. Change the unit for adding parity to dataIt is characterized by that.
[0025]
Such an encoding method according to the present invention performs parity check encoding in at least one of the first encoding step and the second encoding step.
[0026]
  Furthermore, a decoding device according to the present invention that achieves the above-described object is encoded by first encoding means for encoding a first code for input data, and first encoding means. First replacement means for rearranging and rearranging the order of each bit constituting the data, and second encoding means for encoding the second code for the data supplied from the first replacement means A parity check code in which at least one of the first encoding means and the second encoding means adds 1-bit parity to the input data for each predetermined unit. A decoding device that decodes a serially concatenated code by an encoding device that performs encoding, and is provided corresponding to a second encoding means, and an input received value that is a soft input and is input Pre-accuracy for information bits that are soft inputs A first soft output decoding means for performing soft output decoding using information, and a bit array of the data rearranged by the first replacement means in a column connected to the first soft output decoding means in a first column. Reverse replacement means for rearranging the input soft input data so as to return to the bit array of the data encoded by the encoding means,First rate conversion means for converting the clock rate of the data output from the reverse replacement means;Soft output decoding is performed using prior probability information for a code bit that is an input soft input and prior probability information for an information bit that is an input soft input, provided corresponding to the first encoding means. Second soft output decoding means;Second rate conversion means for converting the clock rate of the data output from the second soft output decoding means;And second replacement means for replacing the order of each bit constituting the input soft input data on the basis of the same replacement position information as that of the first replacement means. The means is characterized by inputting soft-input data output from the second replacement means as prior probability information for the information bits.
  In addition, a decoding device according to the present invention that achieves the above-described object is encoded by first encoding means for encoding first code for input data, and first encoding means. First replacement means for rearranging and rearranging the order of each bit constituting the data, and second encoding means for encoding the second code for the data supplied from the first replacement means A parity check code in which at least one of the first encoding means and the second encoding means adds 1-bit parity to the input data for each predetermined unit. A decoding device that decodes a serially concatenated code by an encoding device that performs encoding, and is provided corresponding to a second encoding means, and an input received value that is a soft input and is input Priors for information bits that are soft inputs First soft output decoding means for performing soft output decoding using the information, and a bit arrangement of the data rearranged by the first replacement means connected in series to the first soft output decoding means, The reverse replacement means for rearranging the input soft input data so as to return to the bit arrangement of the data encoded by the encoding means, and the first encoding means are provided. Second soft output decoding means for performing soft output decoding using the prior probability information for the input code bit and the prior probability information for the input soft input information bit, and the same as the first replacement means Second replacement means for rearranging and rearranging the order of each bit constituting the input soft-input data based on the replacement position information, wherein the first soft-output decoding means includes a prior probability for the information bits As information, the second replacement The soft input data output from the stage is input, and the encoding device is a unit for adding parity in the encoding means for performing parity check encoding, out of the first encoding means or the second encoding means. A setting unit for setting a distribution is provided. Of the first encoding unit or the second encoding unit, the encoding unit that performs parity check encoding is input according to the setting content by the setting unit. It is characterized in that the unit for adding parity to data is changed.
[0027]
Such a decoding apparatus according to the present invention decodes a code subjected to parity check coding by at least one of the first coding means or the second coding means provided in the coding device. To do.
[0028]
  Furthermore, the decoding method according to the present invention that achieves the above-described object includes a first encoding step that performs encoding of a first code on input data, and a code in the first encoding step. A first replacement step of rearranging and rearranging the order of each bit constituting the converted data, and a second encoding of the second code for the data rearranged in the first replacement step And at least one of the first encoding step and the second encoding step adds 1-bit parity to the input data for each predetermined unit. A decoding method for decoding a serially concatenated code by an encoding method for performing parity check encoding, wherein the received value is a soft input provided corresponding to the second encoding step. And for the input information bits that are soft inputs The first soft output decoding step for performing soft output decoding using the prior probability information and the bit array of the data rearranged in the first replacement step are encoded in the first encoding step. A reverse permutation step for reordering the input soft-input data to return to the bit array of data;A first rate conversion step of converting a clock rate of the data rearranged in the reverse replacement step;Soft output decoding is performed using prior probability information for a code bit that is an input soft input and prior probability information for an information bit that is an input soft input. A second soft output decoding step;A second rate conversion step of converting the clock rate of the data generated in the second soft output decoding step;A second replacement step of replacing the order of each bit constituting the input soft input data based on the same replacement position information as in the first replacement step and rearranging the first soft output decoding The process is characterized by inputting soft input data rearranged in the second replacement process as prior probability information for information bits.
  The decoding method according to the present invention that achieves the above-described object includes a first encoding step of encoding a first code for input data, and encoding in the first encoding step. A first replacement step of rearranging and rearranging the order of each bit constituting the generated data, and a second code for encoding the second code for the data rearranged in the first replacement step An encoding step, and at least one of the first encoding step and the second encoding step adds 1-bit parity to the input data for each predetermined unit. A decoding method for decoding a serially concatenated code by an encoding method for performing parity check encoding, wherein the received value is a soft input provided corresponding to the second encoding step. And for the input soft bit information bit The first soft output decoding step that performs soft output decoding using the previous probability information and the bit array of the data rearranged in the first replacement step are encoded in the first encoding step Prior probability information for a code bit that is an input soft input and is provided corresponding to a reverse permutation step for rearranging input soft-input data and a first encoding step so as to return to the bit arrangement of the data And a second soft output decoding step for performing soft output decoding using prior probability information for information bits that are input soft inputs, and input based on the same replacement position information as in the first replacement step. A second replacement step of rearranging and rearranging the order of each bit constituting the soft input data. In the first soft output decoding step, as the prior probability information for the information bits, the second replacement step Sorted soft input In the encoding process in which parity check encoding is performed in the first encoding process or the second encoding process, the distribution of units for adding parity is set, and according to the setting contents The unit for adding parity to input data is changed.
[0029]
In such a decoding method according to the present invention, a code that has been subjected to parity check encoding in at least one of the first encoding step and the second encoding step included in the encoding method is used. Decrypt.
[0030]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, specific embodiments to which the present invention is applied will be described in detail with reference to the drawings.
[0031]
In this embodiment, as shown in FIG. 1, digital information is encoded by an encoding device 1 included in a transmission device (not shown), and the output is input to a reception device (not shown) via a no-memory communication channel 2 having noise. Thus, the data transmission / reception system is applied to a communication model decoded by the decoding device 3 included in the receiving device.
[0032]
First, the data transmission / reception system shown as the first embodiment will be described.
[0033]
In this data transmission / reception system, the encoding device 1 uses a 1-bit parity for information of a predetermined unit instead of a repetitive encoder in an RA (Repeat-Accumulate) code which is a kind of cascade concatenated encoding. At least a parity check encoder to be added is provided. Hereinafter, the code in the encoding device 1 is referred to as a PA (Parity-check-Accumulate) code. The decoding device 3 is for decoding the code by the encoding device 1.
[0034]
As shown in FIG. 2, the encoding apparatus 1 adds 1-bit parity for each predetermined unit to data input as the encoding of the first code (hereinafter referred to as an outer code). (1) a parity check encoder 10 as an encoding means, an interleaver 20 as a (first) replacement means for rearranging the order of input data, and a second code (hereinafter referred to as an inner code). And accumulator 30 which is (second) encoding means for performing convolutional encoding by cumulative addition. The encoding device 1 encodes the input k-bit input data D1 with an encoding rate of “k / (k + 1)”, converts it into k + 1-bit encoded data D4, and performs modulation (not shown). Output to the outside through a device.
[0035]
When the parity check encoder 10 receives the input data D1, the parity check encoder 10 adds 1-bit parity to the input data D1 in units of k bits, and outputs the input data D1 to the subsequent interleaver 20 as encoded data D2 of k + 1 bits. . That is, the parity check encoder 10 performs parity check encoding with an encoding rate of “k / (k + 1)” as outer code encoding, and outputs the encoded data D2 to the interleaver 20 at the subsequent stage.
[0036]
The interleaver 20 receives the k + 1-bit encoded data D2 output from the parity check encoder 10 and performs interleaving with a predetermined length N. As shown in FIG. 3, the interleaver 20 includes an input data holding memory 21 that holds input data, a data replacement circuit 22 that rearranges (replaces) the order of input data, and data replacement position information. It has a replacement data generation unit 23 to generate, and an output data holding memory 24 that holds data to be output.
[0037]
The input data holding memory 21 receives and holds the k + 1-bit encoded data D2 output from the parity check encoder 10, and supplies the encoded data D2 to the data replacement circuit 22 at a predetermined timing.
[0038]
The data replacement circuit 22 rearranges the order of the encoded data D2 supplied from the input data holding memory 21 based on the replacement position information of the data generated by the replacement data generation unit 23. The data replacement circuit 22 supplies the rearranged data to the output data holding memory 24.
[0039]
The replacement data generation unit 23 includes, for example, a ROM (Read Only Memory) (not shown) and the like, generates data replacement position information based on the generated random number and the like, and stores the replacement position information in the ROM. The replacement position information generated and stored by the replacement data generation unit 23 is read by the data replacement circuit 22 as needed.
[0040]
The output data holding memory 24 holds the data supplied from the data replacement circuit 22 and outputs these data to the subsequent accumulator 30 as k + 1 bit interleaved data D3 at a predetermined timing.
[0041]
Such an interleaver 20 performs interleaving of length N on the encoded data D2 output from the parity check encoder 10 and outputs it to the accumulator 30 at the subsequent stage.
[0042]
More specifically, the input data holding memory 21 sequentially inputs and holds the encoded data D2 output from the parity check encoder 10. Then, the input data holding memory 21 sequentially holds, for example, each bit constituting the encoded data D2 at a predetermined timing, and at a timing when a bit sequence composed of N bits (N is an arbitrary natural number) is generated. The held data is supplied to the data replacement circuit 22.
[0043]
Subsequently, the data replacement circuit 22 rearranges the order of each of the N bits constituting the bit sequence supplied from the input data holding memory 21 based on the replacement position information generated by the replacement data generation unit 23. The data replacement circuit 22 supplies a new bit sequence obtained by the rearrangement to the output data holding memory 24.
[0044]
The output data holding memory 24 holds each bit constituting the bit series supplied from the data replacement circuit 22, and outputs the held data as interleaved data D3 to the subsequent accumulator 30 at a predetermined timing.
[0045]
As described above, the interleaver 20 receives the k + 1-bit encoded data D2 output from the parity check encoder 10 and stores the order of each bit constituting the encoded data D2 in advance. Rearrangement is performed based on the information to generate k + 1 bit interleaved data D3. Therefore, in the encoding apparatus 1, N / (k + 1) codewords output from the parity check encoder 10 exist in the N-symbol interleaved data D3.
[0046]
For example, as shown in FIG. 4, the accumulator 30 may have one exclusive OR circuit 31 and one shift register 32.
[0047]
The exclusive OR circuit 31 performs an exclusive OR operation using each bit constituting the k + 1-bit interleaved data D3 and the data supplied from the shift register 32, and externally outputs the operation result as encoded data D4. And supplied to the shift register 32.
[0048]
The shift register 32 continues to supply the held 1-bit data to the exclusive OR circuit 31. The shift register 32 newly holds 1-bit data supplied from the exclusive OR circuit 31 in synchronization with the clock, and supplies this data to the exclusive OR circuit 31 anew.
[0049]
When such accumulator 30 receives interleaved data D3 of k + 1 bits, the accumulator 30 performs a recursive convolution operation on the interleaved data D3, thereby accumulating and adding each bit of interleaved data D3 sequentially input. Is output to the outside as encoded data D4 of k + 1 bits.
[0050]
Here, a trellis which is a state transition diagram in the accumulator 30 is described as shown in FIG. In the figure, a path indicated by a broken line indicates a case where the bit input as the interleave data D3 is “0”, and a path indicated by a solid line indicates a case where the bit input as the interleave data D3 is “1”. Yes. Further, the label given to each pass indicates a bit output as encoded data D4. Here, the state is represented by the contents of the shift register 32, and the states of “0” and “1” are represented by the state S₀, State S₁It is called. In this way, the number of states in the accumulator 30 is 2, and the trellis has a structure in which two paths reach from each state to the state at the next time.
[0051]
Such an accumulator 30 performs a recursive convolution operation with an encoding rate of “1” as the encoding of the inner code, and outputs encoded data D4 to the outside.
[0052]
Such an encoding apparatus 1 performs parity check encoding with a coding rate of “k / (k + 1)” as the encoding of the outer code by the parity check encoder 10 and the encoding of the inner code by the accumulator 30. By performing a recursive convolution operation with a coding rate of “1”, as a whole, column concatenated coding with a code of a coding rate of “k / (k + 1) × 1 = k / (k + 1)” is performed. The data encoded by the encoding device 1 is subjected to signal point mapping based on a predetermined modulation method by a modulator (not shown), and is output to the receiving device via the memoryless communication path 2.
[0053]
As described above, the encoding apparatus 1 uses the parity check code instead of the repetitive code in the conventional RA code, so that the encoding rate is only “½” at the maximum for the conventional RA code. However, the coding rate can be made larger than “1/2” by setting the unit k for adding the parity to k ≧ 2. Therefore, the encoding device 1 can perform high-performance encoding at a desired high encoding rate.
[0054]
On the other hand, the decoding device 3 is configured to perform so-called iterative decoding as shown in FIG. Here, in order to simplify the description, the one corresponding to the one in which the coding rate is “2/3” by the parity check encoder 10 in the coding apparatus 1 is shown.
[0055]
As shown in the figure, the decoding device 3 is inputted with soft output decoding circuits 40 and 90 which are first soft output decoding means and second soft output decoding means for performing soft-output decoding. Deinterleaver 50 that is reverse replacement means for restoring the order of data, interleaver 60 that is second replacement means for rearranging the order of input data, and first rate conversion that performs clock rate conversion and the like A rate conversion circuit 70 that is a means, a rate conversion circuit 80 that is also a second rate conversion means that performs clock rate conversion, and a binarization circuit 100 that is a binarization means that binarizes input data. Is provided. This decoding device 3 estimates the input data D1 in the encoding device 1 from the received value D5 which is an analog value and is made soft-input due to the influence of noise generated on the memoryless communication path 2, and decodes it. Output as data D13.
[0056]
The soft output decoding circuit 40 is provided corresponding to the accumulator 30 in the encoding device 1. The soft output decoding circuit 40 performs calculation by holding these probabilities as direct values based on the passing probability of each state on the trellis in the accumulator 30 and the receiving probability of the output of each branch that transits between the states [Bahl, Cocke, Jelinek and Raviv, “Optimal decoding of linear codes for minimizing symbol error rate”, IEEE Trans. Inf. Theory, vol. IT-20, pp. 284-287, Mar. 1974 ”BCJR (Bahl , Cocke, Jelinek and Raviv), and this BCJR algorithm, which treats probabilities in log-likelihood form with log-likelihood notation “Robertson, Villebrun and Hoeher,“ A comparison of optimal and sub-optimal MAP decoding algorithms operating in the domain ”, IEEE Int. Conf. on Communications, pp. 1009-1013, June 1995”, Max-Log-MAP algorithm or Log-MAP algorithm (hereinafter referred to as Max-Log-). . Referred to as CJR algorithm or Log-BCJR algorithm maximum a posteriori (Maximum A Posteriori probability based on);. Hereinafter, referred to as MAP) perform decoding.
[0057]
Here, when the soft output decoding circuit 40 treats the probability in the form of log likelihood using the natural logarithm and treats it in the form of log likelihood, for example, as shown in FIG. A converter 41 that converts the log likelihood into a log likelihood, a MAP decoder 42 that performs MAP decoding, and three subtractors 43, 44, and 45.
[0058]
When receiving the received value D5 that is a soft input, the converter 41 converts the received value D5 into a probability log likelihood. When the converter 41 handles a probability log likelihood ratio (log likelihood ratio), which is a log likelihood notation of the probability ratio, for example, as a probability log likelihood, the probability log likelihood ratio is calculated for each received value D5. Ask. The converter 41 supplies the probability log likelihood D14 obtained by the conversion to the MAP decoder 42.
[0059]
The MAP decoder 42 includes a probability log likelihood D14 that is a soft input supplied from the converter 41 and a priori probability information for 3 information bits that are a soft input supplied from the interleaver 60. D6₁, D6₂, D6_ThreeMAP decoding is performed, and posterior probability information (a posteriori probability information) D15 for three information bits based on the probability log likelihood D14₁, D15₂, D15_ThreeIs generated. The MAP decoder 42 generates the generated posterior probability information D15.₁To the differentiator 43 and the generated posterior probability information D15₂And the generated posterior probability information D15._ThreeIs supplied to the differentiator 45.
[0060]
The subtractor 43 is posterior probability information D15 that is regarded as a soft input.₁And prior probability information D6 that is soft input₁And 1-bit external information D7 of external information (extrinsic information) D7 for the 3-bit information bits obtained from the constraint condition of the code.₁As a soft output to the subsequent deinterleaver 50.
[0061]
The subtractor 44 has posterior probability information D15 that is regarded as a soft input.₂And prior probability information D6 that is soft input₂And 1-bit external information D7 of the external information D7 with respect to the 3-bit information bits obtained by the constraint condition of the code.₂As a soft output to the subsequent deinterleaver 50.
[0062]
The subtractor 45 is posterior probability information D15 that is regarded as a soft input._ThreeAnd prior probability information D6 that is soft input_ThreeAnd 1-bit external information D7 of the external information D7 with respect to the 3-bit information bits obtained by the constraint condition of the code._ThreeAs a soft output to the subsequent deinterleaver 50.
[0063]
Such a soft output decoding circuit 40 receives the soft input received word D5 received by the receiving device, and also inputs prior probability information D6 for the soft input information bits supplied from the interleaver 60. MAP decoding is performed using received value D5 and prior probability information D6, and soft output decoding of the inner code, that is, the code encoded by accumulator 30 in encoding apparatus 1 is performed. The soft output decoding circuit 40 generates external information D7 obtained by the code constraint condition, and supplies the external information D7 to the subsequent deinterleaver 50 as a soft output.
[0064]
For specific explanation, if u is an information bit, c is a sign bit, and y is a received value D5, the soft output decoding circuit 40 sends the received word D5 (y) to the MAP decoder 42 and Prior probability information D6 (L (u)) expressed by equation (9) is input.
[0065]
[Equation 9]

[0066]
That is, the soft output decoding circuit 40 determines that the received word D5 (y), the probability Pr {u = 1} that the information bit u is “1”, and the information bit u are “0” with respect to the MAP decoder 42. Prior probability information D6 (L (u)) having no code constraint condition represented by the natural logarithm of the ratio to a certain probability Pr {u = 0} is input.
[0067]
Subsequently, the soft output decoding circuit 40 performs MAP decoding by the MAP decoder 42, and performs posterior probability information D15 (L^*(U)) is generated.
[0068]
[Expression 10]

[0069]
That is, the soft output decoding circuit 40 receives the probability Pr {u = 1 | y} that the information bit u is “1” when the received word D5 (y) is received by the MAP decoder 42, and the received word D5 ( a posteriori probability information D15 (L) based on the constraint condition of the sign represented by the natural logarithm of the ratio with the probability Pr {u = 0 | y} that the information bit u is “0” when receiving y)^*(U)) is generated. This posterior probability information D15 (L^*Here, (u)) indicates the likelihood of the information bit u when the received word D5 (y) is received.
[0070]
Then, the soft output decoding circuit 40 uses the subtractors 43, 44, and 45 to calculate the posterior probability information D15 (L^*(U)) and external information D7 (L) which is a difference value between prior probability information D6 (L (u))_e(U)) is obtained.
[0071]
## EQU11 ##

[0072]
The soft output decoding circuit 40 generates the external information D7 in this way, and outputs this external information D7 to the subsequent deinterleaver 50 as a soft output. The external information D7 corresponds to the interleaved data D3 interleaved by the interleaver 20 in the encoding device 1.
[0073]
The deinterleaver 50 is supplied from the soft output decoding circuit 40 so as to return the bit arrangement of the interleaved data D3 interleaved by the interleaver 20 in the encoding apparatus 1 to the original bit arrangement of the encoded data D2. Deinterleaving is performed on the soft-input external information D7. The deinterleaver 50 supplies the data D8 obtained by the deinterleaving to the subsequent rate conversion circuit 70.
[0074]
The interleaver 60 performs interleaving on the data D12 supplied from the rate conversion circuit 80 based on the same replacement position information as the interleaver 20 in the encoding device 1. The interleaver 60 outputs the data obtained by the interleaving as prior probability information D6 for the information bits in the soft output decoding circuit 40.
[0075]
The rate conversion circuit 70 converts the clock rate of the data D8 supplied from the deinterleaver 50 in order to absorb the difference in operation speed between the soft output decoding circuit 40 and the soft output decoding circuit 90. Specifically, the rate conversion circuit 70 is composed of a memory (not shown). For example, when the operation speed of the soft output decoding circuit 40 is four times the operation speed of the soft output decoding circuit 90, the input data D8 Is held in the memory, so that the input data D8 is held in the memory in accordance with the difference in operation speed between the soft output decoding circuit 40 and the soft output decoding circuit 90, such that the clock rate is ¼ times. The clock rate is converted. The rate conversion circuit 70 outputs the data after the clock rate conversion as prior probability information D9 for the code bit in the soft output decoding circuit 90 at the subsequent stage.
[0076]
Similar to the rate conversion circuit 70, the rate conversion circuit 80 is for absorbing a difference in operation speed between the soft output decoding circuit 40 and the soft output decoding circuit 90. The clock rate of the external information D11 for the input sign bit is converted. The rate conversion circuit 80 supplies the data D12 after the clock rate conversion to the subsequent interleaver 60.
[0077]
The soft output decoding circuit 90 is provided corresponding to the parity check encoder 10 in the encoding device 1. The soft output decoding circuit 90 receives the prior probability information D9 for the 3-bit soft input code bit output from the data conversion circuit 70, and although not shown, is a 2-bit information bit having a value of “0” The prior probability information is input, and MAP decoding is performed using the prior probability information, and soft output decoding of the outer code, that is, the code encoded by the parity check encoder 10 in the encoding device 1 is performed. Actually, the soft output decoding circuit 90 performs MAP decoding by performing the following operation. Here, for simplicity of explanation, a binary code will be described as an example. That is, the soft output decoding circuit 90 uses the external information given from the code by the accumulator 30 in the encoding apparatus 1 as prior probability information, and calculates the posterior probability information for each codeword symbol having a total of 3 bits for each parity check code. To do.
[0078]
Here, when the soft output decoding circuit 90 treats the prior probability information D9 in logarithmic likelihood format and treats it in the form of log likelihood, as shown in FIG. 8, three arithmetic circuits 91 and 92 which are arithmetic means are used. , 93 and two adders 94, 95. The arithmetic circuits 91, 92, and 93 perform arithmetic operations described in “Robert G. Gallager,“ Low-density parity-check codes ”, MIT Press, 1963, respectively. Assuming that $ "is expressed, an operation defined as the following equation (12) and the following equation (13) is performed on the variables A and BεR → R. Note that log in the following equations (12) and (13) represents a natural logarithm with the number e of nepia as the base.
[0079]
[Expression 12]

[0080]
[Formula 13]

[0081]
The arithmetic circuit 91 includes the second-bit prior probability information D9 among the 3-bit prior probability information D9.₂And prior probability information D9 of the third bit_ThreeAre used to perform the operation represented by the operator “$”, and the obtained result is supplied to the adder 94 and the external information D11 of the first bit of the external information D11 for the 3 bits of the sign bit is used.₁As a soft output to the rate conversion circuit 80.
[0082]
The arithmetic circuit 92 includes the first-bit prior probability information D9 among the 3-bit prior probability information D9.₁And prior probability information D9 of the third bit_ThreeAre used to perform the operation represented by the operator “$”, and the obtained result is supplied to the adder 95, and the external information D11 of the second bit of the external information D11 with respect to the 3-bit code bit is used.₂As a soft output to the rate conversion circuit 80.
[0083]
The arithmetic circuit 93 includes the first-bit prior probability information D9 out of the 3-bit prior probability information D9.₁And second-bit prior probability information D9₂And the operation represented by the operator “$” is performed, and the obtained result is used as the third bit external information D11 of the three bits of the external information D11._ThreeAs a soft output to the rate conversion circuit 80.
[0084]
The adder 94 includes prior probability information for an information bit whose value (not shown) is “0”, and prior probability information D9.₁And external information D11 supplied from the arithmetic circuit 91₁And the obtained result is the external information D10 of the first bit of the external information D10 for the two information bits.₁As a soft output to the binarization circuit 100 in the subsequent stage.
[0085]
The adder 95 includes prior probability information for an information bit whose value (not shown) is “0”, and prior probability information D9.₂And external information D11 supplied from the arithmetic circuit 92₂And the obtained result is the external information D10 of the second bit of the external information D10 for the two information bits.₂As a soft output to the binarization circuit 100 in the subsequent stage.
[0086]
Such a soft output decoding circuit 90 inputs prior probability information for an information bit having a value “0” (not shown) and soft input prior probability information D9 supplied from the rate conversion circuit 70, and inputs these prior probability information D9. By performing MAP decoding using the probability information, external information D10 and D11 obtained by the constraint condition of the code are generated, and the external information D10 is supplied to the binarization circuit 100 as a soft output, and the external information D11 is rate-converted. A soft output is supplied to the conversion circuit 80.
[0087]
In other words, the soft output decoding circuit 90 calculates, as each bit of the external information for the code bit to be generated, a bit other than the input corresponding to its own bit from the soft input prior probability information supplied from the rate conversion circuit 70. Among the soft input prior probability information supplied from the rate conversion circuit 70 as external information for the information bits to be generated by performing the operation represented by the operator “$” between the input bits other than the input corresponding to its own bit The result of the operation represented by the operator “$” performed between the bits, the input corresponding to the self bit, and the prior probability information for the information bit whose value is “0” are added. In other words, the soft-output decoding circuit that performs soft-output decoding of the outer code sets the prior probability information for the information bits to “APP” and sets the prior probability information for the code bits to “R”._k", The encoding device 1 performs the operation shown in the following equation (14) according to the unit to which the parity is added, generates external information (EX) for the code bit, and performs the operation shown in the following equation (15). To generate external information (DEC) for the information bits.
[0088]
[Expression 14]

[0089]
[Expression 15]

[0090]
By the way, for the above-described operator “$”, the theorem shown in the following equation (16) holds. However, the function f in the following equation (16) is expressed by the following equation (17) with the positive number x as a variable.
[0091]
[Expression 16]

[0092]
[Expression 17]

[0093]
In the above equation (16), “sgn” is the variable A_iThe symbol “| A”_i| ”Is the variable A_iThe absolute value of is shown.
[0094]
Thus, the operation represented by the operator “$” can be realized by conversion and addition by the function f. Here, as shown in FIG. 9, the function f is a decreasing function that is given in the first quadrant and gradually approaches 0 as the variable x increases, and the relationship with the variable x is stored in advance as a table in a ROM or the like, for example. It can be implemented by various methods such as approximating the relationship with the variable x by so-called linear approximation or threshold approximation. The function f is a variable A_iCan be stored in a combination of a sign and an absolute value (signed magnitude format) in, for example, a RAM (Random Access Memory) or the like, thereby realizing a simpler implementation with a small amount of calculation.
[0095]
From this, the arithmetic circuits 91, 92, and 93 obtain the relationship between the function f and the variable x described above by referring to a table stored in a ROM (not shown), and are shown in the above equation (16). The calculation may be performed, or the relationship between the function f and the variable x may be approximated by linear approximation or threshold approximation. Further, the arithmetic circuits 91, 92, 93 each have a variable A in the function f held in a RAM (not shown)._iThe calculation shown in the above equation (16) may be performed using a combination of the sign and the absolute value.
[0096]
The binarization circuit 100 binarizes the external information D10 supplied from the soft output decoding circuit 90, and outputs it as hard-output decoded data D13.
[0097]
Such a decoding apparatus 3 includes soft output decoding circuits 40 and 90 corresponding to the accumulator 30 and the parity check encoder 10 in the encoding apparatus 1, so that a code having a high decoding complexity is reduced in complexity. It can be decomposed into elements and the characteristics can be sequentially improved by the interaction between the soft output decoding circuits 40 and 90. When receiving the received value D5, the decoding device 3 repeats the decoding operation of the soft output decoding circuit 40 to the soft output decoding circuit 90 a predetermined number of times, for example, several times to several tens of times, and performs a predetermined number of decoding operations. The decoded data D13 is output based on the soft output external information D10 obtained as a result of the above.
[0098]
Thus, the decoding device 3 can decode the PA code encoded by the encoding device 1 with high accuracy by iterative decoding.
[0099]
Next, a data transmission / reception system shown as the second embodiment will be described with reference to FIGS.
[0100]
This data transmission / reception system includes an encoding device 1 ′ shown in FIG. 10 instead of the above-described encoding device 1, and a code encoded by the encoding device 1 ′ is decoded by a decoding device 3 ′ described later. Is. In this data transmission / reception system, the encoding device 1 'further improves the above-described encoding by the PA code, and changes the unit of information to which the parity is added according to an arbitrary distribution.
[0101]
Note that the encoding apparatus 1 ′ shown in FIG. 10 has a basic configuration similar to that of the encoding apparatus 1 shown in FIG. 2, and has a setting unit 110. Therefore, the same components as those of the encoding device 1 shown in FIG. 2 are denoted by the same reference numerals, and detailed description thereof is omitted.
[0102]
As shown in FIG. 10, the encoding device 1 ′ includes, in addition to the interleaver 20 and the accumulator 30 described above, a parity check encoder 10 ′ and information for adding parity in the parity check encoder 10 ′. And a setting device 110 which is setting means for setting the distribution of units.
[0103]
Similar to the parity check encoder 10 described above, the parity check encoder 10 'adds 1-bit parity to the input data in predetermined bit units. Specifically, when the parity check encoder 10 ′ receives the input data D1, the parity check encoder 10 ′ receives a 1-bit parity for the input data D1 in a predetermined bit unit based on the control signal S supplied from the setting unit 110. Is output to the interleaver 20 at the subsequent stage as encoded data D2. Here, the unit for adding the parity changes according to the control signal S supplied from the setting device 110. This unit will be described in detail later.
[0104]
The setting unit 110 sets a distribution of units for adding parity in the parity check encoder 10 ', and supplies a control signal S indicating the setting contents to the parity check encoder 10'. Specifically, the setting unit 110 sets the ratio of adding 1-bit parity in the i-bit unit of the input data D1 to the total number of bits of the encoded data D2._iThen, the distribution of units for adding parity to the input data D1 is set so as to satisfy the following expressions (18) and (19).
[0105]
[Expression 18]

[0106]
[Equation 19]

[0107]
In order to explain more specifically, consider a case where the parity check encoder 10 'performs encoding with an encoding rate R of "4/5". Here, for example, as shown in FIG. 11A, if the total number of bits of the encoded data D2 generated by the parity check encoder 10 ′ is 50000 bits, the total number of bits of the input data D1 is encoded. Since the rate R is “4/5”, it becomes 40000 bits as shown in FIG.
[0108]
At this time, the parity check encoder 10 ′ performs encoding that adds 1-bit parity in units of i = 3 bits and encoding that adds 1-bit parity in units of i = 5 bits. As shown in FIG. 5A, 2/5 bits of the encoded data D2 of 50000 bits, that is, 20000 bits are generated by parity check encoding in units of 3 bits, and the remaining 3/5 , That is, 30000 bits may be generated by parity check encoding in units of 5 bits.
[0109]
Here, as shown in FIG. 5B, in order to generate 20000 bits of encoded data D2 by parity check encoding in units of 3 bits, 20000 × 3 / (3 + 1) of input data D1. = 15000 bits are required, and 30000 bits of the encoded data D2 are generated by parity check encoding in units of 5 bits, and 30000 × 5 / (5 + 1) = 25000 bits of the input data D1 are required. Will do.
[0110]
Accordingly, the setting unit 110 performs parity check encoding on 15000 bits in 3 bits of the 40000-bit input data D1 and parity check on 25000 bits in 5 bits for the parity check encoder 10 ′. A control signal S indicating that encoding is to be performed is supplied.
[0111]
As described above, the setting unit 110 applies the input data D1 to the input data D1 according to the total number of bits of the input data D1, the coding rate of the encoding to be performed by the parity check encoder 10 ′, and the unit for adding the parity. A distribution of units to which the parity is added is set, and a control signal S indicating the setting content is supplied to the parity check encoder 10 ′.
[0112]
The distribution of the unit for adding the parity may be arbitrary with respect to the total bits of the input data D1, for example, in the case of the example of FIG. 11, the first 15000 bits of the input data D1 are expressed in units of 3 bits. Parity check encoding may be performed, and the remaining 25,000 bits may be parity check encoded in units of 5 bits, or other combinations may be used.
[0113]
Such an encoding apparatus 1 ′ performs parity check encoding with an arbitrary coding rate “R (<1)” as an outer code encoding by the parity check encoder 10 ′, and an inner code by the accumulator 30. By performing recursive convolution operation with a coding rate of “1” as encoding of the above, as a whole, column concatenated coding with a code of coding rate “R × 1 = R” is performed. The data encoded by the encoding device 1 is subjected to signal point mapping based on a predetermined modulation method by a modulator (not shown), and is output to the receiving device via the memoryless communication path 2.
[0114]
In this way, the encoding device 1 ′ changes the unit for adding parity in the parity check encoder 10 ′ according to an arbitrary distribution, so that the PA code shown in the first embodiment is encoded. Since the unit of parity addition uniquely determined according to the coding rate can be different for each arbitrary unit of the input data D1, the coding rate can be set to a desired value close to “1”. It is possible to perform higher-performance encoding under the desired high encoding rate. There are various methods for determining the distribution of the parity-added units set by the setting device 110. For example, by changing the distribution of the parity-added units from the case of a normal PA code, You may make it search for the distribution from which performance is acquired.
[0115]
On the other hand, the decoding device 3 ′ is configured to perform so-called iterative decoding as shown in FIG. 12. Here, in order to simplify the description, the parity check encoder 10 ′ in the encoding device 1 ′ performs encoding that adds 1-bit parity in units of i = 3 bits, and i = 5 bits. The code corresponding to the one that performs coding with 1-bit parity added and performs the coding rate of “4/5” is shown.
[0116]
Further, the decoding apparatus 3 ′ shown in the figure has the same basic configuration as that of the decoding apparatus 3 shown in FIG. 6, and a plurality of units corresponding to the units to which the parity check encoder 10 ′ in the encoding apparatus 1 ′ adds parity. The soft output decoding circuit is provided. Therefore, the same components as those of the decoding device 3 shown in FIG. 6 are denoted by the same reference numerals, and detailed description thereof is omitted.
[0117]
As shown in FIG. 12, the decoding device 3 ′ performs clock rate conversion and the like in addition to the soft output decoding circuit 40, the deinterleaver 50, the interleaver 60, and the binarization circuit 100 described above. The rate conversion circuit 70 'as the first rate conversion means and distribution means, the rate conversion circuit 80' as the second rate conversion means for converting the clock rate, and the parity by the parity check encoder 10 ' Two soft output decoding circuits 90 which are second soft output decoding means for performing soft output decoding according to the unit to be added.₁, 90₂These soft output decoding circuits 90₁, 90₂And a change-over switch 120 for switching and outputting the data supplied from. This decoding device 3 ′ estimates the input data D1 in the encoding device 1 ′ from the received value D5 which is an analog value and is soft input due to the influence of noise generated on the memoryless communication path 2, and as decoded data D23 Output.
[0118]
The rate conversion circuit 70 ′ includes a soft output decoding circuit 40 and a soft output decoding circuit 90.₁, 90₂In order to absorb the difference in operating speed, the clock rate of the data D8 supplied from the deinterleaver 50 is converted. Further, the rate conversion circuit 70 ′ converts the data after the clock rate conversion into the subsequent soft output decoder 90.₁, 90₂It also has a function of distributing to each other.
[0119]
Specifically, as shown in FIG. 13, the rate conversion circuit 70 ′ includes a memory 71 that holds data D8 for converting the clock rate, a control unit 72 that controls the operation of a changeover switch 73 described later, A change-over switch 73 for selecting data having a clock rate converted from the memory 71 and ten latches 74 for latching the data selected by the change-over switch 73.₁74₂74_Three74_Four74_Five74₆74₇74₈74₉74_TenAnd have.
[0120]
In such a rate conversion circuit 70 ', for example, the operation speed of the soft output decoding circuit 40 is such that the soft output decoding circuit 90' operates.₁, 90₂If the input data D8 is held in the memory 71, the input data D8 and the soft output decoding circuit 40 are converted to a quarter of the clock rate. Soft output decoding circuit 90₁, 90₂The clock rate is converted by holding it in the memory 71 according to the difference in operating speed. Subsequently, the rate conversion circuit 70 ′ is generated by the control unit 72 with the data held in the memory 71 added with parity in i-bit units by the parity check encoder 10 ′ in the encoding device 1 ′. It is determined which bit corresponds to the i + 1 bits, the changeover switch 73 is operated under the control of the control unit 72, and the data supplied from the memory 71 is stored in each latch 74.₁74₂74_Three74_Four74_Five74₆74₇74₈74₉74_TenTo distribute. The rate conversion circuit 70 'then latches 74 when the unit for adding parity in the parity check encoder 10' is i = 3.₁74₂74_Three74_Four, 4 bits of data are latched one bit at a time, and each bit is latched in the subsequent soft output decoding circuit 90.₁Prior probability information D16 for the sign bit in₁, D16₂, D16_Three, D16_FourOutput as. Further, the rate conversion circuit 70 ′ latches 74 when the unit for adding parity in the parity check encoder 10 ′ is i = 5._Five74₆74₇74₈74₉74_Ten6-bit data is latched one bit at a time, and each bit is latched by a soft output decoding circuit 90 in the subsequent stage.₂Prior probability information D17 for the sign bit in₁, D17₂, D17_Three, D17_Four, D17_Five, D17₆Output as.
[0121]
The rate conversion circuit 80 'is similar to the rate conversion circuit 70' in the soft output decoding circuit 40 and the soft output decoding circuit 90.₁, 90₂And the soft output decoding circuit 90.₁External information D19 or soft output decoding circuit 90 for the sign bit which is the soft input supplied from₂The clock rate of the external information D21 is converted with respect to the sign bit that is the soft input supplied from. The rate conversion circuit 80 ′ supplies the data D <b> 12 after the clock rate conversion to the subsequent interleaver 60.
[0122]
Soft output decoding circuit 90₁Is provided corresponding to the parity check encoder 10 ′ in the encoding device 1, and decodes the parity check encoded code by adding 1 bit parity in units of i = 3 bits. is there. Soft output decoding circuit 90₁Inputs the prior probability information D16 for the sign bit of the soft input output from the data conversion circuit 70 ′ and inputs the prior probability information for the information bit whose value is “0” (not shown). MAP decoding is performed using the probability information, and soft output decoding of the outer code is performed.
[0123]
Here, the soft output decoding circuit 90₁When the prior probability information D16 is expressed in logarithmic likelihood and handled in the logarithmic likelihood format, as shown in FIG.₁, 92₁, 93₁, 94₁And three adders 95₁, 96₁, 97₁It can implement | achieve as what has. The arithmetic circuit 91₁, 92₁, 93₁, 94₁Respectively perform operations defined as in the above equation (12) and the above equation (13).
[0124]
Arithmetic circuit 91₁Of the 4-bit prior probability information D16, the second-bit prior probability information D16₂And prior probability information D16 of the third bit_ThreeAnd the fourth bit prior probability information D16_FourAnd the operation represented by the operator “$” is performed, and the obtained result is added to the adder 95.₁And external information D19 of the first bit of the external information D19 with respect to the 4-bit code bit₁As a soft output to the rate conversion circuit 80 '.
[0125]
Arithmetic circuit 92₁Of the 4-bit prior probability information D16, the first-bit prior probability information D16₁And prior probability information D16 of the third bit_ThreeAnd the fourth bit prior probability information D16_FourAnd the operation represented by the operator “$” is performed, and the obtained result is added to the adder 96.₁And external information D19 of the second bit of the external information D19 with respect to the 4-bit code bit₂As a soft output to the rate conversion circuit 80 '.
[0126]
Arithmetic circuit 93₁Of the 4-bit prior probability information D16, the first-bit prior probability information D16₁And prior probability information D16 of the second bit₂And the fourth bit prior probability information D16_FourAnd the operation represented by the operator “$” is performed, and the obtained result is added to the adder 97.₁And external information D19 of the third bit of the external information D19 for the 4-bit code bit_ThreeAs a soft output to the rate conversion circuit 80 '.
[0127]
Arithmetic circuit 94₁Of the 4-bit prior probability information D16, the first-bit prior probability information D16₁And prior probability information D16 of the second bit₂And prior probability information D16 of the third bit_ThreeAnd the operation represented by the operator “$” is performed, and the obtained result is used as the fourth bit external information D19 of the four bits of the external information D19._FourAs a soft output to the rate conversion circuit 80 '.
[0128]
Adder 95₁Are prior probability information for information bits whose values are not shown in the figure, and prior probability information D16.₁And the arithmetic circuit 91₁External information D19 supplied from₁And the obtained result is the external information D18 of the first bit of the external information D18 for the 3-bit information bits.₁As a soft output to the selected terminal a.
[0129]
Adder 96₁Are prior probability information for information bits whose values are not shown in the figure, and prior probability information D16.₂And an arithmetic circuit 92₁External information D19 supplied from₂And the obtained result is the external information D18 of the second bit of the external information D18 with respect to the information bits of 3 bits.₂As a soft output to the selected terminal a.
[0130]
Such a soft output decoding circuit 90₁Inputs prior probability information for an information bit whose value is “0” (not shown) and soft input prior probability information D16 supplied from the rate conversion circuit 70 ′, and uses these prior probability information to perform MAP decoding. To generate external information D18 and D19 obtained by the constraint condition of the code, supply the external information D18 to the selected terminal a as a soft output, and also convert the external information D19 to the rate conversion circuit 80 ′ as a soft output. Supply.
[0131]
Soft output decoding circuit 90₂Is provided corresponding to the parity check encoder 10 ′ in the encoding device 1, and decodes the parity check encoded code by adding 1 bit parity in units of i = 5 bits. is there. Soft output decoding circuit 90₂Inputs the prior probability information D17 for the sign bit of the soft input output from the data conversion circuit 70 ′ and inputs the prior probability information for the information bit whose value is “0” (not shown). MAP decoding is performed using the probability information, and soft output decoding of the outer code is performed.
[0132]
Here, the soft output decoding circuit 90₂When the prior probability information D17 is expressed in logarithmic likelihood and handled in the form of log likelihood, as shown in FIG. 15, six arithmetic circuits 91 as arithmetic means are used.₂, 92₂, 93₂, 94₂, 95₂, 96₂And five adders 97₁, 98₁, 99₁, 100₁, 101₁It can implement | achieve as what has. The arithmetic circuit 91₂, 92₂, 93₂, 94₂, 95₂, 96₂Respectively perform operations defined as in the above equation (12) and the above equation (13).
[0133]
Arithmetic circuit 91₂Of the 6-bit prior probability information D17, the second-bit prior probability information D17₂And prior probability information D17 of the third bit_Three4th bit prior probability information D17_FourAnd 5th bit prior probability information D17_FiveAnd prior probability information D17 of the 6th bit₆And the operation represented by the operator “$” is performed, and the obtained result is added to the adder 97.₂And external information D21 of the first bit of the external information D21 for 6-bit code bits₁As a soft output to the rate conversion circuit 80 '.
[0134]
Arithmetic circuit 92₂Of the 6-bit prior probability information D17, the first-bit prior probability information D17₁And prior probability information D17 of the third bit_Three4th bit prior probability information D17_FourAnd 5th bit prior probability information D17_FiveAnd prior probability information D17 of the 6th bit₆And the operation represented by the operator “$” is performed, and the obtained result is added to the adder 98.₂And external information D21 of the second bit of the external information D21 with respect to the 6-bit code bit₂As a soft output to the rate conversion circuit 80 '.
[0135]
Arithmetic circuit 93₂Of the 6-bit prior probability information D17, the first-bit prior probability information D17₁And prior probability information D17 of the second bit₂4th bit prior probability information D17_FourAnd 5th bit prior probability information D17_FiveAnd prior probability information D17 of the 6th bit₆And the operation represented by the operator “$” is performed, and the obtained result is added to the adder 99.₂And external information D21 of the third bit of the external information D21 for 6-bit code bits_ThreeAs a soft output to the rate conversion circuit 80 '.
[0136]
Arithmetic circuit 94₂Of the 6-bit prior probability information D17, the first-bit prior probability information D17₁And prior probability information D17 of the second bit₂And prior probability information D17 of the third bit_ThreeAnd 5th bit prior probability information D17_FiveAnd prior probability information D17 of the 6th bit₆And the operation represented by the operator “$” is performed, and the obtained result is added to the adder 100.₂And external information D21 of the fourth bit among the external information D21 for the 6-bit code bits._FourAs a soft output to the rate conversion circuit 80 '.
[0137]
Arithmetic circuit 95₂Of the 6-bit prior probability information D17, the first-bit prior probability information D17₁And prior probability information D17 of the second bit₂And prior probability information D17 of the third bit_Three4th bit prior probability information D17_FourAnd prior probability information D17 of the 6th bit₆And the operation represented by the operator “$” is performed, and the obtained result is added to the adder 101.₂And external information D21 of the fifth bit of the external information D21 with respect to the 6-bit code bit._FiveAs a soft output to the rate conversion circuit 80 '.
[0138]
Arithmetic circuit 96₂Of the 6-bit prior probability information D17, the first-bit prior probability information D17₁And prior probability information D17 of the second bit₂And prior probability information D17 of the third bit_Three4th bit prior probability information D17_FourAnd 5th bit prior probability information D17_FiveAnd the operation represented by the operator “$” is performed, and the obtained result is used as the sixth bit external information D21 of the six bits of the external information D21.₆As a soft output to the rate conversion circuit 80 '.
[0139]
Adder 97₂Are prior probability information for information bits whose values are not shown in the figure, and prior probability information D17.₁And the arithmetic circuit 91₂External information D21 supplied from₁And the obtained result is the external information D20 of the first bit of the external information D20 for the 5-bit information bits.₁As a soft output to the selected terminal b.
[0140]
Adder 98₂Are prior probability information for information bits whose values are not shown in the figure, and prior probability information D17.₂And an arithmetic circuit 92₂External information D21 supplied from₂And the obtained result is the external information D20 of the second bit of the external information D20 for the information bits of 5 bits.₂As a soft output to the selected terminal b.
[0141]
Adder 99₂Are prior probability information for information bits whose values are not shown in the figure, and prior probability information D17._ThreeAnd an arithmetic circuit 93₂External information D21 supplied from_ThreeAnd the obtained result is the third bit of the external information D20 of the external information D20 for the 5 bits of information bits._ThreeAs a soft output to the selected terminal b.
[0142]
Adder 100₂Are prior probability information for information bits whose values are not shown in the figure, and prior probability information D17._FourAnd the arithmetic circuit 94₂External information D21 supplied from_FourAnd the obtained result is the fourth bit external information D20 of the external information D20 for the five information bits._FourAs a soft output to the selected terminal b.
[0143]
Adder 101₂Are prior probability information for information bits whose values are not shown in the figure, and prior probability information D17._FiveAnd an arithmetic circuit 95₂External information D21 supplied from_FiveAnd the obtained result is the fifth bit external information D20 of the external information D20 for the five information bits._FiveAs a soft output to the selected terminal b.
[0144]
Such a soft output decoding circuit 90₂Inputs prior probability information for an information bit whose value is “0” (not shown) and soft input prior probability information D17 supplied from the rate conversion circuit 70 ′, and uses these prior probability information to perform MAP decoding. To generate external information D20 and D21 determined by the constraint condition of the code, supply the external information D20 as a soft output to the selected terminal b, and set the external information D21 as a soft output to the rate conversion circuit 80 ′. Supply.
[0145]
The changeover switch 120 operates under the control of a control unit (not shown), and the soft output decoding circuit 90.₁When the decoded data D23 is output based on the external information D18 output from, the external data D18 is connected to the selected terminal a and supplied to the binarization circuit 100 as the external information D22. The changeover switch 120 includes a soft output decoding circuit 90.₂When the decoded data D23 is output based on the external information D20 output from, the external terminal D is connected to the selected terminal b, and the external information D20 is supplied to the binarization circuit 100 as the external information D22.
[0146]
When such a decoding device 3 ′ receives the received value D 5, the soft output decoding circuit 40 to the soft output decoding circuit 90 are input.₁, 90₂The decoding operation is repeatedly performed a predetermined number of times, for example, several times to several tens of times, and the decoded data D23 is output based on the soft output external information D22 obtained as a result of the predetermined number of decoding operations.
[0147]
As described above, the decoding device 3 ′ can decode the code by the parity check encoder 10 ′ in which the unit for adding the parity is changed, and the code encoded by the encoding device 1 ′ is repeatedly decoded. It can be decoded with high accuracy.
[0148]
As described above, in a data transmission / reception system configured using an encoding device and a decoding device, k / (k + 1) is obtained by performing parity check encoding using a parity check encoder in the encoding device. It is possible to perform high-performance encoding under a desired high encoding rate that is expressed, and it is possible to decode a code by a parity check encoder in a decoding device.
[0149]
In addition, the data transmission / reception system changes the parity addition unit in the parity check encoder in accordance with an arbitrary distribution in the encoding device, so that the data transmission / reception system has a higher encoding rate under a desired high encoding rate close to “1”. The performance can be encoded, and the decoding apparatus can perform decoding according to the unit of parity addition in the parity check encoder.
[0150]
That is, a data transmission / reception system configured using these encoding devices and decoding devices realizes a high-performance encoding and decoding system and can provide high reliability to the user. is there.
[0151]
Note that the present invention is not limited to the above-described embodiment. For example, as an accumulator in an encoding apparatus, two exclusive OR circuits 31 as shown in FIG.₁', 31₂'And two shift registers 32₁', 32₂The number of states may be other than “2”, such as an accumulator 30 ′ including “′”.
[0152]
Further, in the above-described embodiments, the encoding apparatus is described as including an accumulator as an inner code element encoder. However, the present invention is not necessarily an accumulator, and a code for performing arbitrary encoding. It is also applicable to a generator.
[0153]
Furthermore, in the above-described embodiment, the coding apparatus has been described as including a parity check encoder as an element encoder that performs coding of the outer code, but the parity check encoder is used to encode the inner code. You may provide as an element encoder which performs.
[0154]
That is, the present invention can be applied to any coding apparatus including at least a parity check encoder. Of course, in this case, it is needless to say that a decoding device corresponding to the encoding device is used.
[0155]
Furthermore, in the first embodiment described above, it is assumed that the soft output decoding circuit that performs soft output decoding of the outer code in the decoding device includes a circuit corresponding to the case where the coding rate is “2/3”. In the second embodiment, the soft output decoding circuit for performing soft output decoding of the outer code corresponds to the case where encoding is performed by adding parity in units of i = 3 bits, and the parity is set to i = 5. Although it has been described that it is provided with a unit corresponding to the case where encoding is performed in units of bits, the present invention can be applied to any unit of parity addition in the encoding apparatus, and accordingly The soft output decoding circuit in the decoding apparatus can also be applied only by using the number and configuration corresponding to the parity addition unit of the parity check coding.
[0156]
Further, in the above-described embodiment, as a soft output decoding circuit that performs soft output decoding of an outer code in a decoding device, “i + 1” arithmetic circuits and i number of units are added using a parity addition unit i of parity check coding. Although the present invention has been described as having an adder, the present invention may have other configurations, such as sharing these arithmetic circuits and adders, for example, and the arithmetic circuit and adder are shared. In addition, the circuit scale can be reduced.
[0157]
Further, in the above-described embodiment, the soft output decoding circuit corresponding to the accumulator in the encoding device has been described as performing the MAP decoding based on the BCJR algorithm, the Max-Log-BCJR algorithm, or the Log-BCJR algorithm. The present invention can also be applied to other soft output decoding, for example, decoding by so-called SOVA (Soft Output Viterbi Algorithm).
[0158]
Hereinafter, as a specific example, a description will be given of a new algorithm obtained by improving the BCJR algorithm in which probabilities are expressed in log likelihood and handled in the form of log likelihood.
[0159]
This algorithm has a so-called probability α at time t._t, Β_t, Γ_t, And soft output λ_tLogarithmic likelihood Iα using a natural logarithm_t, Iβ_t, Iγ_tAnd logarithmic soft output Iλ_tAnd at least the probability log likelihood Iα in each state_t, Iβ_tThe decoding is performed using the difference value of the values. The soft output decoding circuit to which this algorithm is applied can reduce the circuit scale and increase the processing speed.
[0160]
In the following, the probability log likelihood Iα expressed in log likelihood_t, Iβ_t, Iγ_tAre described as being probability log likelihood ratios, which are log likelihood representations of probability ratios. In the following, the case where the soft output decoding circuit 40 decodes the code by the accumulator 30 in the encoding apparatus 1 described above will be described.
[0161]
In the BCJR algorithm in which the probability is expressed in log likelihood and handled in the form of log likelihood, if m is the state at time t, the probability log likelihood Iα_t(M), Iβ_tWhat is essentially needed to calculate (m) is the probability log likelihood Iα_t(M), Iβ_tProbability log likelihood Iα, not the value of (m) itself_t(M), Iβ_tThis is a value when (m) is normalized by the sum of values in each state, that is, a difference value between values in each state.
[0162]
Therefore, the soft output decoding circuit 40 has two states S in the accumulator 30.₀, S₁Probability log likelihood Iα for_t(M), Iβ_tInstead of performing the iterative operation of (m), state S₀, S₁The calculation is performed paying attention to the difference value of the values at. Where state S₀Probability log likelihood Iα at time t_t(S₀) "U_t”And state S₁Probability log likelihood Iα at time t_t(S₁) To “V_t”And state S₀Probability log likelihood Iβ at time t_t(S₀) "W_t”And state S₁Probability log likelihood Iβ at time t_t(S₁) To “Z_tReplace with.
[0163]
At this time, prior probability information that corresponds to the above-described prior probability information D6 and is a natural logarithm of the ratio of the probability that the bit input as interleaved data D3 is “1” and the probability that it is “0”. A_tAnd a posteriori probability information for one symbol code bit of the encoded data D4 determined only from the received value D5._tThen, the probability log likelihood Iα in each state_t(M), ie, probability log likelihood U_t, V_tAre represented by the following equations (20) and (21), respectively. The operator “#” in the following expressions (20) and (21) indicates a so-called log-sum operation, and hereinafter, the log-sum operation is represented by the operator “#”. .
[0164]
[Expression 20]

[0165]
[Expression 21]

[0166]
Therefore, the probability log likelihood Iα in each state_tThe difference value of the values of (m), that is, the probability log likelihood U_t, V_tDifference value U_t-V_tIs expanded as shown in the following equation (22) using the above-described operator “$”.
[0167]
[Expression 22]

[0168]
On the other hand, the probability log likelihood Iβ in each state_t(M), ie, probability log likelihood W_t, Z_tRespectively, prior probability information A_tAnd posterior probability information y_tIs expressed by the following formula (23) and the following formula (24).
[0169]
[Expression 23]

[0170]
[Expression 24]

[0171]
Therefore, the probability log likelihood Iβ in each state_tThe difference value of the values of (m), that is, the probability log likelihood W_t, Z_tDifference value W_t-Z_tIs expanded as shown in the following equation (25).
[0172]
[Expression 25]

[0173]
Thus, the above equations (22) and (25), that is, the probability log likelihood Iα in each state_t(M), Iβ_tBoth of the difference values of the value (m) can be expressed using an operation given by the operator “$” and addition.
[0174]
Therefore, the logarithmic soft output Iλ_tIs the probability log likelihood U_t, V_t, W_t, Z_tPrior probability information A_tAnd posterior probability information y_tIs represented by the following formula (26).
[0175]
[Equation 26]

[0176]
In the above equation (26), the second term and the third term on the right side represented by the operator “$” indicate external information corresponding to the above-described external information D7. Thus, the above equation (26), that is, the logarithmic soft output Iλ_tAlso, the probability log likelihood Iα in each state_t(M), Iβ_tSimilar to the difference value of the value of (m), it can be expressed using an operation given by the operator “$” and addition.
[0177]
Therefore, in a normal BCJR algorithm in which probabilities are expressed in log-likelihood notation and handled in the form of log-likelihood, values corresponding to the number of states are held when performing iterative operations for obtaining probabilistic log-likelihoods Iα and Iβ. In this algorithm, the difference value U_t-V_t, W_t-Z_tAnd the values corresponding to “the number of states−1” may be held.
[0178]
Further, in this algorithm, since the difference value is used, there is no need for normalization without causing an overflow of the stored value unlike the normal BCJR algorithm.
[0179]
It should also be noted that this algorithm does not require a log-sum operation. In this algorithm, the difference value U_t-V_t, W_t-Z_tAnd logarithmic soft output Iλ_tIs obtained by performing each operation represented by the operator “$” once.
[0180]
Furthermore, since the operation represented by the operator “$” can be realized by conversion and addition by the function f as shown in the above equations (16) and (17), It is possible to make the implementation simpler and less.
[0181]
From the above discussion, it can be expected to implement the soft output decoding circuit 40 that can reduce the circuit scale and increase the processing speed.
[0182]
Now, the soft output decoding circuit 40 that implements such an algorithm includes each unit as shown in FIGS. Here, in FIG. 17, the probability log likelihood Iα of each part of the soft output decoding circuit 40 is shown._tFIG. 18 shows the probability log likelihood Iβ._tFIG. 19 shows the logarithmic soft output Iλ._tThe part which calculates is shown.
[0183]
Probability log likelihood Iγ_tIs the posterior probability information y_tAnd prior probability information A_tIt is determined by. That is, the probability log likelihood Iγ_tIs the posterior probability information y_tAnd prior probability information A_tAnd posterior probability information y_tIt is the natural logarithm of the probability γ determined by the code output pattern and the posterior probability information for each received value, that is, for each received value. In other words, the soft output decoding circuit 40 performs the probability log likelihood Iγ represented by the matrix shown in FIG._tWill be calculated.
[0184]
The soft output decoding circuit 40 shown in FIG._tAs an Iα calculation circuit for calculating the above, an arithmetic circuit 131 which is an arithmetic means for performing the arithmetic operation represented by the above-described operator “$”, an adder 132, and a register 133 for holding data are provided.
[0185]
The arithmetic circuit 131 uses the prior probability information A_tAnd the difference value U of the probability log likelihood one hour before supplied from the register 133_t-1-V_t-1And the operation represented by the operator “$” is performed. The arithmetic circuit 131 supplies data obtained by the calculation to the adder 132. The arithmetic circuit 131 obtains the relationship between the function f and the variable x described above by referring to a table stored in a ROM (not shown), and performs the calculation shown in the above equation (16). Alternatively, the relationship between the function f and the variable x may be approximated by linear approximation or threshold approximation. The arithmetic circuit 131 also includes a variable A in the function f held in a RAM (not shown)._iThe calculation shown in the above equation (16) may be performed using a combination of the sign and the absolute value.
[0186]
The adder 132 calculates the posterior probability information y_tAnd the data supplied from the arithmetic circuit 131 are added, and the obtained data is supplied to the register 133.
[0187]
The register 133 stores the data supplied from the adder 132, that is, the difference value U of the probability log likelihood._t-V_tHold. The difference value U of the probability log likelihood held in this register 133_t-V_tIs supplied to a memory circuit (not shown).
[0188]
Also, the soft output decoding circuit 40, as shown in FIG._tAs an Iβ calculating circuit for calculating the above, an adder 134, an arithmetic circuit 135 which is an arithmetic means for performing an arithmetic operation represented by an operator “$”, and a register 136 are provided.
[0189]
The adder 134 reads the posterior probability information y read from the memory circuit (not shown)._tAnd the difference value W of the probability log likelihood one hour before supplied from the register 136_t-1-Z_t-1And the obtained data is supplied to the arithmetic circuit 135.
[0190]
The arithmetic circuit 135 reads the prior probability information A read from a memory circuit (not shown)._tAnd the data supplied from the adder 134, the same calculation as the calculation circuit 131 is performed. The arithmetic circuit 135 supplies data obtained by the arithmetic operation to the register 136.
[0191]
The register 136 stores the data supplied from the arithmetic circuit 135, that is, the probability log likelihood difference value W._t-Z_tHold. Difference value W of probability log likelihood held in this register 136_t-Z_tIs supplied to a memory circuit (not shown).
[0192]
Such a soft output decoding circuit 40 includes prior probability information A_tAnd posterior probability information y_tAnd at least the probability log likelihood Iα in each state_t, Iβ_tAs a part of the variable, the calculation shown in the above equation (22) and the above equation (25) is performed, and each state S₀, S₁Probability log likelihood Iα in_t(S₀), Iα_t(S₁) Difference value Iα_t(S₀) -Iα_t(S₁) (= U_t-V_t) And each state S₀, S₁Probability log likelihood Iβ in_t(S₀), Iβ_t(S₁) Difference value Iβ_t(S₀) -Iβ_t(S₁) (= W_t-Z_t) Is calculated. That is, the soft output decoding circuit 40 performs prior probability information A_tAnd posterior probability information y_tPosterior probability information y based on_tEvery time, the difference value of the value in each state of the probability log likelihood Iα, which is the natural logarithm of the probability α that reaches each state from the encoding start state in time series order, is calculated, and The difference value of the value in each state of the probability log likelihood Iβ which is a natural logarithm of the probability β to reach the state is calculated. Then, the soft output decoding circuit 40 calculates the difference value U held in the register 133._t-V_tAnd the difference value W held in the register 136._t-Z_tIs supplied to a memory circuit (not shown).
[0193]
Further, the soft output decoding circuit 40 has a logarithmic soft output Iλ as shown in FIG._tAre provided with two adders 137 and 139 and an arithmetic circuit 138 which is an arithmetic means for performing an arithmetic operation represented by an operator “$”.
[0194]
The adder 137 reads the posterior probability information y read from the memory circuit (not shown)._tAnd the difference value W read from the memory circuit (not shown)_t-Z_tAnd the obtained data is supplied to the arithmetic circuit 138.
[0195]
The arithmetic circuit 138 reads the difference value U read from a memory circuit (not shown)._t-V_tAnd the data supplied from the adder 137, the same calculation as the calculation circuit 131 is performed. The arithmetic circuit 138 supplies the data obtained by the calculation to the adder 139.
[0196]
The adder 139 reads prior probability information A read from a memory circuit (not shown)._tAnd the data supplied from the arithmetic circuit 138 are added, and the obtained data is added to the logarithmic soft output Iλ._tOutput to the outside.
[0197]
Such a soft output decoding circuit 40 includes prior probability information A read from a memory circuit (not shown)._tPosterior probability information y_tAnd the difference value U_t-V_t, W_t-Z_tAnd at least the difference value U in each state_t-V_t, W_t-Z_tAs a part of the variable, the calculation shown in the above equation (26) is performed, and the logarithmic soft output Iλ at each time_tIs calculated. Then, the soft output decoding circuit 40 calculates the logarithmic soft output Iλ._tAre rearranged in chronological order and then output to the outside.
[0198]
In this way, the soft output decoding circuit 40 improves the normal BCJR algorithm, and the probability log likelihood Iα in each state._t, Iβ_tIt is possible to perform soft output decoding to which an algorithm that performs decoding using a difference value between the values is applied.
[0199]
The soft output decoding circuit 40 is configured to calculate a difference value U_t-V_t, W_t-Z_tIn order to calculate each of the above, “the number of states −1”, here, each of the arithmetic circuits 131 and 135 is provided, and the logarithmic soft output Iλ_tIn the same manner, one arithmetic circuit 138 may be provided. Since each of these arithmetic circuits 131, 135, and 138 has a simple configuration as described above, the soft output decoding circuit 40 reduces the circuit scale and shortens the processing time. Can do.
[0200]
The soft output decoding circuit 40 does not need to include a normalization circuit unlike the soft output decoding circuit that implements the normal BCJR algorithm._t-V_t, W_t-Z_tSince the number of registers necessary for calculating each of the number of states is “number of states−1”, which is one here, the circuit scale can be reduced and the processing speed can be increased.
[0201]
The soft output decoding circuit 40 is not limited to the accumulator 30, and is an element coding that performs coding at any coding rate as long as the state transition is a linear trellis code represented by a trellis that is a state transition diagram. The code by the device can be decoded. For example, when decoding a code having four states, the soft output decoding circuit 40 may select and use “number of states−1”, that is, three difference values. In particular, the soft output decoding circuit 40 works effectively for codes having a small number of states, and has a remarkable effect when the accumulator 30 decodes codes.
[0202]
In this way, the soft output decoding circuit 40 performs the probability log likelihood Iα in each state._t, Iβ_tBy performing decoding using the difference value between these values, it is possible to reduce the circuit scale and speed up the processing without degrading the performance, with simple and few arithmetic processing.
[0203]
The present invention can apply various soft output decoding including such an algorithm as a soft output decoding circuit corresponding to an accumulator in an encoding apparatus.
[0204]
Furthermore, in the above-described embodiment, the encoding device and the decoding device have been described as being applied to a transmission device and a reception device in a data transmission / reception system. It can also be applied to a recording and / or reproducing apparatus that performs recording and / or reproduction on a recording medium such as a magnetic, optical or magneto-optical disk. In this case, the data encoded by the encoding device is recorded on a recording medium equivalent to the memoryless communication path, and is decoded and reproduced by the decoding device.
[0205]
As described above, it goes without saying that the present invention can be modified as appropriate without departing from the spirit of the present invention.
[0206]
【The invention's effect】
As described above in detail, the encoding apparatus according to the present invention is an encoding apparatus that performs column concatenated encoding on input data, and the first code is encoded on the input data. A first encoding unit that performs encoding, a replacement unit that replaces and rearranges the order of each bit constituting the data encoded by the first encoding unit, and the data supplied from the replacement unit And a second encoding means for encoding the second code. At least one of the first encoding means and the second encoding means is configured to input data to the input data. On the other hand, parity check coding for adding 1-bit parity for each predetermined unit is performed.
[0207]
Therefore, the coding apparatus according to the present invention performs a parity check coding by at least one of the first coding means or the second coding means, thereby achieving a desired high coding rate. Can perform high-performance encoding.
[0208]
An encoding method according to the present invention is an encoding method for performing serially concatenated encoding on input data, and includes a first code for encoding a first code on input data. An encoding step, a replacement step of replacing the order of each bit constituting the data encoded in the first encoding step, and rearranging the data rearranged in the replacement step. A second encoding step for encoding the code of 2, and at least one of the first encoding step and the second encoding step is predetermined for the input data Parity check coding is performed to add 1-bit parity for each unit.
[0209]
Therefore, the encoding method according to the present invention performs desired high encoding by performing parity check encoding in at least one of the first encoding step and the second encoding step. It is possible to perform high performance encoding at a rate.
[0210]
Furthermore, the decoding device according to the present invention comprises first encoding means for encoding the first code for the input data, and data encoded by the first encoding means. First replacement means for replacing the order of each bit and rearranging; and second encoding means for encoding a second code for the data supplied from the first replacement means, At least one of the first encoding unit and the second encoding unit is a code that performs parity check encoding that adds 1-bit parity to input data for each predetermined unit. A decoding device that decodes a code that is serially concatenated encoded by an encoding device, is provided corresponding to the second encoding means, and includes a received value that is an input soft input and an input soft input Using prior probability information for a certain information bit A first soft output decoding means for performing soft output decoding, and a bit arrangement of data connected to the first soft output decoding means in a column and rearranged by the first replacement means; A reverse permutation means for rearranging the input soft-input data so as to return to the bit arrangement of the data encoded by the first encoding means, and a column connected to the reverse permutation means. Second soft output decoding means for performing soft output decoding using prior probability information for code bits that are soft inputs output from the inverse permutation means and prior probability information for information bits that are input soft inputs; Second replacement means for replacing the order of each bit constituting the soft input data output from the second soft output decoding means and rearranging based on the same replacement position information as the first replacement means; The first soft output recovery It means, as a priori probability information for the information bits, and inputs the data of the soft-input output from the second replacement means.
[0211]
Therefore, the decoding apparatus according to the present invention provides a high-accuracy code that has been subjected to parity check coding by at least one of the first coding means and the second coding means included in the coding device. Can be decrypted.
[0212]
Furthermore, the decoding method according to the present invention includes a first encoding step for encoding the first code for the input data, and the data encoded in the first encoding step. A first replacement step of rearranging the rearranged bits in order, and a second encoding step of encoding a second code for the data rearranged in the first replacement step And at least one of the first encoding step and the second encoding step, a parity check code that adds 1-bit parity for each predetermined unit to the input data A decoding method for decoding a serially concatenated code by an encoding method for performing encoding, provided in correspondence with the second encoding step, and an input received value that is a soft input Prior probability information for information bits that are soft inputs A first soft output decoding step for performing soft output decoding using the bit sequence of the data rearranged in the first substitution step, and the bits of the data encoded in the first encoding step An inverse permutation step for rearranging input soft input data so as to return to the array and a code bit that is a soft input rearranged in the reverse permutation step, corresponding to the first encoding step. A second soft output decoding step for performing soft output decoding using prior probability information and prior probability information for information bits that are input soft inputs, and based on the same replacement position information as in the first replacement step A second replacement step of rearranging and rearranging the order of each bit constituting the soft input data generated in the second soft output decoding step, and in the first soft output decoding step, information bits As prior probability information for the second To enter the data of the soft-input sorted by the conversion process.
[0213]
Therefore, the decoding method according to the present invention increases the code subjected to parity check encoding in at least one of the first encoding step and the second encoding step included in the encoding method. It enables decoding with high accuracy.
[Brief description of the drawings]
FIG. 1 is a block diagram illustrating a configuration of a communication model to which a data transmission / reception system shown as an embodiment of the present invention is applied.
FIG. 2 is a block diagram illustrating a configuration of an encoding device in the data transmission / reception system shown as the first embodiment of the present invention.
FIG. 3 is a block diagram illustrating a configuration of an interleaver included in the encoding device.
FIG. 4 is a block diagram illustrating a configuration of an accumulator included in the encoding device.
FIG. 5 is a diagram for explaining a trellis in the accumulator shown in FIG. 4;
FIG. 6 is a block diagram illustrating a configuration of a decoding device in the data transmission / reception system.
FIG. 7 is a block diagram illustrating a configuration of a soft output decoding circuit that performs decoding of an inner code included in a decoding device.
FIG. 8 is a block diagram illustrating a configuration of a soft output decoding circuit that performs decoding of an outer code included in a decoding device.
FIG. 9 is a diagram illustrating a function f.
FIG. 10 is a block diagram illustrating a configuration of an encoding device in a data transmission / reception system shown as a second embodiment of the present invention.
FIG. 11 is a diagram for explaining input data and encoded data for explaining an operation in a setter included in the encoding device, in which (A) is output from a parity check encoder included in the encoding device; (B) is a figure which shows the input data input into a parity check encoder.
FIG. 12 is a block diagram illustrating a configuration of a decoding device in the data transmission / reception system.
FIG. 13 is a block diagram illustrating a configuration of a rate conversion circuit included in the decoding device.
FIG. 14 is a block diagram illustrating a configuration of a soft output decoding circuit that performs decoding of an outer code included in a decoding device, and adds a parity in units of 3 bits and decodes a parity check encoded code It is a block diagram explaining the structure of a decoding circuit.
FIG. 15 is a block diagram illustrating a configuration of a soft output decoding circuit that performs decoding of an outer code included in a decoding device, and adds a parity in units of 5 bits to decode a parity check encoded code; It is a block diagram explaining the structure of a decoding circuit.
16 is a block diagram illustrating a configuration of an accumulator included in the encoding device, and is a block diagram illustrating a configuration of an accumulator different from the accumulator illustrated in FIG. 4. FIG.
FIG. 17 is a block diagram illustrating a configuration of a soft output decoding circuit included in a decoding device, and a probability log likelihood Iα_tIt is a block diagram which shows the part which calculates.
FIG. 18 is a block diagram illustrating a configuration of a soft output decoding circuit included in a decoding device, and a probability log likelihood Iβ_tIt is a block diagram which shows the part which calculates.
FIG. 19 is a block diagram illustrating a configuration of a soft output decoding circuit included in a decoding device, and a logarithmic soft output Iλ_tIt is a block diagram which shows the part which calculates.
FIG. 20: Probability log likelihood Iγ_tIt is a figure explaining the matrix which shows.
FIG. 21 is a block diagram illustrating a configuration of a communication model.
FIG. 22 is a block diagram illustrating a configuration of a conventional encoding device.
FIG. 23 is a block diagram illustrating a configuration of a conventional decoding device.
[Explanation of symbols]
1, 1 'encoder, 3, 3' decoder, 10, 10 'parity check encoder, 20, 60 interleaver, 30, 30' accumulator, 40, 90, 90₁, 90₂  Soft output decoding circuit, 50 deinterleaver, 70, 70 ', 80, 80' rate conversion circuit, 100 binarization circuit, 110 setter, 91, 92, 93, 91₁, 92₁, 93₁, 94₁, 91₂, 92₂, 93₂, 94₂, 95₂, 96₂, 131, 135, 138 arithmetic circuit, 133, 136 registers

Claims (26)

An encoding device that performs column concatenated encoding on input data,
First encoding means for encoding the first code for the input data;
Replacing means for replacing the order of each bit constituting the data encoded by the first encoding means;
Second encoding means for encoding a second code for the data supplied from the replacement means,
At least one of the first encoding unit and the second encoding unit performs parity check encoding that adds 1-bit parity to the input data for each predetermined unit. There line,
Of the first encoding means or the second encoding means, the encoding means for performing parity check encoding comprises setting means for setting a distribution of units for adding parity,
Of the first encoding means or the second encoding means, the encoding means for performing parity check encoding adds parity to the input data according to the setting contents of the setting means. An encoding apparatus characterized by changing a unit. The setting means performs the coding according to the total number of bits of data input to the coding means for performing the parity check coding, the coding rate of coding performed by the coding means, and a unit for adding parity. encoding apparatus according to claim 1, wherein setting the distribution unit for adding parity to the input data to the device.   The coding means other than the coding means for performing the parity check coding in the first coding means or the second coding means performs convolutional coding by cumulative addition. The encoding device according to 1. An encoding method for performing column concatenated encoding on input data,
A first encoding step for encoding the first code for the input data;
A replacement step of replacing and rearranging the order of each bit constituting the data encoded in the first encoding step;
A second encoding step for encoding a second code for the data rearranged in the replacement step,
In at least one of the first encoding step and the second encoding step, parity check encoding is performed to add 1-bit parity to the input data for each predetermined unit. There line,
Of the first encoding step or the second encoding step, in the encoding step for performing parity check encoding, the distribution of units to which parity is added is set and input according to the setting content. An encoding method comprising changing a unit for adding parity to data . In the encoding process for performing the parity check encoding, the input data is subjected to the total number of bits of the input data, the coding rate of the encoding performed in the encoding process, and the unit for adding the parity. 5. The encoding method according to claim 4 , wherein a distribution of units for adding parity is set. The convolutional encoding by cumulative addition is performed in an encoding step other than the encoding step in which the parity check encoding is performed in the first encoding step or the second encoding step. 4. The encoding method according to 4 . A first encoding means for encoding the first code for the input data and the order of each bit constituting the data encoded by the first encoding means are replaced and rearranged. A first replacement unit; and a second encoding unit that performs encoding of a second code on the data supplied from the first replacement unit, and the first encoding unit or the first encoding unit. Among the two encoding means, at least one of the encoding means is subjected to cascade concatenated encoding by an encoding device that performs parity check encoding that adds 1-bit parity to input data for each predetermined unit. A decoding device for decoding the received code,
A first output that is provided corresponding to the second encoding means and performs a soft output decoding using a received value that is an input soft input and prior probability information for an information bit that is an input soft input Soft output decoding means;
The bit array of the data connected in a column to the first soft output decoding means and rearranged by the first replacing means is returned to the bit array of the data encoded by the first encoding means. And reverse replacement means for rearranging the input soft input data,
First rate conversion means for converting the clock rate of the data output from the reverse replacement means;
Soft output decoding is performed using prior probability information for a code bit that is an input soft input and prior probability information for an information bit that is an input soft input, provided corresponding to the first encoding means. Second soft output decoding means for performing;
Second rate conversion means for converting the clock rate of the data output from the second soft output decoding means;
Based on the same replacement position information as the first replacement means, second replacement means for replacing the order of each bit constituting the input soft input data and rearranging,
The decoding apparatus according to claim 1, wherein the first soft output decoding means inputs soft input data output from the second replacement means as prior probability information for the information bits. 8. The decoding apparatus according to claim 7, further comprising: binarizing means for binarizing the external information of the soft output generated by the second soft output decoding means and outputting it as hard output decoded data. A first encoding means for encoding the first code for the input data and the order of each bit constituting the data encoded by the first encoding means are replaced and rearranged. A first replacement unit; and a second encoding unit that performs encoding of a second code on the data supplied from the first replacement unit, and the first encoding unit or the first encoding unit. Among the two encoding means, at least one of the encoding means is subjected to cascade concatenated encoding by an encoding device that performs parity check encoding that adds 1-bit parity to input data for each predetermined unit. A decoding device for decoding the received code,
A first output that is provided corresponding to the second encoding means and performs a soft output decoding using a received value that is an input soft input and prior probability information for an information bit that is an input soft input Soft output decoding means;
The bit array of the data connected in a column to the first soft output decoding means and rearranged by the first replacing means is returned to the bit array of the data encoded by the first encoding means. And reverse replacement means for rearranging the input soft input data,
Soft output decoding is performed using prior probability information for a code bit that is an input soft input and prior probability information for an information bit that is an input soft input, provided corresponding to the first encoding means. Second soft output decoding means for performing;
Based on the same replacement position information as the first replacement means, second replacement means for replacing the order of each bit constituting the input soft input data and rearranging,
The first soft output decoding means inputs soft input data output from the second replacement means as prior probability information for the information bits,
The encoding device includes setting means for setting a distribution of units for adding parity in the encoding means for performing parity check encoding among the first encoding means or the second encoding means. ,
Of the first encoding means or the second encoding means, the encoding means for performing parity check encoding adds parity to the input data according to the setting contents of the setting means. A decoding apparatus characterized by changing a unit. Of the first soft output decoding means or the second soft output decoding means, the soft output decoding means provided corresponding to the coding means for performing the parity check coding is a code for performing the parity check coding. Individual soft output decoding means corresponding to the above unit of parity check encoding by the encoding means,
First rate conversion means for converting the clock rate of the data output from the reverse replacement means;
10. The decoding apparatus according to claim 9 , further comprising distribution means for distributing the data whose clock rate has been converted by the first rate conversion means to the individual soft output decoding means. The setting means performs the coding according to the total number of bits of data input to the coding means for performing the parity check coding, the coding rate of coding performed by the coding means, and a unit for adding parity. 10. The decoding apparatus according to claim 9 , wherein a distribution of units for adding a parity to data input to the means is set. Of the first encoding means or the second encoding means, the encoding means other than the encoding means for performing the parity check encoding performs convolutional encoding by cumulative addition. The decoding device according to claim 7 or 9. Of the first soft output decoding means or the second soft output decoding means, the soft output decoding means provided corresponding to the coding means for performing the parity check coding includes a BCJR algorithm, Max-Log-BCJR. 10. The decoding apparatus according to claim 7, wherein maximum a posteriori probability decoding is performed based on an algorithm or a Log-BCJR algorithm. Of the first soft output decoding means or the second soft output decoding means, the soft output decoding means provided corresponding to the encoding means for performing the parity check encoding is a prior probability that is input data. In the case where information is expressed in logarithmic likelihood and handled in the form of logarithmic likelihood, an arithmetic means for performing an arithmetic operation represented by the following general formula (1) and the following general formula (2) using the prior probability information as a variable is provided. Have
10. The decoding apparatus according to claim 7 , wherein soft output external information is generated using a result calculated by the calculating means.

(However, A, B, A ₀ , A ₁ ,..., _An are variables, log is a natural logarithm based on the number e of Nepeya, and $ is an operator.) Of the first soft output decoding means or the second soft output decoding means, the soft output decoding means provided corresponding to the encoding means other than the encoding means for performing the parity check encoding is a BCJR algorithm, 10. The decoding device according to claim 7, wherein maximum a posteriori probability decoding is performed based on a Max-Log-BCJR algorithm or a Log-BCJR algorithm. Of the first soft output decoding means or the second soft output decoding means, the soft output decoding means provided corresponding to the encoding means other than the encoding means for performing the parity check encoding includes at least each state. A calculation means for performing a calculation represented by the following general formula (3) and the following general formula (4) using the difference value of the probability logarithmic likelihood in
10. The decoding apparatus according to claim 7, wherein a logarithmic soft output in which a soft output at each time is expressed by a logarithmic likelihood notation using a natural logarithm is calculated using a result calculated by the calculating means.

(However, A, B, A ₀ , A ₁ ,..., _An are variables, log is a natural logarithm based on the number e of Nepeya, and $ is an operator.) A first encoding process for encoding the first code for the input data, and the order of each bit constituting the data encoded in the first encoding process are replaced and arranged. A first substituting step for switching, and a second encoding step for encoding a second code for the data rearranged in the first substituting step, wherein the first encoding step Alternatively, in at least one of the second encoding steps, tandem concatenation is performed by an encoding method that performs parity check encoding that adds 1-bit parity to input data for each predetermined unit. A decoding method for decoding an encoded code, comprising:
A first output that is provided corresponding to the second encoding step and performs soft output decoding by using a received value that is an input soft input and prior probability information for an information bit that is an input soft input. A soft output decoding step;
The input soft input data is rearranged so that the bit arrangement of the data rearranged in the first replacement step is returned to the bit arrangement of the data encoded in the first encoding step. A reverse substitution step;
A first rate conversion step of converting a clock rate of the data rearranged in the reverse replacement step;
Soft output decoding is performed using a priori probability information for a code bit that is an input soft input and a priori probability information for an information bit that is an input soft input, provided corresponding to the first encoding step. A second soft output decoding step to perform;
A second rate conversion step of converting the clock rate of the data generated in the second soft output decoding step;
Based on the same replacement position information as in the first replacement step, a second replacement step of replacing the order of each bit constituting the input soft input data and rearranging,
In the first soft output decoding step, the soft input data rearranged in the second replacement step is input as prior probability information for the information bits. 18. The decoding method according to claim 17, further comprising: a binarization step of binarizing the soft output external information generated in the second soft output decoding step and outputting it as hard output decoded data. A first encoding step for encoding the first code for the input data, and the order of each bit constituting the data encoded in the first encoding step are replaced and arranged. A first substituting step for switching, and a second encoding step for encoding a second code for the data rearranged in the first substituting step, wherein the first encoding step Alternatively, in at least one of the second encoding steps, tandem concatenation is performed by an encoding method that performs parity check encoding that adds 1-bit parity to input data for each predetermined unit. A decoding method for decoding an encoded code, comprising:
A first output that is provided corresponding to the second encoding step and performs soft output decoding by using a received value that is an input soft input and prior probability information for an information bit that is an input soft input. A soft output decoding step;
The input soft input data is rearranged so that the bit arrangement of the data rearranged in the first replacement step is returned to the bit arrangement of the data encoded in the first encoding step. A reverse substitution step;
Soft output decoding is performed using a priori probability information for a code bit that is an input soft input and a priori probability information for an information bit that is an input soft input, provided corresponding to the first encoding step. A second soft output decoding step to perform;
Based on the same replacement position information as in the first replacement step, a second replacement step of replacing the order of each bit constituting the input soft input data and rearranging,
In the first soft output decoding step, the soft input data rearranged in the second replacement step is input as prior probability information for the information bits,
Of the first encoding step or the second encoding step, in the encoding step for performing parity check encoding, the distribution of units to which parity is added is set and input according to the setting content. A decoding method, wherein a unit for adding parity to data is changed. Of the first soft output decoding step or the second soft output decoding step, the soft output decoding step provided corresponding to the encoding step for performing the parity check encoding is a code for performing the parity check encoding. Each soft output decoding step according to the above unit of parity check encoding by the encoding step,
A first rate conversion step of converting a clock rate of the data rearranged in the reverse replacement step;
20. The decoding method according to claim 19, further comprising a distribution step of distributing the data whose clock rate has been converted in the first rate conversion step to the individual soft output decoding steps. In the encoding process for performing the parity check encoding, the input data is subjected to the total number of bits of the input data, the coding rate of the encoding performed in the encoding process, and the unit for adding the parity. 20. The decoding method according to claim 19 , wherein a distribution of units for adding parity is set. Of the first encoding step or the second encoding step, convolutional encoding by cumulative addition is performed in an encoding step other than the encoding step for performing the parity check encoding. The decoding method according to claim 17 or 19 . Of the first soft output decoding step or the second soft output decoding step, in the soft output decoding step provided corresponding to the coding step for performing the parity check coding, a BCJR algorithm, Max-Log-BCJR 20. The decoding method according to claim 17 or 19 , wherein maximum a posteriori probability decoding is performed based on an algorithm or a Log-BCJR algorithm. Of the first soft output decoding step or the second soft output decoding step, the soft output decoding step provided corresponding to the encoding step for performing the parity check encoding is a prior probability that is input data. When information is expressed in log-likelihood notation and handled in the form of log-likelihood, an operation step of performing an operation represented by the following general formula (5) and the following general formula (6) using the prior probability information as a variable is performed. Have
20. The decoding method according to claim 17 , wherein soft output external information is generated using a result calculated in the calculation step.

(However, A, B, A ₀ , A ₁ ,..., _An are variables, log is a natural logarithm based on the number e of Nepeya, and $ is an operator.) Among the first soft output decoding step or the second soft output decoding step, in the soft output decoding step provided corresponding to the encoding step other than the encoding step for performing the parity check encoding, the BCJR algorithm, The decoding method according to claim 17 or 19 , wherein maximum a posteriori probability decoding is performed based on a Max-Log-BCJR algorithm or a Log-BCJR algorithm. Of the first soft output decoding step or the second soft output decoding step, the soft output decoding step provided corresponding to the encoding step other than the encoding step for performing the parity check encoding includes at least each state. A calculation step of performing the calculation represented by the following general formula (7) and the following general formula (8) using the difference value of the probability logarithmic likelihood in
20. The decoding method according to claim 17 or 19 , wherein a logarithmic soft output in which a soft output at each time is expressed using a logarithmic likelihood is expressed using a result calculated in the calculating step.

(However, A, B, A ₀ , A ₁ ,..., _An are variables, log is a natural logarithm based on the number e of Nepeya, and $ is an operator.)

Images