JP2001290671A - In-circuit emulator, recording medium and middleware issuing system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve the problem where conventional middleware cannot be freely distributed since copy is easy and the analysis of an algorithm by means of disassemble or the like is facilitated, while a distribution form capable of easily providing the middleware or peripheral circuit data on the internet is desired for making a profit by sales of IPs. SOLUTION: A chip ID characteristic of a system LSI is arranged, the middleware is composed of a body part of middleware and a chip ID confirming part using a user non-disclosed instruction, and a shipping ID desired to make the middleware executable is received from a user. While using a shipping ID data base, the correspondent chip ID is extracted, and the middleware capable of validation only by means of an LSI having the limited chip ID is combined and transferred to the user.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention provides middleware that operates only with a permitted LSI and that has difficulty in analyzing an algorithm, thereby achieving both free distribution on a network and charging according to the number of used devices. The present invention relates to an in-circuit emulator, a recording medium, and a middleware issuing system.

[0002]

2. Description of the Related Art Currently, middleware is sold on a contract basis. For example, it is sold under a contract such as "Payment of 4 million yen for use of 40,000 copies, do not use more copies, do not copy to other companies".

[0003]

However, if copied illegally, duplication and analysis of the algorithm are easy. Therefore, a distribution form in which middleware and peripheral circuit data can be easily obtained through the Internet or the like has not been realized.

The present invention has been made in view of such a problem, and has been developed in view of the above problem.
By issuing middleware that operates only on I and difficult to analyze algorithms, the purpose is to achieve both free distribution on the network and charging according to the number of devices used.

[0005]

In order to solve this problem, an in-circuit emulator according to the present invention has an ICE interrupt detecting means, an ICE interrupt generating means, and an instruction executing means, and executes an ICE interrupt invalidating instruction by executing the instruction. When the means executes, the ICE interrupt suppression flag is set, and when the ICE interrupt instruction is executed by the instruction execution means while the ICE interrupt suppression flag is set, the ICE interrupt detection means sets the trace effective flag; Suppress the ICE interrupt of the ICE interrupt generation means.

In order to solve this problem, an in-circuit emulator of the present invention resets the interrupt suppression flag when an ICE interrupt enable instruction is executed by the instruction execution means while the trace enable flag is set. Generates an ICE interrupt.

In order to solve this problem, the recording medium of the present invention includes a step of confirming a chip ID of an ICE chip, a step of confirming a chip ID of a mass-produced chip, and a subroutine call if the result of the confirmation is not satisfied. And returning to the next address.

In order to solve this problem, a recording medium according to the present invention comprises a step of first disabling an ICE interrupt,
Finally, a program comprising the step of enabling the ICE interrupt is stored.

In order to solve this problem, in the recording medium of the present invention, the step of disabling the ICE interrupt is described by an instruction code that is not disclosed to the user.

To solve this problem, a middleware issuing system according to the present invention is connected to a user computer by a communication line, and obtains a shipping ID and a number of the shipping ID and the number from the user computer;
A shipping ID database indicating the correspondence with the ID,
A chip ID checking unit generating means for extracting a chip ID using the shipping ID and the number from the ID database to generate a chip ID checking unit, a middleware database storing a plurality of middleware main units, and a user ID from the middleware database. Middleware combining means for extracting a designated middleware main body and combining it with the chip ID confirmation unit to generate middleware, and middleware transferring means for transferring the middleware to the user computer.

In order to solve this problem, a middleware issuing system according to the present invention includes circuit data transfer means for transferring circuit data to the user computer, and includes a circuit control middleware for controlling a circuit formed using the circuit data. Transfer to the user computer.

In order to solve this problem, the middleware of the middleware issuing system of the present invention starts with an instruction for disabling an ICE interrupt instruction and ends with an instruction for enabling an ICE interrupt.

In order to solve this problem, in the middleware of the middleware issuing system of the present invention, the instruction for invalidating the ICE interrupt instruction is described by an instruction code not disclosed to the user.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below with reference to FIGS.

FIG. 1 is a block diagram showing a configuration of a middleware issuing system according to an embodiment of the present invention.

In FIG. 1, 1 is a host computer for issuing middleware and peripheral circuit data, 2 is a database of a correspondence relationship between a shipment ID of a system LSI sold to a user and a chip ID, and 3 is a plurality of types of middleware main units. The stored database, 8 is a circuit database that stores circuit information, 4 is a user computer connected to the host computer 1 via the communication line 7, and 9 is a middleware issuing database that stores middleware information transferred to the user computer. Reference numeral 5 denotes an ICE chip connected to a user computer and used for program development. Reference numeral 6 denotes a ROM writer for writing a completed user program and peripheral circuits to a system LSI.

In the above system, the user connects to the host computer 1 via the communication line 7 such as the Internet using the user computer 4, and logs in using the user ID and password. Next, the user specifies the desired middleware for the host computer 1. This middleware includes those requiring peripheral circuits such as timers. When the middleware is evaluated by the ICE chip 5, the charge is free, and the host computer 1 transfers the middleware that operates only on the ICE chip 5 to the user computer 4. Further, when middleware is mounted on a system LSI for mass production, a user must pay for the number of used middleware. The user specifies the shipping ID printed on each system LSI and the number of middleware used in the host computer 1, and the host computer 1 stores the middleware and circuit data that can be operated only by the system LSI and the ICE chip 5 requested by the user. Transfer to computer 4.

FIG. 4 is a diagram showing the configuration of a system LSI 41 in which middleware and circuit data are written by the ROM writer 6. 41 is a system LSI and 43 is a ROM writer 6 that can write peripheral circuit data.
The FPGA 45 is a nonvolatile memory for writing a user program including middleware by the ROM writer 6, and the CPU 42 executes a program stored in the nonvolatile memory 45 and controls a peripheral circuit created in the FPGA 43. . 44 is a chip ID unique to the system LSI 41
Therefore, all the system LSIs have different chip IDs including the ICE chip.

FIG. 7 is a diagram showing a configuration of the ICE chip 5. 73 is an FPG to which peripheral circuit data can be written
A and 75 are volatile memories in which a user program including middleware is stored, and 72 is a CPU that executes a program stored in the volatile memory 75 and controls a peripheral circuit created in the FPGA 73. Reference numeral 74 denotes a chip ID unique to the ICE chip 5, and all ICE chips have different chip IDs. Further, reference numeral 421 denotes an address storage means used when executing the step of the instruction, and 422 denotes an instruction storage means used when executing the step of the instruction.
423 is a trace valid flag used when skipping middleware tracing, 424 is an ICE interrupt detecting means for detecting an ICE interrupt instruction, 425 is an ICE interrupt generating means for generating an ICE interrupt, and 426 is used for suppressing middleware tracing. The ICE interrupt suppression flag 427 is an instruction executing means for executing an instruction.

FIG. 2 is a diagram showing each function realized by the host computer 1.

As described above, the user first connects to the host computer 1 via the communication line 7 such as the Internet using the user computer 4, and logs in using the user ID and password. Here, the host computer 1 recognizes the user ID by the user ID obtaining means 100.

Next, the user specifies the desired middleware for the host computer 1. This includes peripheral circuits such as timers. Although the address of the control register of the peripheral circuit is not disclosed and cannot be directly accessed by the user, it is controlled using dedicated middleware. As will be described later, the middleware of the present invention is a fixed LS
An LSI that can be used only with I, and therefore has a fixed circuit
Only available in. And whether to use middleware for evaluation with ICE chip 5 or mass production system
Specify whether to mount on LSI, and use system L for mass production
Specify the shipping ID printed for each SI. Where shipping ID
The acquisition unit 101 recognizes the range of the shipping ID. For example, IC
When used for evaluation with the E chip 5, the value "ICE" is recognized as the shipping ID meaning the ICE chip,
In the case of mass production, the value “99-12-000020” (meaning the 20th in December 1999) and the number of used units are recognized as the shipping ID printed on each system LSI. 100 used
Then, shipping IDs 99-12-000020 to 99-12-000119 use middleware. Further, the shipping ID acquisition means 101
Chip ID corresponding to shipping ID using shipping ID database
And confirm that there is no inconsistency in the recognized user ID. If there is a contradiction, the distribution of the middleware is stopped.

Then, using the extracted chip ID, the chip ID confirming unit generating means 102 is placed at the head of the middleware so that the middleware can be used only in the system LSI and ICE having the specified chip ID. Generate a chip ID confirmation unit to be used.

Finally, the middleware synthesizing means 103 extracts the middleware main body from the middleware database 3 in accordance with the user's specification, and synthesizes the chip ID confirmation part and the extracted middleware main body to generate middleware. 104 transfers the completed middleware to the user computer 4. When the middleware requires a peripheral circuit, the circuit data transfer unit 105 extracts desired circuit data from the circuit database 8 and transfers the circuit data to the user computer 4.

As described above, the ID and version of the middleware transferred to the user computer 4, the type and version of the circuit, and the range of the shipping ID permitted to execute the middleware are recorded in the middleware issuing database 9.
Then, it is assumed that the middleware version is updated.
When the user computer 4 accesses the host computer 1, the user computer 4 refers to the middleware ID recorded in the middleware issuing database 9, extracts the latest version information of the middleware having the ID from the middleware database 3, and stores the latest version information in the middleware issuing database 9. The version is compared with the recorded middleware version, and if different, the latest version information is transferred to the user computer 4.

FIG. 3 is a diagram showing the structure of the middleware 30 that the host computer 1 transfers to the user computer 4. The middleware 30 is described by a binary code. 31 is an ICE trace invalidation instruction for disabling the ICE interrupt, and 32 is NO having the same size as the ICE interrupt instruction.
P and 33 are chip ID confirming units for checking the IDs of the ICE and the system LSI for mass production and immediately returning to the next address of the instruction that issued the middleware subroutine call if the conditions are not satisfied. 34 is a middleware main body, 35 is an ICE trace enable command for enabling ICE interrupts, and 36 is a return command for returning to the subroutine call destination.

Here, the ICE trace invalidation instruction 31, NOP
32, chip ID confirmation unit 33, ICE trace enable instruction 3
5 is written in an instruction code that is not disclosed to the user. The disassembly program sold to the user is assumed to be able to handle only the instruction code that is open to the user. Therefore, since the middleware shown in FIG. 3 cannot be disassembled, the algorithm cannot be easily analyzed. After the subroutine call of the middleware is performed, the ICE trace invalidation instruction 31 is executed. If the ICE chip 5 is executing one instruction at a time in the trace mode by the ICE chip 5, the ICE chip 5 replaces the NOP 32 with an ICE interrupt instruction and executes the ICE trace invalidation instruction 31, so an interrupt is generated by the ICE interrupt instruction replacing the NOP 32. do not do. Instead, the fact that the ICE interrupt has been executed is stored by setting the trace valid flag 423. If the trace enable flag 423 is set when the ICE trace enable instruction 35 is executed,
ICE interrupt occurs. That is, the middleware cannot be traced by the step execution of the ICE chip 5. The inability to trace, along with the inability to disassemble, makes the analysis of middleware algorithms more difficult.

FIG. 5 is a diagram showing the step execution by the ICE chip 5. Here, a case where the instruction B52 follows the instruction A51 and the instruction A51 is step-executed is shown.

First, in (a), the ICE chip 5 stores the instruction B52 next to the instruction A51 to be step-executed in the instruction storage means 422 and the address of the instruction B52 in the address storage means 421. Next, immediately after instruction A51 in (b)
The ICE interrupt instruction is overwritten on the instruction B52, and the instruction A51 is executed. When the ICE interrupt instruction is executed subsequent to the execution of the instruction A51, an ICE interrupt is generated, and the process proceeds to the ICE processing routine. Then, the instruction B52 stored in the instruction storage means 422 is stored at the location indicated by the address storage means 421 in (c), and the instruction B52 is restored to the state of (a).

FIG. 5 shows the case of the general step execution. FIG. 6 shows the case of executing the middleware 30.

First, in (a), the first instruction of the middleware, I
The NOP 32, which is the instruction following the CE trace invalidation instruction 31, is stored in the instruction storage means 422, and the address B where the NOP is located is stored in the address storage means 421. Here, the value of the trace valid flag 423 is 0. Next, in (b), immediately after the ICE trace invalidating instruction 31, an ICE interrupt instruction is
ICE trace invalidation instruction 31 is executed.
Then, the ICE interrupt suppression flag 426 is set by the instruction execution means 427. The ICE interrupt instruction is executed subsequent to the execution of the ICE trace invalidation instruction 31, but the ICE interrupt detection means 424 suppresses the ICE interrupt generation means 425 from generating an ICE interrupt because the ICE interrupt suppression flag 426 is set. At the same time, the ICE interrupt detection means 424 sets the trace valid flag 423. Since no ICE interrupt occurs, instructions are executed one after another until the ICE trace enable instruction 31 is executed. And ICE in (c)
When the trace enable instruction 31 is executed, the ICE interrupt suppression flag 426 is released, and the trace enable flag 42
Since 3 is set, the ICE interrupt generating means 425 generates an ICE interrupt. Due to the occurrence of the ICE interrupt, the ICE chip 5 stores the N stored in the instruction storage unit 422 at the position of the address B stored in the address storage unit 421.
OP32 is stored and stopped.

That is, if the step execution is performed before the execution of the middleware 30, after the subroutine call to the middleware 30, the ICE chip 5 stops in a state where the execution of the middleware is completed, and the middleware is not traced.

In the above embodiment, the system LSI
Has been described above, the middleware body 34 may be middleware created by the user. When the development of the middleware is completed, the user can transfer the middleware code to a manufacturer that sells the system LSI, and have the structure shown in FIG. The system LSI shown in FIG. 4 can easily read information from a nonvolatile memory. By having the middleware have the structure shown in FIG. 3, it is possible to prevent the use of middleware and algorithm analysis by a third party.

In the above embodiment, the case where the ICE system is constituted by the user computer 4 and the ICE chip 5 has been described. However, the technique shown in FIG. 7 can be implemented by another debugger (for example, JTAG).

In the above embodiment, the FeRA shown in FIG.
M is a recording medium for storing middleware, but the recording medium may be another medium such as a CD-ROM or a floppy (registered trademark) disk.

[0036]

As described above, the in-circuit emulator, the recording medium, and the middleware issuing system according to the present invention operate only with the permitted LSI and issue the middleware for which the algorithm analysis is difficult, so that the freedom in the network can be improved. Compatible distribution and billing according to the number used.

Further, since the middleware developed by the user can be operated only by the user's LSI and the algorithm analysis can be made difficult, the user's IP can also be protected.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a middleware issuing system according to an embodiment of the present invention.

FIG. 2 is a diagram illustrating respective functions realized by a host computer according to an embodiment of the present invention.

FIG. 3 is a diagram showing a structure of middleware according to the embodiment of the present invention.

FIG. 4 is a diagram showing a configuration of a system LSI according to an embodiment of the present invention;

FIG. 5 is a diagram showing step execution by an ICE chip according to an embodiment of the present invention.

FIG. 6 is a diagram showing step execution by an ICE chip of middleware according to an embodiment of the present invention.

FIG. 7 is a diagram showing a configuration of an ICE chip according to an embodiment of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Host computer 2 Shipping ID database 3 Middleware database 4 User computer 5 ICE chip 6 ROM writer 7 Communication line 8 Circuit database 9 Middleware issuing database 30 Middleware 31 ICE trace invalidation instruction 32 NOP 33 Chip ID confirmation unit 34 Middleware main unit 35 ICE Trace enable command 36 Return command 41 System LSI 42, 72 CPU 43, 73 FPGA 44, 74 Chip ID 45 Non-volatile memory 51 Command A 52 Command B 75 Volatile memory 100 User ID acquisition means 101 Shipping ID acquisition means 102 Chip ID Confirmation unit generation means 103 Middleware synthesis means 104 Middleware transfer means 105 Circuit data transfer means 421 Address storage means 422 Instruction storage means 423 Trace valid flag 424 ICE interrupt detection means Stage 425 ICE interrupt generation means 426 ICE interrupt suppression flag 427 Instruction execution means

Claims (9)

[Claims] An ICE interrupt detecting means, an ICE interrupt generating means, and an instruction executing means, wherein when the ICE interrupt invalidating instruction is executed by the instruction executing means, an ICE interrupt suppressing flag is set, and the ICE interrupt suppressing flag is set. An in-circuit emulator, wherein when the ICE interrupt instruction is executed by the instruction execution means while being set, the ICE interrupt detection means sets a trace effective flag and suppresses an ICE interrupt of the ICE interrupt generation means. . 2. When the ICE interrupt enable instruction is executed by the instruction execution means while the trace enable flag is set, the interrupt suppression flag is reset to reset the IC.
The in-circuit emulator according to claim 1, wherein an E-interrupt is generated. 3. A step of confirming a chip ID of an ICE chip, a step of confirming a chip ID of a mass-produced chip, and a step of returning to a next address of a subroutine call if the condition is not satisfied as a result of the confirmation. A recording medium that stores a program. 4. The recording medium according to claim 3, further comprising a step of first disabling an ICE interrupt and finally a step of enabling an ICE interrupt. 5. The recording medium according to claim 3, wherein the step of disabling the ICE interrupt is described by an instruction code not disclosed to a user. 6. A shipment ID acquisition means connected to a user computer via a communication line and acquiring a shipment ID and a number from the user computer, a shipment ID database indicating a correspondence between the shipment ID and a chip ID, A chip ID checking unit generating means for extracting a chip ID using the shipping ID and the number from the shipping ID database to generate a chip ID checking unit, a middleware database storing a plurality of middleware main units, and a user from the middleware database. Extract the middleware body specified by
A middleware issuing system, comprising: middleware combining means for creating middleware by combining with an ID confirmation unit; and middleware transfer means for transferring the middleware to the user computer. 7. The middleware issuing system further comprises:
7. The middleware according to claim 6, further comprising circuit data transfer means for transferring circuit data to the user computer, and transferring circuit control middleware for controlling a circuit created using the circuit data to the user computer. Publishing system. 8. The middleware issuing system according to claim 6, wherein the middleware further starts with an instruction for disabling an ICE interrupt instruction and ends with an instruction for enabling an ICE interrupt. 9. The middleware issuing system according to claim 6, wherein the instruction for invalidating the ICE interrupt instruction is described by an instruction code not disclosed to a user.