JP2001285384A - Demodulator - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a demodulator which can precisely detect frequency differences in semi-synchronous detection and improve the adjustment capability toward noise. SOLUTION: The phase sampling data of π/4 shift QPSK modulated wave which is sampled by a semi-synchronous detector 1 is delayed by the time period required for n-times sampling by a delay unit 3 to obtain the phase difference between the sampling data before and after the delay. Then the phase difference obtained by the delay unit 3 is compared with the basic phase difference stored in the base phase difference storage 51 by a phase comparison unit 5. Based on the time period when preambles are detected by a preamble detector 4, and the comparison result given by the phase comparison unit 5, the frequency difference of a carrier is calculated by a operating unit 6, based on which the frequency of the phase sampling data sampled by the semi-synchronous detector 1 is corrected by a frequency corrector 6.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a π / 4 shift Q
The present invention relates to a quasi-synchronous detection type demodulator that captures a carrier frequency of a quadrature phase shift keying (PSK) signal and corrects a frequency difference.

[0002]

2. Description of the Related Art Digital mobile telephone systems and PHSs (Personal Handy Phone Systems) have become quite popular, and are equipped with a digital demodulation circuit used in such digital mobile communication systems. There is a demodulator.

[0003] The PHS is under a relatively slow fading environment, and its transmission power is considerably smaller than that of a portable telephone system. The modulation scheme of this PHS is π / 4 shift Q
The PSK modulation method is adopted, and the signal is an eight-phase digital modulation wave as shown in FIG. In the orthogonal two-channel IQ signal plane of the eight-phase digital modulation wave, as shown in FIG. 9B, after the phase of the symbol makes a π / 4 transition with respect to the immediately preceding symbol, the next symbol becomes −3.
It has a specific preamble pattern in which π / 4 transition is alternately repeated. This specific preamble pattern is repeated continuously for a period of 31 symbols, except for some channels such as an LCCH (physical control channel) scan. This means that the continuous preamble pattern can be used as a method of detecting the phase information of the received signal based on the reference timing of the demodulator itself and specifying the timing of the preamble pattern.

As a method of detecting the timing from the preamble pattern, a method of detecting a timing using a PH
In the S receiver, phase sampling data is extracted by quasi-synchronous detection of the received signal, the phase sampling data is delayed by one symbol, and the phase difference between the delayed phase sampling data and the phase sampling data before delay is calculated. The received signal is processed as a BPSK (Binary Phase Shift Keying) signal by performing the arithmetic processing to obtain the signal, binarized by the polarity of the BPSK signal, and the frequency of the square wave of the binarized signal is calculated. It is known that a frequency difference is obtained by calculation (Japanese Patent Application Laid-Open No. 9-266499).

As a method of extracting phase information from a preamble pattern, focusing only on symbol points,
In FIG. 9 (b), the symbol point is the point of the circle where the preamble waveform intersects the circle, and the phase difference between the two symbols may be π / 2 from the drawing of FIG. 9 (b). Found. It is known that when a received signal is detected at a symbol point, if delay detection between two symbols is performed from the detected signal, a frequency error is calculated from information on a phase angle obtained as a result (Japanese Patent No. 2643792). Publication).

[0006] When a received signal becomes an information channel,
Generally, as shown in FIGS. 11A and 11B, the preamble pattern becomes short, and it becomes difficult to extract phase information from the preamble pattern. Therefore, in the information channel,
After delay detection of the quasi-synchronous detected phase sampling data, a frequency difference at each sampling point is obtained by an operation using demodulated data having no regularity, and a moving average is calculated for several tens of symbol periods. The difference has been derived.

In general, a demodulator is open to a synchronous detection system using a closed loop such as the Costas system, a delay detection system using a quasi-synchronous detection that can reduce the circuit scale, and similar quasi-synchronous detection. There is a synchronous detection method to which a loop is added.

[0008] The preamble pattern in FIG.
It is created from the S standard and shows the trajectory of symbol change in the preamble of the control channel and the synchronization burst. In this preamble, the bit string is defined by the standard, and from the standard specification and FIG. 9B, the phase between two symbols is π / at the symbol points (points of ○ and ●).
2 can be found. In this case, in order to sample the received signal at the symbol point, it is necessary to adopt a synchronous detection method using a closed loop or the like. However, considering a case where phase detection is performed at a point other than a symbol point in quasi-synchronous detection other than synchronous detection, for example, A ₁ at an arbitrary point and a point two symbols ahead in the waveform of the preamble in FIG.
Although a point ~B ₁ point and A ₂ points ~B ₂ points, they are difficult to derive that there is some regularity in the phase difference between the point A ~B point from the drawing. The calculated trajectory of the preamble shows a trajectory as shown in FIG. 10 (a waveform after passing through a root Nyquist filter). This FIG.
In FIG. 9 (b), sample points are marked so that the time trajectory is easy to understand, but if there is no mark as shown in FIG. It is difficult to derive the phase difference between one sample point and another sample point and find the trajectory of the phase difference, and an approach to calculate the phase difference by a quantitative method including computer simulation and derive regularity is necessary. is there.

In the case of such synchronous detection, the received signal is sampled at symbol points, so that a phase difference between two symbols can be derived. However, in the conventional synchronous detection, a closed-loop PLL (Phase-Locked Lo
op: a phase-locked loop), which causes a problem that the PLL is unlocked due to fading or the like. For this reason, a circuit for controlling unlocking of the PLL or the like is required. However, it is difficult to design an unlock prevention circuit that can be controlled under any receiving environment, and there is a limit. For this reason, a method of performing delay detection after performing quasi-synchronous detection, or performing open-loop synchronous detection after performing quasi-synchronous detection is generally adopted, and both methods employ quasi-synchronous detection first. Has become.

In the quasi-synchronous detection, focusing on the number of samples for which the frequency difference is obtained, the frequency difference is obtained from 31 symbols of a specific preamble pattern in the conventional method. Is 29 to 31 samples. For this reason, in an environment where the reception sensitivity is not good, the phase sampling data subjected to quasi-synchronous detection has a large amount of noise, and the arithmetic processing is performed from the number of samples having a small frequency difference of 29 to 31. Significantly affects averaging. It is also conceivable to remove sample data containing a lot of noise in the operation process. In such a case, however, the accuracy of the operation result is reduced due to a further decrease in the number of samples, so that the error of the frequency difference increases. In an environment where reception sensitivity is not good such that the error rate is deteriorated, accurately specifying the timing of the preamble pattern to improve the error rate leads to an improvement in the reception performance such as, for example, preventing interruption of voice. . In the conventional method, detection is considered to be effective in an environment where reception sensitivity is somewhat good, so in an environment where reception sensitivity is not good, the frequency difference detection accuracy for specifying the timing of the preamble pattern may decrease. Can be considered. For example, in the conventional technology, the frequency difference information is detected by averaging from the phase difference information in the section of 24 symbols out of 31 symbols, and the phase noise is strengthened. In this case, the reliability of the frequency difference information may be reduced.

In the information channel of the received signal, the preamble period becomes very short.
There are four symbols including the SS (start bit). FIG.
1 (a) and 1 (b) show the configuration of each slot of a control channel and the like and an information channel. The reason why the preamble is shortened in the information channel shown in FIG. 11 (b) is that synchronization has already been established with the base station, a link has been established and transmission and reception are possible, and the preamble in the slot has been shortened. This is because it is intended to transmit a lot of information by assigning it to data or the like. In FIG. 11B, the preamble of the information channel has only four symbols. The phase of the modulated wave can be created by convolving a single pulse at about 8 to 10 symbol points before and after. However, in the preamble of the information channel for 4 symbol periods, the π / phase is accurately influenced by the convolution from the preceding and following symbol points. After four transitions, the next symbol does not draw a phase trajectory that makes a -3π / 4 transition.

Further, as shown in FIG. 12, the phase of the preamble period (PR in FIG. 12) of the information channel is wavy and does not converge to a fixed phase. Is difficult to identify. Therefore, conventionally, in the information channel, a frequency difference at each sampling point is obtained by calculation using demodulated data having no regularity after delay detection of phase sampling data subjected to quasi-synchronous detection, and this is calculated for several tens of symbol periods. , And a frequency difference is derived from the moving average. However, there is a problem that accuracy and precision are reduced and an error is large.

It is an object of the present invention to provide a demodulator capable of accurately detecting a frequency difference from a preamble in quasi-synchronous detection and improving a margin for noise.

It is another object of the present invention to provide a demodulator capable of accurately detecting a frequency difference from a unique word of an information channel having a short preamble pattern in quasi-synchronous detection and improving a margin for noise. is there.

[0015]

In order to achieve the above object, a demodulation apparatus according to the present invention comprises a π / 4 shift QP
A quasi-synchronous detector that receives an SK modulated wave as an input signal and samples the phase of the input signal at a sampling interval of n (n is an integer of 2 or more) per two symbols using a sampling clock generated from a reference oscillator. A delay difference unit that delays the phase sampling data sampled by the quasi-synchronous detection unit by a time required for n times of sampling, and calculates a phase difference between the delayed phase sampling data and the phase sampling data before the delay. , The phase of the symbol of the input signal makes a π / 4 transition with respect to the immediately preceding symbol, and the phase of the next symbol becomes -3π / 4.
A preamble detection unit that detects a preamble of a specific pattern in which transitions are alternately repeated; and a preamble detection unit that detects a preamble between two symbols in the predetermined preamble based on a condition of a π / 4 shift QPSK modulated wave transmitted from a transmitter. A reference phase difference storage unit that stores the reference phase difference, a phase difference calculated by the delay difference unit, and a phase comparison unit that compares the reference phase difference stored in the reference phase difference storage unit, A period in which the preamble is detected by the preamble detector, a frequency difference calculator that calculates a frequency difference of the carrier based on the comparison result of the phase comparator, and a frequency difference of the carrier calculated by the frequency difference calculator. A frequency correction unit that corrects the frequency of the phase sampling data sampled by the quasi-synchronous detection unit. Using the phase sampling data corrected by the frequency correction unit reproduces the demodulation clock, and characterized in that a demodulator for obtaining a demodulated data from said corrected phase sampled data based on the demodulation clock.

According to the demodulation device having the above configuration, the quasi-synchronous detector receives the π / 4 shift QPSK modulated wave as an input signal, and uses the sampling clock generated from the reference oscillator to determine the phase of the input signal. N per two symbols
(n is an integer of 2 or more) sampling. In the control channel and synchronization burst of this input signal, the symbol is π on the IQ signal plane of the signal components of two orthogonal channels.
It has a preamble of a specific pattern that is alternately repeated to make a / 4 transition and then a -3π / 4 transition. The delay difference unit delays the quasi-synchronous detected phase sampling data by a time required for n times of sampling (two symbols), and obtains a phase difference between the delayed phase sampling data and the phase sampling data before delay. . In this case, when the input signal is a preamble, if the sampling point is on a symbol point, the received symbol makes a π / 4 transition, and then the next symbol is alternately repeated so as to make a -3π / 4 transition. Because it is a specific pattern,
The delay difference value (phase difference between two symbols) is π / 2. Here, when trying to obtain the phase difference other than the symbol points, FIG.
It is difficult to derive from the trajectory of the preamble pattern shown in (b). Actually, the waveform of the specific preamble pattern of the π / 4 shift QPSK modulation wave is calculated and created, and the delay difference of n sample intervals at an arbitrary sampling point is obtained. It is necessary to determine a value. FIG. 10 shows a π / 4 shift QP
It is created by calculating the waveform of a specific preamble pattern using the SK modulation wave. Since the start of this specific preamble pattern starts from the ramp (rising) of the slot, it starts from (0, 0) in IQ coordinates, and
This is a “crowbar waveform” that is alternately repeated so as to make a −π / 4 transition after a / 4 transition. So 2
The phase difference is obtained at n sampling intervals per symbol and is shown in FIG. 13 (the horizontal axis is the sample, and the vertical axis is the phase difference). The waveform at each sample point is generated from convolution of an isolated single-shot waveform of approximately 8 to 10 symbols before and after. This means that the first and last few symbols of the 31 symbols in the preamble section are convolved with data outside the preamble section, so that the phase difference of the delay difference section does not converge to a constant value at n sampling intervals. If the preamble is the fourth or fifth symbol or later, the horizontal axis in FIG.
As shown after one sample, it converges to a constant phase angle (90 °). Paying attention to the fact that the fixed phase angle fluctuates due to the frequency error of the carrier, the frequency error of the carrier is estimated from the phase angle of the preamble.

First, a reference phase difference between two symbols obtained in advance by calculation or the like based on the conditions of a π / 4 shift QPSK modulated wave transmitted from the transmitter is stored in a reference phase difference storage unit, and a preamble is stored. Is detected, the phase comparison unit compares the phase difference of n sampling intervals with the reference phase difference, and based on the comparison result of the phase comparison unit, calculates the frequency difference of the carrier by the frequency difference calculation unit. derive. The frequency correction unit corrects the frequency of the phase sampling data detected by the quasi-synchronous detection unit based on the carrier frequency difference calculated by the frequency difference calculation unit. As a result, the frequency of the phase sampling data is corrected, a demodulation clock is generated by the demodulation unit using the corrected phase sampling data, and the demodulation data is obtained based on the demodulation clock.

Therefore, with a simple configuration, the frequency difference can be accurately detected from the preamble in the quasi-coherent detection, and the margin for noise can be improved.

In one embodiment of the present invention, in the demodulation device, the delay difference section delays the phase sampling data sampled by the quasi-synchronous detection section by shifting the phase sampling data by n stages with the sampling clock; A phase difference calculation unit for calculating a phase difference between the phase sampling data delayed by the shift register and the phase sampling data before the delay, wherein the preamble detection unit includes a phase difference calculated by the phase difference calculation unit. Is determined to be in a detection window including an upper limit value set above the reference phase difference stored in the reference phase difference storage unit and a lower limit value set below the reference phase difference. When the preamble detection window and the preamble detection window determine that the phase difference is within the detection window, When the preamble detection window unit determines that the phase difference is not within the detection window, the preamble is detected when the count value of the up / down counter that counts down and the count value of the up / down counter exceeds a predetermined value. And a preamble determination unit that determines

According to the demodulation device of the embodiment, the phase sampling data sampled by the quasi-synchronous detection unit is shifted by the sampling clock by the shift register by n stages. Next, the phase difference calculator calculates the phase difference between the phase sampling data delayed by the shift register and the phase sampling data before the delay. The phase difference calculated by the phase difference calculation unit is a detection window consisting of an upper limit value set above the reference phase difference in the reference phase difference storage unit and a lower limit value set below the reference phase difference. It is determined by the preamble detection window whether or not there is an entry. That is, it is determined whether or not the phase difference calculated by the phase difference calculation unit is within the range between the upper limit and the lower limit. When the preamble detection window unit determines that the phase difference is within the detection window, the up-down counter is counted up, while the preamble detection window unit determines that the phase difference is not within the detection window. Then, the up / down counter counts down. Thus, when the count value of the up / down counter exceeds a predetermined value, it is determined that the preamble determination unit has detected the preamble. Therefore, the preamble can be reliably detected with a simple configuration.

In one embodiment of the present invention, in the demodulation device, the phase comparison section stores the phase difference obtained by the delay difference section and the reference phase difference storage section during a period in which the preamble is detected by the preamble detection section. A phase comparison level histogram unit for taking a difference from the reference phase difference and binarizing the same, and outputting a count-up signal and a count-down signal in accordance with positive or negative for each bit value of the binarized difference, A frequency difference calculation unit pairs the pair having the same absolute value of the difference binarized by the phase comparison level histogram unit and counts up by a count-up signal corresponding to the pair, while counting down by a count-up signal corresponding to the pair. Up / down counters for counting down, and count values of the up / down counters for difference And a phase difference accumulating unit for accumulating the weighted count values of the differential up / down counters after weighting according to the absolute value of the binarized difference.

According to the demodulation device of the embodiment, the phase comparison level histogram section stores the phase difference obtained by the delay difference section and the reference phase difference storage section during the period when the preamble is detected by the preamble detection section. A binary value is obtained by taking the difference from the reference phase difference, and a count-up signal and a count-down signal are output according to the sign of each bit value of the binary difference. Then, pairs having the same absolute value of the difference binarized by the phase comparison level histogram unit but different signs are paired, and the pair is associated with each difference up / down counter, and a count-up signal corresponding to the pair is provided. , Each differential up / down counter is counted up, while each differential up / down counter is counted down by a countdown signal corresponding to the pair. The phase difference accumulator weights the count value of each differential up / down counter in accordance with the absolute value of the binarized difference. That is, when the difference is, for example, 2 bits, the counter value is weighted to double, and when the difference is 1 bit, the counter value is weighted (1 time) as it is. The weighted count values of the difference up / down counters are integrated. By doing so, the integrated value of the difference between the phase difference obtained by the delay difference unit and the reference phase difference stored in the reference phase difference storage unit can be obtained with a simple configuration, and the circuit scale can be reduced.

In one embodiment, the frequency difference calculating section divides the integrated count value integrated by the phase difference integrating section by the number of samples in a period during which the preamble detecting section detects the preamble. By
An average value calculating unit that calculates an average value per unit sampling of the frequency difference, wherein the frequency correction unit is configured to calculate the average value per unit sampling of the frequency difference calculated by the average value calculating unit. The frequency of the phase sampling data sampled by the quasi-synchronous detector is corrected.

According to the demodulation device of the above embodiment, the average value calculating section divides the integrated count value integrated by the phase difference integrating section by the number of samples in a period during which the preamble is detected by the preamble detecting section. Then, the average value of the frequency difference per unit sampling is calculated. Then, the frequency of the phase sampling data sampled by the quasi-synchronous detection unit is corrected by the frequency correction unit based on the average value of the frequency difference per unit sampling. Therefore, the frequency of the phase sampling data can be easily corrected from the integrated count value integrated by the phase difference integrating unit.

In one embodiment of the present invention, in the demodulation device, the phase comparison level histogram section calculates a difference between the phase difference obtained by the delay difference section and the reference phase difference stored in the reference phase difference storage section. The difference upper limit value and the difference lower limit value are set, and the difference out of the range of the difference upper limit value and the difference lower limit value is excluded, and the average value calculation unit calculates the difference from the total number of samples in the detection period of the preamble detection unit. An average value per unit sampling of the frequency difference is calculated by dividing the integrated count value by the number of samples obtained by subtracting the number of samples of the difference excluded in the phase comparison level histogram section.

According to the demodulation apparatus of the above embodiment, the phase comparison level histogram section calculates the difference between the phase difference obtained by the delay difference section and the reference phase difference stored in the reference phase difference storage section. An upper limit value and a difference lower limit value are set, and a difference out of the range of the difference upper limit value and the difference lower limit value is excluded. Then, the integrated count value is divided by the average value calculation unit by the number of samples obtained by subtracting the number of samples of the difference excluded by the phase comparison level histogram unit from the total number of samples in the detection period of the preamble detection unit. Then, the average value of the frequency difference per unit sampling is calculated. Thus, when noise is superimposed on the phase sampling data, it is possible to exclude a phase difference that is larger than the reference phase difference from the phase difference obtained by the delay difference unit. Also, by dividing the accumulated count value by the number of samples excluded from the total number of samples by the number of phase sample data that deviates from the reference phase difference (total number of samples minus the number of excluded samples), the average of the frequency difference per unit sampling is obtained. Find the value. Therefore, even if an error caused by noise occurs in the preamble, the phase sampling data is removed.
The margin for noise can be further improved.

Further, the demodulation device of the present invention can
A quasi-synchronous detector for receiving a / 4 shift QPSK modulated wave as an input signal and sampling the phase of the input signal using a sampling clock generated from a reference oscillator of a receiver, and a unique word of an information channel of the input signal. , A UW symmetry detecting section for detecting a unique word area having a phase change substantially symmetric in the time axis direction from the phase sampling data sampled by the quasi-synchronous detecting section, and the substantially symmetric detecting section detected by the UW symmetry detecting section. A unique word difference unit for calculating a phase difference between phase sampling data having a symmetrical relationship with each other for phase sampling data in a unique word region having a large phase change, and a condition of a π / 4 shift QPSK modulated wave transmitted from a transmitter. Based on the above, a unique word region having a substantially symmetric phase change For the phase sampling data, the phase difference between the phase sampling data having a symmetrical relationship with each other is determined in advance, and the phase difference is stored as a reference unique word phase difference. UW for calculating a frequency difference of a carrier based on the phase difference between phase sampling data having a symmetrical relationship and the reference unique word phase difference stored in the reference unique word storage unit.
A frequency difference calculation unit, and a UW frequency correction unit that corrects the frequency of the phase sampling data sampled by the quasi-synchronous detection unit based on the carrier frequency difference calculated by the UW frequency difference calculation unit. A demodulation unit that reproduces a demodulated clock using the phase sampling data corrected by the UW frequency correction unit and obtains demodulated data from the corrected phase sampling data based on the demodulated clock. I have.

According to the demodulation device having the above configuration, the quasi-synchronous detector samples the phase of the π / 4 shift QPSK modulated wave using the sampling clock generated from the reference oscillator. Then, in the unique word for identifying the information channel of the input signal, attention is paid to a region having a phase change substantially symmetric in the time axis direction. FIG. 14 shows the phase change of the unique word of this information channel. The left and right phases in the time axis direction around time a are almost symmetrical in the region of the arrow period (the vertical axis in FIG. , The horizontal axis is time). FIG. 15 shows the difference between the phase sampling data having a symmetrical relationship with each other in the unique word area. The phase difference during the UW difference period indicated by the arrow is almost 0 (the vertical axis in FIG. 15 indicates the position). Phase difference, horizontal axis is time). The phase difference in the UW difference period fluctuates due to the frequency error of the carrier, and can be used for estimating the frequency error.

Based on the conditions of the π / 4 shift QPSK modulated wave on the transmitter side, the reference value of the phase difference of the unique word area whose phase change is substantially symmetric is determined in advance by calculation or the like, and the reference value is set as the reference unique word phase difference. Store in the unique word storage. Based on the phase difference between the symmetrically-phased sampling data obtained by the unique word difference section and the reference unique word phase difference stored in the reference unique word storage section, the frequency of the carrier wave is calculated by a UW frequency difference calculation section. Calculate the difference. Then, based on the frequency difference of the carrier calculated by the UW frequency difference calculator, the UW frequency corrector corrects the frequency of the phase sampling data sampled by the quasi-synchronous detector. Next, a demodulation clock is reproduced using the phase sampling data corrected by the UW frequency correction section, and demodulation data is obtained based on the demodulation clock.

Therefore, in quasi-synchronous detection, the frequency difference can be accurately detected from the unique word of the information channel having a short preamble pattern, and the margin for noise can be improved.

In one embodiment, the demodulation device is provided with the UW
A frequency difference calculating unit calculates a binary value by taking a difference between the phase difference obtained by the unique word difference unit and the reference unique word phase difference stored in the reference unique word storage unit during the unique word period of the information channel. A UW phase comparison level histogram section that outputs a count-up signal and a count-down signal in accordance with the sign of the difference for each of the binarized bit values, and a difference between the binarized difference in the UW phase comparison level histogram section. A pair having the same absolute value is paired, and while counting up by a count-up signal corresponding to the pair, a plurality of up-down counters that count down by a count-down signal corresponding to the pair, and a count value of the plurality of up-down counters After weighting according to the absolute value of the binarized difference And a UW phase difference integrating section for integrating the weighted count value.

According to the demodulation device of the above embodiment, the U
The W phase comparison level histogram is binarized by taking the difference between the phase difference obtained by the unique word difference section and the reference unique word phase difference stored in the reference unique word storage section during the unique word period of the information channel. And outputs a count-up signal and a count-down signal in accordance with the sign of the difference for each of the binarized bit values.
Next, pairs having the same absolute value of the binarized difference in the UW phase comparison level histogram section are paired, each pair is associated with each up-down counter, and each up-down counter is associated with a count-up signal corresponding to the pair. While counting down the down counter, each up / down counter is counted down by a countdown signal corresponding to the pair. Then, the UW phase difference integrating unit weights the count value of each up / down counter according to the absolute value of the binarized difference. That is,
When the difference is, for example, 2 bits, the counter value is weighted to double, and when the difference is 1 bit, the counter value is weighted as it is (1 time). Then, the weighted count value is integrated. By doing so, the integrated value of the difference between the phase difference obtained by the delay difference section and the reference unique word phase difference stored in the reference unique word storage section can be obtained with a simple configuration, and the circuit scale can be reduced.

In one embodiment, the demodulation device includes the UW
The frequency difference calculating unit divides the integrated count value integrated by the UW phase difference integrating unit by half the number of samples in the period in which the unique word area is detected by the UW symmetry detecting unit. A UW average value calculation unit for calculating an average value per unit sampling; the frequency correction unit based on the average value per unit sampling of the frequency difference calculated by the UW average value calculation unit; The frequency of the phase sampling data sampled by the synchronous detection unit is corrected.

According to the demodulation device of the above embodiment, the U
By dividing the accumulated count value accumulated by the UW phase difference accumulating section by the W average value computing section by サ ン プ ル the number of samples in the period in which the unique word area is detected by the UW symmetry detecting section, the frequency difference is calculated. Calculate the average value per unit sampling. And the frequency correction unit is
The frequency of the phase sampling data sampled by the quasi-synchronous detection unit is corrected based on the average value per unit sampling of the frequency difference calculated by the UW average value calculation unit. Therefore, the frequency of the phase sampling data can be easily corrected from the integrated count value integrated by the UW phase difference integrating unit.

[0035]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram of a demodulator according to the present invention. In this embodiment, RCR (Radio System Development Center)
-It is assumed that it is applied to PHS based on STD28.

(First Embodiment) FIG. 1 is a block diagram showing a configuration of a demodulation device according to a first embodiment of the present invention. In FIG. 1, 1 indicates the phase of the π / 4 shift QPSK modulation signal as 2
A quasi-synchronous detection unit that samples at n (n is an integer of 2 or more) sampling intervals per symbol, a carrier generation unit that outputs a sampling clock to the quasi-synchronous detection unit 1, and a quasi-synchronous detection unit 3 Is delayed by two symbols, and a delay difference unit 4 for calculating a phase difference between the delayed phase sampling data and the phase sampling data before delay is used to generate a preamble based on the phase difference from the delay difference unit 3. A preamble detector 5 for detecting the phase difference is a phase comparator for comparing the phase difference from the delay difference unit 3 with the reference phase difference stored in the reference phase difference storage 51, and 6 is a comparison result of the phase comparator 5. A frequency difference calculator 7 for calculating the frequency difference of the carrier based on the frequency difference calculated by the frequency difference calculator 6,
A frequency correction unit for correcting the frequency of the phase sampling data, 8 is a data demodulation unit for demodulating data from the phase sampling data corrected by the frequency correction unit 7, and 9 is a phase sampling data corrected by the frequency correction unit 7. Is a clock reproducing unit that reproduces a demodulated clock based on the demodulated clock and supplies the demodulated clock to the data demodulating unit 8. The quasi-synchronous detection unit 1 and the carrier generation unit 2 constitute a quasi-synchronous detection circuit block 10, and the data demodulation unit 8 and the clock recovery unit constitute a demodulation circuit block 20 as a demodulation unit.

FIG. 2 is a block diagram showing details of the configuration of the quasi-synchronous detection circuit block 10. In the quasi-synchronous detection unit 1, a π / 4 shift QPSK modulation signal is input to one input terminal. An exclusive-OR circuit 11, a low-pass filter 12 to which the output of the exclusive-OR circuit 11 is input, a first phase sampling unit 13 to which an output of the low-pass filter 12 is input, and an output of the low-pass filter 12. Is input to the second phase sampling unit 14
A phase averaging unit 15 that averages the phase sampling data output from the first and second phase sampling units, and a latch 16 that holds the phase sampling data output from the phase averaging unit 15 in accordance with a sampling clock. Have. Further, the carrier generation unit 2 includes a reference oscillator 2
1, a frequency divider 22 for dividing the reference signal from the reference oscillator 21 by 1 / h and inputting the frequency-divided signal to the other input terminal of the exclusive OR circuit 11, and the reference oscillator 2
A counter 23 that counts the reference signal from 1 and outputs a count output to the second phase sampling unit 14;
A phase shifter 2 for delaying the output of the counter 23 by π / 2 phase
4 and a frequency divider 25 for dividing the reference signal from the reference oscillator 21 by 1 / g and outputting the frequency-divided signal as a system clock. The above system clock is
The signal is input to the clock input terminal of the latch 16.

In FIG. 2, a quasi-synchronous detection unit 1 detects and outputs a phase difference (hereinafter, referred to as an instantaneous phase) of a π / 4 shift QPSK modulation signal based on a carrier signal. Further, the carrier generation unit 2 performs the π / 4 shift QPS
The frequency is asynchronous with the K modulation signal, but is substantially the same as the carrier of the π / 4 shift QPSK modulation signal. In a general synchronous detection method, a carrier generation section is controlled by a PLL (Phase-Locked Lo
op: a phase locked loop) to generate a carrier signal synchronized with the phase of the input π / 4 shift QPSK modulation signal.
In the first embodiment, a carrier that is asynchronous with respect to the input π / 4-shifted QPSK modulation signal is generated from the viewpoint of loss of lock.

In the quasi-synchronous detection circuit block 10, the input signal of the π / 4 shift QPSK modulation wave is converted into 2 by using the sampling clock generated from the reference oscillator.
Sampling is performed at a sampling interval of n (n is an integer of 2 or more) times per symbol. Then, the phase sampling data as the instantaneous phase signal from the quasi-synchronous detection circuit block 10 is input to the delay difference section 3 (shown in FIG. 1).

FIG. 3 is a block diagram showing the configuration of the delay difference section 3. The delay difference section 3 includes an n-stage shift register 31 for shifting phase sampling data in accordance with a sampling clock, and an n-stage shift register 31. And an adder 32 for subtracting the phase sampling data from the output of the shift register 31. The sampling cycle of the phase sampling data (instantaneous phase signal) is 25 samples per two symbols, and the n-stage shift register 31 has 25 stages. The n-stage shift register 31 delays the phase sampling data by two symbols. Then, a phase difference between the delayed phase sampling data and the phase sampling data before the delay is obtained by the adder 32.

FIG. 4 is a block diagram showing the structure of the preamble detector 4.
Is a PR_DET gate 41, an up / down counter 42, a threshold level determination unit 43, and a PR_DET
A circuit control 44. When receiving a control channel or a synchronization burst having a preamble pattern of 31 symbols, the preamble detector 4 detects it.

The PR_DET gate 41 determines a detection window including an upper limit value set on the upper side and a lower limit value set on the lower side with respect to the reference phase difference, and outputs the detection window from the delay difference section 3 (shown in FIG. 3). It is determined whether or not the input phase difference is within the detection window, and the determination result is counted by the up / down counter 42. That is, when the input phase difference is within the detection window, the up-down counter 4
On the other hand, when the input phase difference does not fall within the detection window, the up / down counter 42 counts down. Then, the count value of the up / down counter 42 becomes the predetermined value ThB of the threshold level.
Is exceeded, the threshold level determination unit 43 determines that the received signal (π / 4 shift QPSK modulation signal) is in the period of the preamble pattern. When the threshold level determination unit 43 determines that the received signal is in the period of the preamble pattern, the PR_DET control signal is output from the PR_DET circuit control 44 and the PR window which determines the number of samples counted by the PR_DET gate 41 and the preamble period. And outputs the number of PR (preamble) samples based on. It should be noted that the flag / TCH is active when the channel is other than the information channel, and when the channel becomes the information channel, the operation of the preamble detector 4 stops.

FIG. 5 is a block diagram showing the configuration of the phase comparing section 5 and the frequency difference calculating section 6. The frequency difference calculation unit 6 includes difference up / down counters 61 and 62 that perform up / down operations based on the comparison result from the phase comparison unit 5.
A multiplier 63 for doubling the count value of the output of the difference up / down counter 61; and a count value output from the multiplier 63 and a difference up / down counter 62.
An adder 64 for adding the count value output from
An average value calculator 65 divides the addition result of the adder 64 by the number of PR (preamble) samples.

The phase comparing section 5 is a circuit for distributing a phase comparison result which is a difference between the phase difference obtained by the delay difference section 5 and the reference phase difference during a period when the preamble is detected. That is, the phase comparison unit 5 sets a difference upper limit (+2 bits) above the reference phase difference,
A phase comparison level histogram section in which a difference lower limit value (−2 bits) is set below the reference phase difference, wherein +2
It has gates 5a to 5d through which the respective differences of bits, +1 bit, -1 bit and -2 bit pass. A pair (+ 2 / −2, + 1 / −1) having the same absolute value of the difference passed through each of the gates 5a to 5d is defined as a pair (+ 2 / −2, + 1 / −1). , 62. That is, +2
, The difference up / down counter 61 is counted up by the count up signal of the output of the gate 5a corresponding to +2, while the count up of the difference up / down counter 61 is counted down by the count down signal of the output of the gate 5d corresponding to + −2, The differential up / down counter 62 is counted up by the output count-up signal of the gate 5b corresponding to (1), while the differential up-down counter 62 is counted down by the count-down signal of the output of the gate 5c corresponding to -1.
In this case, the difference 0 bit is 0 even if the multiplied count value is multiplied by any coefficient, and becomes 0 even if the multiplied count value is multiplied. During the counting period, the counting operation of the differential up / down counters 61 and 62 is enabled based on the start and stop flags (PR_DET control signal) from the preamble detector 4. Next, + 2 / -2, + 1 / -1
After weighting the outputs of the difference up / down counters 61 and 62 according to the number of bits of each difference, that is, the output of the difference up / down counter 61 whose absolute value of the difference corresponds to 2 bits includes: The multiplier 63 multiplies the weight by 2 to obtain a weight of 2, while the absolute value of the difference becomes the weight 1 as it is as the output of the differential up / down counter 62 corresponding to 1 bit. An integrated value of the binarized difference is obtained.

The number of PR (preamble) samples in this case is given by (total number of samples during the period in which the preamble is detected)-(number of samples outside the detection window set by the phase comparator). Then, the average value calculation unit 65
Calculates the average value by dividing the output of the adder 64 by the total number of samples, and calculates the frequency difference per unit sampling.

FIG. 6 is a block diagram of the frequency compensator 7. The frequency compensator 7 includes a delay unit 71 for delaying phase sampling data and a delay unit 7 for delaying the phase sampling data.
A correction unit 72 for correcting the frequency of the phase sampling data delayed by 1; and a phase difference / 1 sample unit for converting a frequency difference from the average value calculation unit 65 (shown in FIG. 5) into a phase difference per sample. 73, an adder 74 whose phase difference per sample from the phase difference / one sample unit 73 is input to one input terminal and whose output is input to the correction unit 71, and an output of the adder 74. Delay
And a delay unit 75 for inputting to the other input terminal of the adder 74.

First, the frequency difference calculated by the average value calculating section 65 (shown in FIG. 5) is converted into a unit phase difference at a unit sampling time by the phase difference / 1 sampling section 73. The phase sampling data is delayed by the delay unit 71 during the arithmetic processing of the phase difference / 1 sampling unit 73, and the correction unit 72 adds (decreases) the unit phase difference m times to the delayed phase sampling data. Then, the frequency of the phase sampling data is corrected by the accumulated phase difference (where m is an integer that is incremented from 1 to the end of the slot for each phase sampling data). In the next control channel and synchronization burst slot,
With this value as the initial value, add (decrease) immediately after the quasi-synchronous detection output.
There is also a configuration to calculate.

Next, when moving to the information channel, new frequency difference detection and correction are not performed, and correction of a constant value is continued using the frequency correction value obtained in the immediately preceding control channel or synchronization burst. Here, if the reception channel is deteriorated and the information channel cannot be maintained, a synchronization burst is sent again from the base station, so that the frequency correction value is updated.
When the base station changes due to handover, the frequency correction value is reset, and a new frequency correction value is obtained again from the base station by a synchronization burst.

As described above, in the demodulator, the frequency difference can be accurately detected from the preamble in the quasi-synchronous detection, and the margin for noise can be improved.

Further, the preamble can be reliably detected by the simple configuration of the preamble detection section 4.

Further, the phase comparison section 5 (phase comparison level histogram section) and the frequency difference calculation section 6 (difference up / down counters 61 and 62, multiplier 63, adder 64, and average value calculation section 65) are simplified. With this configuration, an integrated value of the difference between the phase difference obtained by the delay difference unit 3 and the reference phase difference stored in the reference phase difference storage unit 51 can be obtained, and the circuit scale can be reduced.

Further, the frequency of the phase sampling data can be easily corrected from the accumulated count value accumulated by the phase difference accumulating section constituted by the multiplier 63 and the adder 64.

Further, in the average value calculating section 65, the PR which excludes from the total number of samples the number of phase sample data which is out of the range of not more than the difference upper limit value and not less than the difference lower limit value.
By dividing the accumulated count value by the number of samples,
Since the average value of the frequency difference per unit sampling is obtained, even if an error due to noise occurs in the preamble, the phase sampling data is removed, so that the margin for noise can be further improved.

(Second Embodiment) FIG. 7 is a block diagram showing a demodulator according to a second embodiment of the present invention. In the first embodiment, the timing is specified using a regular preamble pattern in the control channel and the synchronization burst. In the second embodiment, the symmetric phase change of the unique word in the information channel is focused. Then, the timing is specified and the frequency difference is detected.

In FIG. 7, 1 is a π / 4 shift QPSK.
A quasi-synchronous detection unit that samples the phase of the modulated signal at n (n is an integer of 2 or more) sampling intervals per two symbols, 2 is a carrier generation unit that outputs a sampling clock to the quasi-synchronous detection unit 1, and 101 is a control unit. The preamble frequency corrector 102 performs a frequency correction based on the frequency correction value of the channel or the synchronization burst. In the phase sampling data output from the preamble frequency corrector 101, a unique word area having a phase change substantially symmetric in a time axis direction is obtained. UW symmetry detection unit to detect, 103
Is a reference unique word storage unit that stores a reference unique word phase difference, and 104 is a U that calculates a frequency difference between unique words based on the detection result of the UW symmetry detection unit 102.
A W frequency difference calculating unit, 105, a UW frequency correcting unit for correcting the frequency of the phase sampling data corrected by the preamble frequency correcting unit 101, and 8, a demodulation of data from the phase sampling data corrected by the UW frequency correcting unit 105 The data demodulating unit 9 reproduces a demodulated clock from the phase sampling data corrected by the UW frequency correcting unit 105, and supplies the demodulated clock to the data demodulating unit 8.

In the preamble frequency correction section 101, the frequency correction value in the control channel and the synchronization burst is held in the information channel, and the flag / TC
When H is active, the same correction is made for each slot. When a demodulated data is processed, a baseband unit (not shown) detects a unique word from the information channel when the information channel is reached, determines that the channel is an information channel, and sets a flag TCH. When the flag TCH is set, it is determined that the channel is an information channel, and the UW frequency correction unit 1 shown in FIG.
05 and the like start operating, while the preamble frequency correction unit 101 stops.

FIG. 8 shows the UW symmetry detector 102 and the UW
FIG. 4 is a block diagram illustrating a specific configuration of blocks of a frequency difference calculation unit 104 and a reference unique word storage unit 103. The register 111 shifts phase sampling data by a sample clock, and the difference (phase difference) between outputs from the register 111. A unique word difference unit 112 having a plurality of difference blocks 112a for calculating a unique word difference unit 112, and a plurality of comparison blocks 113a for comparing a phase difference output from each difference block 112a of the unique word difference unit 112 with a reference unique word phase difference. A word comparing unit 113, an adder 114 for adding the comparison result of each comparing block 113a of the unique word comparing unit 113,
A UW determination unit 115 that determines whether or not the word region has a unique symmetrical phase change based on the addition result of the adder 114 and the flag TCH, and based on the determination result of the UW determination unit 115, And an average value calculation unit 116 for calculating the average value of the addition result of the unit 114.

The phase sampling data quasi-synchronously detected by the quasi-synchronous detection circuit block 10 is input to a P-stage shift register 111. This shift register 1
The output of the 11th qth stage and (P−q + 1) th stage (q is an integer) is P
/ 2 difference blocks 112a. After the phase difference from each of the difference blocks 112a is compared with the reference unique word phase difference by the comparison block 113a of the unique word comparison unit 113, it is added by the adder 114. Then, the UW determination unit 115 has a threshold level of, for example, ± 5 degrees near 0, and if the addition result by the adder 114 falls within the threshold level,
It is determined that the region is a unique word region having a substantially symmetric phase change, and the average value calculator 116 performs the following frequency difference calculation operation. In the comparison between each output of the difference block 112a of the unique word difference unit 112 and the reference unique word phase difference, a comparison (difference) with the previously calculated reference unique word phase difference is performed as shown in FIG.

Next, the frequency correction of the phase sampling data is performed by adding and subtracting the frequency difference per unit sampling to the original phase sampling data by the UW frequency correction unit 105 (shown in FIG. 7). This frequency correction is performed in the same manner as the frequency correction unit 7 shown in FIG. 6 of the first embodiment.

As described above, in the demodulator, the frequency difference can be accurately detected from the unique word of the information channel having a short preamble pattern in the quasi-synchronous detection, and the margin for noise can be improved.

Further, the frequency of the phase sampling data can be easily corrected from the integrated count value integrated by the adder 114 by the average value calculating section 116.

It is to be noted that, in place of the unique word comparing section 113 and the adder 114, the phase difference obtained by the unique word difference section 112 and the reference unique word stored in the reference unique word storage section 103 during the unique word period of the information channel. A UW phase comparison level histogram section for binarizing by taking a difference from the word phase difference and outputting a count-up signal and a count-down signal in accordance with the sign of the difference for each binarized bit value; A plurality of up-down counters that count as a pair with the same absolute value of the difference and count down with a count-down signal corresponding to the pair, and count down with a count-down signal corresponding to the pair; According to the absolute value of the binarized difference with respect to the count value of And a UW phase difference integrating unit that integrates the weighted count value after the weighting. In this case, the unique word difference unit 112
Difference and reference unique word storage unit 103 obtained by
Can be obtained with a simple configuration, and the circuit scale can be reduced.

The concept of the frequency correction of the information channel according to the second embodiment is mainly for the frequency correction in the control channel and the synchronization burst, and is supplementarily performed. For example, it is limited to ± 2 deg (the average value calculation unit 116 in FIG. 8). Also, when no unique word is detected by the unique word comparing unit 113 (ie,
(When the threshold level is +5 deg or more or -5 deg or less), the frequency correction by the unique word of the slot of the information channel is not performed.

In the first and second embodiments, the demodulation device used for the PHS has been described.
However, the present invention is not limited to this demodulator.

[0065]

As is clear from the above, according to the first demodulator of the present invention, the characteristic that the phase change of the instantaneous phase signal is patterned during the preamble pattern period of the control channel or the synchronization burst is used. A signal for correcting a frequency difference is formed, and even if sampling points do not match on a symbol, a method of detecting a difference between sampling point intervals to detect a constant phase difference. . In this method, since the number of phase sampling data is large, it is possible to easily remove phase sampling data on which noise is superimposed or phase sampling data including burst noise, thereby increasing the margin for noise at the time of frequency difference detection. Further, since the number of phase sampling data itself is large, the accuracy of frequency correction can be improved. Further, according to this demodulation device, the preamble can be detected with a simple configuration, and those having the same absolute value of the binarized difference are paired, and an up / down counter is counted for each pair, and This is a method of calculating an integrated value, in which phase sampling data with a lot of noise can be easily excluded, the frequency difference can be accurately calculated, and the integration is performed using an up-down counter, so that the circuit scale can be reduced.

According to the second demodulating apparatus of the present invention, it is difficult to detect a frequency difference due to a preamble in an information channel, so that a unique word period of the information channel has a phase change substantially symmetric in the time axis direction. Since the frequency difference is detected using the unique word area, the accuracy of the phase difference correction is higher than that of the moving average type circuit after demodulation, and the phase difference component shifted from the phase reference axis of the receiver is appropriately detected. Can be removed.

[Brief description of the drawings]

FIG. 1 is a block diagram of a demodulation device according to a first embodiment of the present invention.

FIG. 2 is a block diagram of a quasi-synchronous detection circuit block of the demodulation device.

FIG. 3 is a block diagram of a delay difference unit of the demodulation device.

FIG. 4 is a block diagram of a preamble detector of the demodulation device.

FIG. 5 is a block diagram of a phase comparison unit and a frequency difference calculation unit of the demodulation device.

FIG. 6 is a block diagram of a frequency correction unit of the demodulation device.

FIG. 7 is a block diagram of a demodulation device according to a second embodiment of the present invention.

FIG. 8 is a block diagram of a UW symmetry detection unit, a unique word difference unit, and a UW frequency difference calculation unit of the demodulation device.

9A is an explanatory diagram of a phase plane of an eight-phase digital modulation wave, and FIG. 9B is an explanatory diagram of a phase plane of a preamble pattern.

FIG. 10 is a diagram showing a trajectory of a preamble pattern.

FIG. 11A is a diagram illustrating a slot configuration of a control channel and the like, and FIG. 11B is a diagram illustrating a slot configuration of an information channel.

FIG. 12 is a diagram showing a phase waveform in a preamble period of an information channel.

FIG. 13 is a diagram showing a phase waveform during a preamble period of a control channel.

FIG. 14 is a diagram showing a phase waveform of a unique word of an information channel.

FIG. 15 is a diagram showing a change in a phase difference of a unique word.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Semi-synchronous detection part, 2 ... Carrier generation part, 3 ... Delay difference part, 4 ... Preamble detection part, 5 ... Phase comparison part, 6 ... Frequency difference calculation part, 7 ... Frequency correction part, 8 ... Data demodulation part, 9 clock recovery unit 10 quasi-synchronous detection circuit block 11 exclusive OR circuit 12 low-pass filter 13 first phase sampling unit 14 second phase sampling unit 15 phase averaging unit 16 ... Latch, 20 ... Demodulation circuit block, 21 ... Reference oscillator, 22 ... 1 / h frequency divider, 23 ... Counter, 24 ... π / 2 phase shifter, 25 ... 1 / g frequency divider, 31 ... N-stage shift register 32, an adder, 41, a PR_DET gate, 42, 61, 62, an up / down counter, 43, a threshold level judging unit, 44, a PR_DET circuit control 61, 62, a differential up Counter: 63: multiplier; 64: adder; 65: average calculator; 71: delay unit; 72: correction unit; 73: phase difference / one sample unit; 74: adder; ... Preamble frequency corrector 102, UW symmetry detector 103, reference unique word storage 104, UW frequency difference calculator 105, UW frequency corrector 111, shift register 112, unique word difference 113 Unique word comparison unit, 114: adder, 115: UW determination unit, 116: average value calculation unit

Claims (8)

[Claims] 1. A received π / 4-shifted QPSK modulated wave is received as an input signal, and the phase of the input signal is n per two symbols (n is an integer of 2 or more) using a sampling clock generated from a reference oscillator. A quasi-synchronous detector that samples at a sampling interval of one time, and delays the phase sampling data sampled by the quasi-synchronous detector by a time required for n times of sampling, and delays the delayed phase sampling data and the phase sampling before the delay. A delay difference section for calculating a phase difference from data; and the phase of the symbol of the input signal makes a π / 4 transition with respect to the immediately preceding symbol and the phase of the next symbol makes a -3π / 4 transition is alternately repeated. A preamble detection unit for detecting a preamble of a specific pattern, and a π / 4 shift QPS transmitted from a transmitter side A reference phase difference storage unit that stores a reference phase difference between two symbols in the predetermined preamble based on a condition of the modulated wave; a phase difference obtained by the delay difference unit; A phase comparison unit that compares the reference phase difference stored in the preamble detection unit; and a frequency difference calculation unit that calculates a frequency difference of a carrier based on a comparison result of the phase comparison unit during a period in which a preamble is detected by the preamble detection unit. A frequency correction unit that corrects the frequency of the phase sampling data sampled by the quasi-synchronous detection unit based on the frequency difference of the carrier wave calculated by the frequency difference calculation unit; and A demodulated clock is reproduced using the corrected phase sampling data, and the corrected phase sampler is reproduced based on the demodulated clock. Demodulating apparatus characterized by comprising a demodulator for obtaining a demodulated data from pulling data. 2. The demodulation device according to claim 1, wherein the delay difference unit delays the phase sampling data sampled by the quasi-synchronous detection unit by shifting the phase sampling data by n stages with the sampling clock. A phase difference calculator for calculating a phase difference between the phase sampling data delayed by the shift register and the phase sampling data before the delay, wherein the preamble detector is calculated by the phase difference calculator. Whether or not the phase difference is within a detection window including an upper limit value set above the reference phase difference stored in the reference phase difference storage unit and a lower limit value set below the reference phase difference. And a preamble detection window that determines whether the phase difference is within the detection window. When counting up, the preamble detection window unit determines that the phase difference is not within the detection window, and detects an up-down counter that counts down and a preamble when the count value of the up-down counter exceeds a predetermined value. And a preamble determining unit that determines that the demodulation has been performed. 3. The demodulator according to claim 1, wherein the phase comparison unit stores the phase difference obtained by the delay difference unit and the reference phase difference during a period in which the preamble is detected by the preamble detection unit. A phase comparison level histogram unit that takes a difference from the reference phase difference stored in the unit and binarizes it, and outputs a count-up signal and a count-down signal in accordance with positive or negative for each bit value of the binarized difference The frequency difference calculation unit pairs the pair having the same absolute value of the binarized difference in the phase comparison level histogram unit, and counts up by a count-up signal corresponding to the pair. A plurality of differential up / down counters that count down by a corresponding countdown signal; and the plurality of differential up / down counters. And a phase difference accumulator for accumulating the weighted count values of the differential up / down counters after weighting the count values of the data according to the absolute value of the binarized difference. Characteristic demodulator. 4. The demodulation device according to claim 3, wherein the frequency difference calculation unit calculates the integrated count value integrated by the phase difference integration unit with the number of samples in a period during which the preamble detection unit detects the preamble. An average value calculating unit for calculating an average value per unit sampling of the frequency difference by dividing the frequency difference unit, wherein the frequency correcting unit calculates an average value per unit sampling of the frequency difference calculated by the average value calculating unit. A demodulator that corrects the frequency of the phase sampling data sampled by the quasi-synchronous detector based on 5. The demodulation device according to claim 3, wherein the phase comparison level histogram section includes a phase difference obtained by the delay difference section and the reference phase difference stored in the reference phase difference storage section. The difference upper limit value and the difference lower limit value are set for the difference, and the difference that is out of the range of the difference upper limit value and the difference lower limit value is excluded. By dividing the integrated count value by the number of samples obtained by subtracting the number of samples of the difference excluded in the phase comparison level histogram section from the number of samples, an average value per unit sampling of the frequency difference is calculated. Demodulator. 6. A quasi-synchronous detector that receives the received π / 4-shifted QPSK modulated wave as an input signal and samples the phase of the input signal using a sampling clock generated from a reference oscillator of a receiver. A UW symmetry detection unit for detecting a unique word region having a phase change substantially symmetric in a time axis direction from phase sampling data sampled by the quasi-synchronous detection unit in a unique word of an information channel of an input signal; A unique word difference section for calculating a phase difference between phase sampling data having a symmetrical relationship with each other with respect to the phase sampling data of the unique word area having a substantially symmetric phase change detected by the section; The above substantially symmetric phase change based on the condition of the 4-shift QPSK modulated wave A phase difference between phase sampling data having a symmetrical relationship with each other with respect to the phase sampling data of the unique word area having the reference word unique storage section for storing the phase difference as a reference unique word phase difference; A UW frequency difference calculation unit that calculates a frequency difference of a carrier based on the phase difference of the phase sampling data and the reference unique word phase difference stored in the reference unique word storage unit, obtained by A UW frequency correction unit that corrects the frequency of the phase sampling data sampled by the quasi-synchronous detection unit based on the carrier frequency difference calculated by the UW frequency difference calculation unit; Use the phase sampling data corrected by A demodulation unit that reproduces a demodulated clock and obtains demodulated data from the corrected phase sampling data based on the demodulated clock. 7. The demodulation device according to claim 6, wherein the UW frequency difference calculation unit stores a phase difference obtained by the unique word difference unit and a reference unique word storage unit during a unique word period of the information channel. U which takes the difference from the stored reference unique word phase difference and binarizes it, and outputs a count-up signal and a count-down signal in accordance with the sign of the difference for each binarized bit value
A pair having the same absolute value of the difference binarized by the W phase comparison level histogram unit and the UW phase comparison level histogram unit is paired, and counted up by a count up signal corresponding to the pair. A plurality of up / down counters that count down by a countdown signal to be counted, and weighting the count values of the plurality of up / down counters in accordance with the absolute value of the binarized difference. A demodulation device comprising: a UW phase difference accumulating unit for accumulating. 8. The demodulation device according to claim 6, wherein the UW frequency difference calculation unit detects the accumulated count value accumulated by the UW phase difference accumulation unit, and detects a unique word area by the UW symmetry detection unit. A UW average calculating unit for calculating an average value per unit sampling of the frequency difference by dividing by a half of the number of samples of the period, wherein the frequency correcting unit is calculated by the UW average calculating unit A demodulator for correcting the frequency of the phase sampling data sampled by the quasi-synchronous detector based on an average value of the frequency difference per unit sampling.