JP2001285136A - Synchronization following circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a digital synchronization following circuit which reduces errors in received modulation data. SOLUTION: The circuit is provided with a punctual correlation device 8 for performing inverse spreading at the position of a reference phase with respect to a spread spectrum signal and outputting a correlation value by each symbol, an early correlation device 1 for performing inverse spreading at a position where the phase is advanced by Δ chip from the reference phase and outputting a correlation value by each symbol and a late correlation device 2 for performing inverse spreading at a position where the phase is delayed by Δ chip from the reference phase and outputting a correlation value by each symbol. The operation clock with respect to the device 8 is made faster than the operation clock with respect to the device 1 and the device 2.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a spread spectrum communication system and a spread spectrum communication technology using the spread spectrum communication technology.
The present invention relates to a synchronization tracking circuit used in a receiver of a DMA (Code Division Multiple Access) system.

[0002]

2. Description of the Related Art Spread-spectrum communication systems and CDMA systems using spread-spectrum communication technology are resistant to multipath fading, can speed up data, have good communication quality, and have good frequency use efficiency. It is a promising communication method for next generation mobile communication and multimedia wireless communication.

In this spread spectrum communication, the transmitting side spreads a signal over a band much wider than the bandwidth of the signal to be transmitted and transmits the signal. On the other hand, the receiving side is required to have a function of restoring the spread spectrum signal to the original signal bandwidth. The operation of restoring the original signal bandwidth in this way is called despreading, and a method of performing despreading by a matched filter and a method of performing despreading by sliding correlation are known. In particular, the sliding correlation method is widely used because of its easy configuration, and an initial synchronization function is executed by the sliding correlation, and the synchronization is completed by the operation of following or maintaining the synchronization. As described above, the synchronization tracking function is one of the most important functions of the spread spectrum communication technology.

[0004] Conventionally, a technique described in, for example, Japanese Patent Application Laid-Open No. H11-234168 has been known as a synchronous follow-up circuit for correlation processing on spread signals. This conventional synchronous tracking circuit will be described with reference to the drawings. FIG. 3 is a block diagram showing a conventional synchronous tracking circuit. In FIG. 3, members having the same functions as those of the synchronization tracking circuit according to the present invention, which will be described in detail later, are given the same reference numerals and described.

[0005] As shown in FIG. 3, the conventional synchronous tracking circuit includes an early correlator for outputting a correlation value at a position advanced by Δ chips (for example, チ ッ プ chip) from the reference phase with respect to the received signal 10. 1, a late correlator 2 for outputting a correlation value at a position delayed by Δ chips (for example, チ ッ プ chip) from the reference phase, a punctual correlator 8 for outputting a correlation value at the reference phase,
A comparator 3 that compares the correlation value from the early correlator 1 with the correlation value from the late correlator 2, and a chip clock phase (hereinafter referred to as chip CL) based on the comparison result from the comparator 3.
Loop filter 4 for performing control of K phase)
And a sample clock (hereinafter, referred to as a sample CLK)
(Hereinafter referred to as CLK generator) 5 for generating the clock signal, and a chip clock phase adjuster (hereinafter referred to as chip CLK) for adjusting the chip CLK phase based on the phase control signal from the loop filter 4. 6) and a chip code outputted from the chip CLK phase adjuster 6, a spread code having a .DELTA. Chip phase advanced from a reference phase, a spread code having a .DELTA. Chip phase delayed and a reference phase. And a spreading code generator 7 for generating a spreading code of

[0006] The CLK generator 5 is a device for generating a master clock (hereinafter, referred to as a master CLK) of the receiver.
K is output to the chip CLK phase adjuster 6. Chip CL
The K phase adjuster 6 generates a chip CLK based on the output control signal of the loop filter 4, and outputs the chip CLK to the spreading code generator 7, the early correlator 1, the late correlator 2, and the punctual correlator 8. .

The spreading code generator 7 generates ΔΔ
The spreading code with the chip phase advanced is output to the early correlator 1, the spreading code with the Δ chip phase delayed with respect to the reference phase is output to the late correlator 2, and the spreading code with the reference phase is output to the punctual correlator 8. I do. Early correlator 1 and la receiving chip CLK and spreading code
The te correlator 2 despreads the received signal 10 to obtain a correlation for each symbol, and outputs the result to the comparator 3. In the comparator 3,
The correlation values in the early correlator 1 and the late correlator 2 are compared, and the comparison result is output to the loop filter 4.

The loop filter 4 averages the received comparison results and instructs the chip CLK phase adjuster 6 to adjust the phase. When receiving the instruction to advance the phase, the chip CLK phase adjuster 6 that has received the instruction to adjust the phase from the loop filter 4 advances the phase of the chip CLK by, for example, チ ッ プ chip. On the other hand, when an instruction to delay the phase is received, the phase is delayed by, for example, チ ッ プ chip with respect to the chip CLK.

[0010] By repeating the above operation, synchronous tracking is performed. For details of this synchronization tracking, see "Mitsuo Yokoyama," Spread Spectrum Communication System "
pp. 290-300 ”. punctu
The al correlator 8 performs correlation between the spread code of the reference phase and the received signal, that is, performs despreading, and outputs demodulated data for each symbol.

[0010]

However, in the above-described conventional synchronous follow-up circuit, since the signal sampled for each chip is despread, the spreading factor is low, and the C / N (signal-to-noise ratio) is low. ) Decreases, the noise is not sufficiently averaged, and the influence of the noise on the signal increases. For this reason, there is a problem that an error easily occurs in the received demodulated data output from the punctual correlator 8.

The present invention has been proposed in view of the above circumstances, and has as its object to provide a digital synchronization follow-up circuit having few errors in received demodulated data.

[0012]

The synchronous tracking circuit according to the present invention has the following features in order to achieve the above object.

That is, the synchronous tracking circuit according to the present invention comprises:
An early correlator for performing despreading on the received spread spectrum signal at a position advanced by the Δ chip phase from the reference phase and outputting a correlation value for each symbol; A late correlator for performing despreading at a position where the chip phase is delayed, and outputting a correlation value for each symbol, and performing despreading at a reference phase position for the spread spectrum signal, and calculating a correlation value for each symbol. A punctual correlator for output;
The correlation value output from the early correlator and the la
a comparator for comparing the correlation values output from the te correlator, a loop filter for controlling the chip clock phase based on the output signal of the comparator, and a loop filter based on the control signal of the loop filter. A chip clock phase adjuster for adjusting a chip clock phase, and respective spread codes shifted by + Δ chip phase or −Δ phase with respect to a reference phase based on a chip clock output from the chip clock phase adjuster. And a spread code generator for generating a spread code of a reference phase and the pu based on the phase timing from the chip clock phase adjuster.
Synchronous tracking circuit including a sample clock phase adjuster for adjusting an operation clock for an nctual correlator, and a clock generator for generating a master clock for the chip clock phase adjuster and the sample clock phase adjuster In the above-mentioned punct
The operating clock for the ual correlator is the aforementioned early
It is characterized by being faster than the operating clock for the correlator and the late correlator.

The operation clock for the punctual correlator may be the same sample clock signal as a sampling clock in an analog-to-digital converter for converting a received signal into a digital signal.

The operation clock for the punctual correlator is the same sample clock signal as the sampling clock in the analog-to-digital converter for digitally converting the received signal, and the sample clock signal is switched based on the spreading factor. It is also possible.

In this case, when N is an integer of 2 or more, the master clock used in the synchronization follow-up circuit is 2 times the chip clock and N times the sample clock.
Is a positive integer, it is preferable to switch the sample clock based on the spreading factor so that N ≧ K, which is a multiple of 2 times the chip clock.

Further, it is preferable that 2 ≦ N ≦ 5 in the master clock used in the synchronous tracking circuit.

In the synchronous tracking circuit of the present invention having such a configuration, when the C / N is reduced and the spreading factor is low, the noise is averaged by increasing the number of samplings. Therefore, depending on the spreading factor of the received signal, pun
By changing the sample CLK of the ctual correlator, noise can be averaged efficiently and a synchronous tracking circuit with less reception errors can be configured. Note that punct
Since the ual correlator has a configuration prepared for a case where the spreading factor is high, a reception error can be reduced without complicating the configuration of the device.

[0019]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a synchronous tracking circuit according to the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram illustrating a synchronization tracking circuit according to an embodiment of the present invention. As shown in FIG. 1, the synchronization tracking circuit according to the embodiment of the present invention outputs an early value for outputting a correlation value at a position advanced by Δ chips (for example, チ ッ プ chip) from the reference phase with respect to the received signal 10. Correlator 1 and Δ from reference phase
Late correlator 2 for outputting a correlation value at a position delayed by a chip (for example, １ ／ chip), punctual correlator 8 for outputting a correlation value at a reference phase, and correlation value from early correlator 1 And a comparator 3 that compares the correlation value from the late correlator 2 with a chip clock (chip CLK) based on the comparison result from the comparator 3.
Filter 4, a clock generator (CLK generator) 5 for generating a sample clock (sample CLK), and a chip clock (chip CLK) based on a phase control signal from the loop filter 4. Clock phase adjuster (chip CLK phase adjuster) 6 for performing phase adjustment of
And a spreading code generator 7 for generating a spreading code in which the Δ chip phase is advanced with respect to the reference phase, a spreading code in which the Δ chip phase is delayed and a spreading code of the reference phase based on the chip CLK output from Have.

As described above, in the synchronization tracking circuit according to the present embodiment, since the synchronization tracking operation is realized by using the correlation value from the early correlator 1 and the correlation value from the late correlator 2, the function Specifically, the same operation as that of the conventional synchronous tracking circuit shown in FIG. 3 is performed.

Next, with reference to FIGS. 1 and 2, characteristic functions and operations of the synchronous tracking circuit according to the present embodiment will be described. As shown in FIG. 1, the sample CLK phase adjuster 9 generates a clock using the CLK phase signal from the chip CLK phase adjuster 6 as a reference phase. This clock functions as a clock for the punctual correlator 8 and, at the same time, although not shown in FIG.
It also functions as a sampling clock for D (analog-digital) conversion. Therefore, in the synchronous tracking circuit according to the present embodiment, the clock of the punctual correlator 8 and the clock for AD conversion are commonly used, and are therefore referred to as a sample CLK.

The sample CLK phase adjuster 9 generates an operation clock of the punctual correlator 8, that is, a sample CLK signal, from the phase timing of the chip CLK phase adjuster 6 according to the spreading factor of the received signal. The spreading factor of the received signal is a ratio between the spreading code rate and the baseband data rate. For example, for the baseband data or baseband symbol shown in FIG.
The speed of the spreading code shown in FIG.

The master CLK output from the CLK generator 5 shown in FIG. 2A is faster than the chip CLK shown in FIG. 2D. For example, master CL
Assuming that K is eight times faster than chip CLK, FIG.
As shown in (E), (F), (G), and (H), the sample CLK having four different speeds of 1 ×, 2 ×, 4 ×, and 8 × of the chip CLK is supplied to the sample CLK phase adjuster 9. Generated by The sample CLK phase adjuster 9 has a function of selecting which sample CLK to use from the plurality of generated sample CLKs according to the spreading factor. FIG. 2C shows an example of a spread code generated from the chip CLK shown in FIG.

The punctual correlator 8 correlates the spread code signal of the reference phase output from the spread code generator 7 with the received signal 10, that is, despreads the received signal 10 and demodulates data (symbol) for each symbol. Output. For example, if the spreading factor is set to 4 and sampling is performed at the chip CLK rate as in the conventional synchronous tracking circuit example, 1
Although only four samples can be averaged per symbol, the synchronous tracking circuit according to the present embodiment uses eight times the chip CLK rate shown in FIG. Averaging of 32 samples can be performed. Similarly, averaging of 16 samples per symbol can be performed by using CLK that is four times the chip CLK rate shown in FIG. 2G as the sample CLK.

For example, when the spreading factor is 4, sampling is performed with an 8 × sample CLK. When the spreading factor is 8, sampling is performed with a 4 × sample CLK. When the spreading factor is 16, the sampling is performed. By sampling at twice the sample CLK, the number of samples for one symbol becomes 32. By performing such control,
The number of samples for one symbol can be kept constant.

In the above-described embodiment, the master CLK is eight times the chip CLK. However, the present invention is not limited to this numerical example, and the above-described operation can be performed by appropriately changing the numerical value. In the case where a master CLK that is 2 N times the chip CLK is used, a clock of 2 (N−1) times can be easily generated by dividing the master CLK. The synchronization follow-up circuit can function effectively. Note that N is an integer of 2 or more.

Further, when N is an integer of 2 or more, the master CLK used in the synchronous tracking circuit according to the present embodiment is a multiple of 2 times the chip CLK, and is punctual.
Clock of correlator 8 and sample CLK of AD converter
Is the K of chip 2 when K is a positive integer.
The sample CLK is switched based on the spreading factor such that N ≧ K so as to be a multiplier. Therefore, ear
The operating clock of the ly correlator 1 and the late correlator 2 is p
Since the operation correlator 8 and the operation clock of the A / D converter are different from each other, the correlation operation in the early correlator 1 and the late correlator 2 is a correlation in a form in which the input received signal 10 is thinned out.

In the above embodiment, the clock (chip CL) for the early correlator 1 and the late correlator 2 is used.
Although the speed of K) is set as the chip speed, for example, by increasing the clock speed to twice or four times the chip speed, the following operation can be performed little by little, so that the synchronous following characteristic can be improved. Even in this case, pun
clock to sample correlator 8 (sample CL
By setting K) to be equal to or higher than the speed of the clock (chip CLK) for the early correlator 1 and the late correlator 2, it is possible to provide a digital synchronization tracking circuit with less error in the received demodulated data.

Further, a correlator operating at high speed, ie, p
Clock for uncorrelator 8 (sample C
LK) and an early correlator 1 which is another correlator.
And clock for the late correlator 2 (chip CLK)
, The increase in power consumption can be minimized, and the error characteristic of the demodulated data output from the punctual correlator 8 can be improved.

By the way, the master CLK is changed to the chip CLK.
When N is set to N times, by increasing N (4 or more), the number of samples per symbol can be sufficiently increased, and the number of averaging can be increased to improve the characteristics. Since the speed is increased, power consumption is increased. On the other hand, when N is reduced (2 or less), the number of samples cannot be increased, so that the number of averages is limited. Therefore, it is necessary to determine the value of N by comparing the power consumption and the characteristic improvement. Although the value of N also depends on the progress of semiconductor technology for reducing power consumption, 2 to 5 is appropriate for current technology.

[0031]

As described above, according to the synchronization tracking circuit according to the present invention, the operation clock for the punctual correlator is made faster than the operation clock for the early correlator and the late correlator. Demodulation with improved error characteristics is possible without complicating the situation even in a situation where the spreading factor is low and the C / N is low.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a synchronization tracking circuit according to an embodiment of the present invention.

FIG. 2 is a timing chart illustrating an operation of the synchronization tracking circuit according to the embodiment of the present invention.

FIG. 3 is a block diagram showing a conventional synchronous tracking circuit.

[Explanation of symbols]

 Reference Signs List 1 early correlator 2 late correlator 3 comparator 4 loop filter 5 CLK generator 6 chip CLK phase adjuster 7 spreading code generator 8 punctual correlator 9 sample CLK phase adjuster 10 received signal 11 demodulated data (symbol)

Claims (5)

[Claims] 1. Despreading is performed on a received spread spectrum signal at a position advanced by Δ chip phase from a reference phase,
An early correlator for outputting a correlation value for each symbol;
A late correlator for performing despreading at a position where the chip phase is delayed, and outputting a correlation value for each symbol, and performing despreading at a reference phase position for the spread spectrum signal, and calculating a correlation value for each symbol. Punct for output
a correlator, a comparator for comparing a correlation value output from the early correlator with a correlation value output from the late correlator, and control of a chip clock phase based on an output signal of the comparator. Filter, a chip clock phase adjuster for adjusting a chip clock phase based on a control signal of the loop filter, and a reference phase based on a chip clock output from the chip clock phase adjuster. A spreading code generator for generating a spreading code of a reference phase and a spreading code of a phase shifted by + Δ chip phase or −Δ phase with respect to
A sample clock phase adjuster for adjusting an operation clock for the punctual correlator based on a phase timing from the chip clock phase adjuster; and a master clock for the chip clock phase adjuster and the sample clock phase adjuster. A synchronization tracking circuit comprising: a clock generator for generating the clock signal;
A synchronization tracking circuit, wherein the synchronization tracking circuit is faster than an operation clock for the early correlator and the late correlator. 2. Despreading the received spread spectrum signal at a position advanced by Δ chip phase from the reference phase,
An early correlator for outputting a correlation value for each symbol;
A late correlator for performing despreading at a position where the chip phase is delayed, and outputting a correlation value for each symbol, and performing despreading at a reference phase position for the spread spectrum signal, and calculating a correlation value for each symbol. Punct for output
a correlator, a comparator for comparing a correlation value output from the early correlator with a correlation value output from the late correlator, and control of a chip clock phase based on an output signal of the comparator. Filter, a chip clock phase adjuster for adjusting a chip clock phase based on a control signal of the loop filter, and a reference phase based on a chip clock output from the chip clock phase adjuster. A spreading code generator for generating a spreading code of a reference phase and a spreading code of a phase shifted by + Δ chip phase or −Δ phase with respect to
A sample clock phase adjuster for adjusting an operation clock for the punctual correlator based on a phase timing from the chip clock phase adjuster; and a master clock for the chip clock phase adjuster and the sample clock phase adjuster. A synchronization tracking circuit comprising: a clock generator for generating the clock signal;
A synchronous follow-up circuit, which is the same sample clock signal as a sampling clock in an analog-to-digital converter for digitally converting a received signal. 3. Despreading the received spread spectrum signal at a position advanced by Δ chip phase from the reference phase,
An early correlator for outputting a correlation value for each symbol;
A late correlator for performing despreading at a position where the chip phase is delayed, and outputting a correlation value for each symbol, and performing despreading at a reference phase position for the spread spectrum signal, and calculating a correlation value for each symbol. Punct for output
a correlator, a comparator for comparing a correlation value output from the early correlator with a correlation value output from the late correlator, and control of a chip clock phase based on an output signal of the comparator. Filter, a chip clock phase adjuster for adjusting a chip clock phase based on a control signal of the loop filter, and a reference phase based on a chip clock output from the chip clock phase adjuster. A spreading code generator for generating a spreading code of a reference phase and a spreading code of a phase shifted by + Δ chip phase or −Δ phase with respect to
A sample clock phase adjuster for adjusting an operation clock for the punctual correlator based on a phase timing from the chip clock phase adjuster; and a master clock for the chip clock phase adjuster and the sample clock phase adjuster. A synchronization tracking circuit comprising: a clock generator for generating the clock signal;
A synchronous tracking circuit, which is the same sample clock signal as a sampling clock in an analog-to-digital converter for digitally converting a received signal, and switches the sample clock signal based on a spreading factor. 4. A master clock used in the synchronization tracking circuit is 2 times the chip clock N times when N is an integer of 2 or more, and a sample clock is a clock when K is a positive integer. N times the chip clock times 2 and N
4. The synchronous tracking circuit according to claim 3, wherein the sample clock is switched based on the spreading factor so that ≧ K. 5. The synchronization tracking circuit according to claim 4, wherein 2 ≦ N ≦ 5 in a master clock used in the synchronization tracking circuit.