JP3602397B2 - CDMA transceiver - Google Patents

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a transmission / reception apparatus in a spread spectrum communication apparatus and a CDMA (Code Division Multiple Access) communication apparatus.
[0002]
[Prior art]
2. Description of the Related Art Conventionally, spread spectrum communication and CDMA systems using spread spectrum communication technology have features such as being resistant to multipath fading, capable of increasing data speed, having good communication quality, and having high frequency use efficiency. Therefore, it is a promising communication system for next-generation mobile communication and multimedia mobile communication.
A transmission signal in the spread spectrum communication and the CDMA system is transmitted by being spread over a band much wider than the bandwidth of the signal to be transmitted on the transmission side. On the other hand, on the receiving side, the above characteristics are exhibited by restoring the spread spectrum signal to the original signal bandwidth.
[0003]
FIG. 10 shows a block diagram of a receiving section of the CDMA system. The CDMA signal received by the antenna 61 is amplified by the RF amplifying unit 62 and then converted from the radio frequency to the intermediate frequency or the baseband frequency by the frequency converting unit 63. The despreading / synchronizing unit 64, the synchronous detection and the Rake combining function Demodulated data 68 is obtained via the information demodulation unit 65 having The CDMA receiver has a configuration in which a despreading / synchronizing unit 64 is added to conventional narrowband communication.
In addition, since mobile communication operates in a multipath environment, a path search unit 66 for grasping the situation is provided, and defines a path of a received signal to be despread / synchronized and rake-combined. Further, an AFC unit 67 using the despread signal or the signal 69 after Rake combining is configured, and is fed back to the frequency conversion unit 63.
[0004]
A matched filter (MF) is one method for grasping a multipath situation and searching for a path of a received signal or a main reception path. The MF has a function of separating a plurality of signal components generated from a multipath included in a received signal. That is, since an output signal in which the direct wave and the delayed wave reaching the receiver are separated by the MF can be obtained, a desired wave can be selected and the influence of an unnecessary wave can be reduced. The details are explained in "Translation of Spread Spectrum Communication" by Jatec Publishing.
[0005]
Another method for searching and selecting a path of a received signal or a main reception path is described in Japanese Patent Application Laid-Open No. 10-173630.
[0006]
[Problems to be solved by the invention]
However, in any of the above means, a means for selecting and switching a path is provided, so that when the multipath environment changes and the main path fluctuates, as a result of path selection or path switching, the reception signal is changed. The timing of the path changes sharply.
A CDMA receiver generally receives a signal from a base station, and performs timing and AFC control in the receiver based on the received signal. Therefore, if the timing of the received signal fluctuates greatly sharply, it will have a great effect on the system timing management in the CDMA receiver.
[0007]
The present invention has been made in order to solve the above-mentioned problem, and even when a multipath environment changes and a main path changes, a reception reference is made based on a reception signal from a base station. It is an object of the present invention to provide a CDMA transmitting / receiving apparatus that can generate a timing and a transmission reference timing smoothly without sharply changing the timing.
[0008]
[Means for Solving the Problems]
The present invention has the following configuration to achieve the above object.
A first gist of the present invention is to receive a signal having a periodicity spread by a pseudo-random code, combine a plurality of delayed waves, prepare a plurality of correlators prepared for receiving, spread various data, A CDMA transmitting / receiving apparatus having a transmitting unit for performing transmission, wherein each of the plurality of correlators has a function of synchronously following a corresponding delay wave included in a received signal, and a tracking timing of each correlator. A plurality of reception timing signal generators that output a periodic reception timing signal synchronized with, and a selector that selects one main reception timing signal according to a predetermined condition from the plurality of reception timing signals, A reference timing signal generation unit for generating a transmission timing signal having a periodicity by a transmission clock signal, and a transmission timing signal and a main reception timing signal. A transmission clock controlled by the clock expansion / contraction unit, comprising: a timing determination unit for determining a phase difference; and a clock expansion / contraction unit for controlling expansion / contraction of the cycle of the transmission clock signal in accordance with the determination result of the phase difference in the timing determination unit. A CDMA transmitting / receiving apparatus is characterized in that a transmission timing signal is synchronized with a main reception timing signal by supplying a signal to a reference timing signal generation unit.
[0009]
A second gist of the present invention is a CDMA transmitting / receiving apparatus having a plurality of correlators prepared for receiving a signal having a periodicity spread by a pseudo random code and combining and receiving a plurality of delayed waves. Each of the plurality of correlators has a function of synchronously following the corresponding delay wave included in the received signal, and outputs a periodic reception timing signal synchronized with the follow-up timing of each correlator. A plurality of reception timing signal generation units, a selection unit that selects one main reception timing signal from the plurality of reception timing signals according to predetermined conditions, and a reception timing having periodicity by a supplied reception clock signal. A reference timing signal generation unit that generates a signal, a timing determination unit that determines a phase difference between the reception timing signal and the main reception timing signal, A clock expansion / contraction unit that controls expansion / contraction of the cycle of the reception clock signal in accordance with the determination result of the phase difference in the timing determination unit. To synchronize the reception timing signal with the main reception timing signal.
[0010]
A third gist of the present invention is to receive a signal having a periodicity spread by a pseudo-random code, combine a plurality of delayed waves, prepare a plurality of correlators prepared for receiving, spread various data, A CDMA transmitting / receiving apparatus having a transmitting unit for performing transmission, wherein each of the plurality of correlators has a function of synchronously following a corresponding delay wave included in a received signal, and a tracking timing of each correlator. A plurality of reception timing signal generators for outputting a periodic reception timing signal synchronized with the control signal, and a selector for selecting one main reception timing signal based on a predetermined condition from the plurality of reception timing signals. A first reference for generating either a reference reception timing signal serving as a reference for a receiving device having periodicity or a transmission timing signal based on a clock signal An imaging signal generation unit, a timing determination unit that determines a phase difference between the output signal generated by the first reference timing signal generation unit and the main reception timing signal, and a timing determination unit that determines a phase difference. A clock expansion / contraction unit that controls expansion / contraction of a cycle of a clock signal and supplies the clock signal subjected to expansion / contraction control to the first reference timing signal generation unit, and a case where the first reference timing signal generation unit generates a reference reception timing signal The transmission timing signal, the reception timing signal when the first reference timing signal generation unit is generating the transmission timing signal, and the time offset to the output signal generated by the first reference timing signal generation unit. And a second reference timing signal generation unit for generating the CDMA transmission / reception signal.
[0011]
According to a fourth aspect of the present invention, in the CDMA transmitting / receiving apparatus according to the first, second or third aspect, the reference timing signal is generated by adding an arbitrary time offset to the main reception timing signal. In the device.
[0012]
According to a fifth aspect of the present invention, in the CDMA transmitting / receiving apparatus according to the first, second, or third aspect, the clock expansion / contraction unit has a timing control unit capable of arbitrarily controlling execution timing of expansion / contraction control of a clock signal cycle. A CDMA transmitting / receiving apparatus is characterized.
[0013]
According to a sixth aspect of the present invention, in the CDMA transmitting / receiving apparatus according to the fifth aspect, the timing control section performs averaging by providing an integrating function to improve control stability. In the device.
[0014]
A seventh aspect of the present invention resides in a CDMA transmitting / receiving apparatus according to the sixth aspect, wherein the integration function is realized by an up / down counter.
[0015]
According to an eighth aspect of the present invention, in the CDMA transmitting / receiving apparatus according to the first, second, or third aspect, the selecting section that selects the main reception timing signal is a correlation unit that can obtain the maximum reception power among a plurality of correlators. A CDMA transmitting / receiving apparatus characterized by selecting a reception timing signal obtained from the apparatus.
[0016]
According to a ninth aspect of the present invention, in the CDMA transmitting / receiving apparatus according to the first, second, or third aspect, the selecting unit for selecting the main reception timing signal is a delay unit having the earliest radio wave arrival time among the plurality of correlators. A CDMA transmitting / receiving apparatus is characterized by selecting a reception timing signal obtained from a correlator for receiving a wave.
[0017]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
After the CDMA signal received by the antenna is subjected to RF amplification, filtering, and frequency conversion, baseband processing is performed. In the description of the CDMA transmitting / receiving apparatus of the present embodiment, a received signal is treated as a signal converted to a baseband. FIG. 1 is a block diagram illustrating a schematic configuration of a baseband signal processing unit according to the first embodiment of the present invention.
[0018]
The received signal is, for example, a CDMA signal having periodicity spread by an M-sequence, a Gold code, or a pseudo-random code generated by combining them with a Hadamard code. The pseudo random code is not limited as long as it can be used as a spread spectrum code.
[0019]
The baseband signal processing unit illustrated in FIG. 1 includes, for example, three correlation devices 11-a, 11-b, and 11-c and three reception timing signal generation units 12-a, 12-b, and 12-c. A main reception timing selector 13, a selection controller 14 for controlling the main reception timing selector 13, a reference clock generator 15 for generating a reference clock, and a reference timing signal generator 16 for generating a reference timing signal. And a path search unit 10.
[0020]
The path search unit 10 separates and searches a multipath component included in a received signal, and selects a path component to be demodulated. The path search unit 10 sets path information, for example, in a plurality of correlators as a path component to be demodulated. By this operation, path information to be RAKE-combined, which is a feature of CDMA, is obtained. The number of the correlators is determined by the number to be RAKE-combined, and in the present embodiment, for simplicity, the number is described as three.
[0021]
The three reception timing signals 17-a to 17-c obtained from the correlation devices 11-a to 11-c via the reception timing signal generation units 12-a to 12-c are output by the main reception timing signal selection unit 13. One reception timing signal is selected as the main reception timing signal 18 based on preset selection conditions such as maximum power, minimum reception time, and the like.
The correlation devices 11-a to 11-c are configured by a sliding correlator or a matched filter as proposed in, for example, Japanese Patent Application Laid-Open No. H11-234168 (a synchronous tracking circuit for correlation processing on spread signals). Next, FIG. 2 shows a synchronization tracking circuit included in the correlation devices 11-a to 11-c of FIG.
[0022]
FIG. 2 is a block diagram showing an example of the synchronization tracking circuit according to the present embodiment. In FIG. 2, reference numeral 1 denotes a reference phase for a received baseband signal. Ripa The early correlators 1 and 2 that output the correlation output value at the advanced position (for example, 1/2 chip) are based on the reference phase with respect to the received baseband signal. Ripa Late correlators 2 and 3 for outputting a correlation output value at a position delayed by (for example, 1/2 chip) are comparators 3 for comparing the correlation value from Early correlator 1 with the correlation value from Late correlator 2, Reference numeral 4 denotes a loop filter 4 for averaging the comparison result from the comparator 3, and reference numerals 5 and 5 refer to CLK generators 5 and 6 for generating a sample clock ("clock" may be abbreviated as "CLK"). The chip CLK phase adjusters 6 and 7 that adjust the phase of the chip CLK based on the phase control signal from the filter 4 are based on the chip CLK output from the chip CLK phase adjuster 6 with respect to the reference phase. Te A spreading code generator 7 for generating a spreading code (Early code) with an advanced phase, a spreading code (Late code) with a △ phase delay, and a symbol CLK.
[0023]
The CLK generator 5 outputs a sampling CLK having a speed four times the chip rate to the chip clock phase adjuster 6, for example. The chip clock phase adjuster 6 divides the frequency of the received sample CLK (in this example, divides by 4) to generate a chip clock 8 and outputs the chip clock 8 to the spreading code generator 7, the early correlator 1, and the late correlator 2.
I do.
[0024]
The spreading code generator 7 outputs a spreading code (Early code) with △ phase advanced to the reference phase to the Early spreader 1, and a spreading code (Late code) with △ phase delayed to the Late correlator 2. The Early correlator 1 and the Late correlator 2, which have received the chip CLK8 and the spreading code, despread the received baseband signal to obtain a correlation for each symbol and output it to the comparator 3.
[0025]
The comparator 3 compares the correlation values of the Early correlator 1 and the Late correlator 2 and outputs the comparison result to the loop filter 4.
The operation of the comparator 3 generates “Low” if the correlation value of the Early correlator 1 is larger and “High” if the correlation value is smaller, as an up-down signal as shown in FIG. 3B for each symbol.
In the present embodiment, the Early correlator 1 and the Late correlator 2 add (integrate) their correlation outputs over the symbol length for each chip CLK8, and then take the difference with the comparator 3 to obtain ( 1, 0) (FIG. 3B).
[0026]
The operation of the loop filter 4 will be described with reference to FIGS. Using the up / down counter unit 20 of FIG. 4, a binary up / down signal (FIG. 3B) generated depending on which correlation value is larger for each symbol is counted. The count value (FIG. 3C) is output.
[0027]
The phase control unit 21 instructs the chip CLK phase adjuster 6 to delay the phase when the count value becomes equal to a preset value on the Late side (“15” in the example of FIG. 3) (Late_rq = “High”). ) (FIG. 3 (E)), and thereafter, the up / down counter unit 20 is initialized (Clear = “high”) (FIG. 3 (F)).
[0028]
In FIG. 2, the chip CLK phase adjuster 6, which has received the instruction to adjust the phase from the loop filter 4, receives the instruction to advance, advances the phase of the chip CLK8 by, for example, 1/4 chip, and receives the instruction to delay it. , 1/4 chip.
The above operation is repeated to follow the synchronization.
[0029]
The reception timing signal generators 12-a to 12-c (FIG. 1) include a counter that is counted by the phase-adjusted CLK generated by the CLK phase adjuster 6 in the correlator, and the reception is performed by the counter. The reception timing signals 17-a, 17-b, and 17-c are generated by generating periodic pulses similar to the signals.
[0030]
The selection control unit 14 (FIG. 1) for selecting one main reception timing signal receives the reception timing signal 17 obtained from the correlator demodulating an arbitrary delay wave among the delay waves selected by the path search unit 10. -A to 17-c as a main reception timing signal 18.
[0031]
The main reception timing selection unit 13 is formed of, for example, a selector, and selects selection information obtained from the selection control unit 14 from among a plurality of reception timing signals 17-a to 17-c obtained from a plurality of correlation devices. The main reception timing signal 18 is selected and output.
[0032]
Next, the configuration of the reference clock generator 15 is shown in FIG.
The reference clock generation unit 15 has two blocks, namely, a timing determination unit 22 and a clock expansion / contraction unit 23.
[0033]
The timing determination section 22 compares the phases of the main reception timing signal 18 and the transmission timing signal 19. In FIG. 5, the main reception timing signal 18 corresponds to the input signal A and the transmission timing signal 19 corresponds to the input signal B.
In the timing determination 22, the phase comparison is performed only once each time the main reception timing signal 18 is input, and outputs, for example, one of the following three state determination signals (1) to (3).
(1) When the main reception timing signal and the transmission timing signal have the same phase, the "synchronization state signal"
(2) When the phase of the transmission timing signal lags behind the main reception timing signal, the "delay state signal"
(3) If the phase of the transmission timing signal is earlier than the main reception timing signal, an "early state signal"
[0034]
The function of the timing determination unit 22 performing the above operation will be described with reference to FIG.
FIG. 6A shows a master clock, which operates at four times the speed of the chip clock in this example. FIG. 6B shows an example of the main reception timing pulse signal 18, which corresponds to the input signal A in FIG. The phase relationship between the main reception timing signal 18 and the transmission timing signal 19 is one of the states (1) to (3) described above, and the respective states are shown in FIGS. 6 (C), (D), and (E). Corresponding to One of the signals shown in FIGS. 6C, 6D, and 6E corresponds to the input signal B in FIG. 5, and the output of the determination result by the timing determination unit 22 is shown in FIGS. And (H), and is input to the clock expansion / contraction unit 23.
[0035]
The clock expansion / contraction unit 23 performs the following operation in response to the three states determined by the timing determination unit 22.
(1a) In the case of the “synchronization state signal”, simple frequency division (for example, frequency division by four in this case) is performed.
(2a) In the case of the "delay state signal", for example, the convex portion (High) of the clock is reduced by a predetermined amount in the clock adjustment section, and normal frequency division is performed in other sections.
(3a) In the case of the “early state signal”, for example, a convex portion (High) of the clock is extended by a predetermined amount in the clock adjustment section, and normal frequency division is performed in other sections.
The above operation will be described with reference to FIG.
[0036]
FIG. 7A shows a master clock, which operates at four times the chip clock in this example. In order to represent a four-time clock, "0", "1", "2", "3"".
FIG. 7B shows the synchronization state of the above (1a), in which the master clock (A) is simply divided (divided by four).
FIG. 7C shows the delay state of the above (2a). In only the clock adjustment section 30, the protruding portion (High) is shortened by the master clock period 31.
Accordingly, the transmission clock 24, which is the output signal of the reference clock generation unit 15, has a clock phase earlier than that of FIG. 7C by the amount of the master clock, and operates to reduce the delay state.
FIG. 7D shows the early state of the above (3a), in which the convex portion (High) is extended by the master clock period 32 only in the clock adjustment section 30.
Therefore, the transmission clock 24, which is the output signal of the reference clock generation unit 15, has a clock phase delayed by the master clock from FIG. 7D, and operates so as to alleviate the early state.
The clock adjustment section 30 exists only once each time the timing determination section 22 performs the phase determination. When the phase adjustment is performed in the clock adjustment section 30, the result determined by the phase determination unit 22 is cleared, and a state of waiting for a new determination result is set.
The clock adjustment section 30 has a time width of about one chip or more for each cycle of the main reception timing signal 18.
[0037]
The reference timing signal generator 16 (FIG. 1) has a function of generating a periodic transmission timing signal 19 using the main reception timing signal 18 selected by the main reception timing selector 13.
The reference timing signal generator 16 is constituted by a counter synchronized with the transmission clock 24 generated by the reference clock generator 15, and starts operating when triggered by the main reception timing signal 18 (start pulse). FIG. 8 shows a block diagram of the reference timing signal generator 16.
[0038]
8 corresponds to the main reception timing signal 18, the operation clock C corresponds to the transmission clock 24 output from the reference clock generation unit 15, and the reference signal timing D output corresponds to the transmission timing signal 19. Corresponding.
When the input signal A, that is, the main reception timing signal 18, is input, the constant cycle counter 29 of FIG. 8 starts counting the operation clock C, that is, the signal of the transmission clock 24, and after counting a predetermined number, , A transmission timing signal 19 which is the reference timing D.
By using the constant period counter 29, the transmission reference timing signal 19 synchronized with the main reception timing signal 18 can be generated.
[0039]
As described in FIG. 7 (C) or (D), the clock phase is gradually increased or decreased by the master clock cycle which is the smallest in the receiver, that is, the master clock cycle usable as the fine adjustment function. It is adjusted to.
Therefore, by using the transmission timing signal 19 and the transmission clock 24 obtained from the reference clock generation unit 15 for a transmission unit (not shown), the transmission timing can always be synchronized with the main reception timing, and the main reception timing can be further reduced. Even when the switching is performed, it is possible to perform control so that a sharp timing variation does not occur in the transmission unit.
[0040]
By changing the phase of the transmission clock 24 supplied to the reference timing signal generator 16 as described above, the progress of the counter of the reference timing signal generator 16 is changed, and the output phase of the reference timing signal generator 16 is changed. Can be made.
In the first embodiment described above, the case where the transmission timing is synchronized with the main reception timing has been described. However, the case where the reception timing is synchronized with the main reception timing will be described below as a second embodiment.
[0041]
FIG. 9 is a schematic block diagram of a baseband signal processing unit according to the second embodiment of the present invention.
The baseband signal processing unit includes, for example, three correlation devices (11-a to 11-c), three reception timing signal generation units (12-a to 12-c), a main reception timing selection unit 13, It has a selection control unit 14 that controls the reception timing selection unit 13, a reference clock generation unit 15, a reference timing signal generation unit 16, and a path search unit 10. In FIG. 9, the same components as those in FIG.
[0042]
The configuration of the reference clock generation unit 15 is roughly divided into two blocks, that is, a timing determination unit 22 and a clock expansion / contraction unit 23, as shown in FIG.
The timing determination unit 22 compares the phases of the main reception timing signal 18 and the reception timing signal 43. In FIG. 5, the main reception timing signal 18 corresponds to the input signal A, and the reception timing signal 43 corresponds to the input signal B.
[0043]
The phase determination by the timing determination unit 22 is performed only once each time the main reception timing signal 18 is input. For example, (1) When the main reception timing signal and the reception timing signal have the same phase, the “synchronization state signal” (2) "Delay state signal" when the phase of the reception timing signal is behind the main reception timing signal, and (3) "Early state signal" when the phase of the reception timing signal is earlier than the main reception timing signal. Is output.
[0044]
The clock expansion / contraction unit 23 receives the three states determined by the timing determination unit 22 and performs the following operation.
(1a) In the case of the “synchronization state signal”, simple frequency division (for example, frequency division by four in this case) is performed.
(2a) In the case of the "delay state signal", for example, the convex portion (High) of the clock is reduced by a predetermined amount in the clock adjustment section, and normal frequency division is performed in other sections.
(3a) In the case of the “early state signal”, for example, a convex portion (High) of the clock is extended by a predetermined amount in the clock adjustment section, and normal frequency division is performed in other sections.
The above operation is the same as that described with reference to FIG.
[0045]
Next, the reference timing signal generator 16 (FIG. 1) has a function of generating a periodic reception timing signal 43 using the main reception timing signal 18 selected by the main reception timing selector 13.
[0046]
The reference timing signal generation unit 16 is configured by a counter synchronized with the reception clock 42 generated by the reference clock generation unit 15, and starts operation when triggered by the main reception timing signal 18.
[0047]
The reference timing signal generation unit 16 can generate the reception reference timing signal 43 synchronized with the main reception timing signal 18 by using the constant period counter 29.
By using the reception timing signal 43 and the reception clock 42 obtained from the reference clock generation unit 15 for the reception unit, an operation in which the reception timing is always synchronized with the main reception timing can be realized, and when the main reception timing is switched. However, it is possible to perform control so that a sharp timing variation does not occur in the receiving unit.
[0048]
Next, other embodiments will be described.
In a CDMA system, a signal transmitted from a base station is received by a receiver, and the signal is used to generate a reference timing signal. If the reception or transmission timing signal, that is, the second timing signal is generated using any one of the timing signals generated in FIG. 1 or FIG. 9, that is, the first timing signal, the transmission and reception timings can be synchronized. For example, when the reception timing is generated as the first reference timing, the transmission timing that is the second reference timing is generated using the first reception timing. Conversely, when the transmission timing is generated as the first reference timing, the reception timing that is the second reference timing is generated using the first transmission timing. As described above, using the received signal, synchronized reception and transmission timing can be generated.
[0049]
Further, the second reference timing can generate a more general reference timing signal by giving a time offset to the first reference timing.
[0050]
Further, in the above-described embodiment, the reference timing is generated using the main reception signal timing, but the main reception signal timing fluctuates due to a multipath condition or the like in a radio channel. Therefore, a more general reference timing can be generated even when a time offset is given to the main reception signal timing and the reference timing signal is generated using the main reception signal timing to which the time offset is given.
[0051]
In the above embodiment, when the reference timing is generated using the main reception signal timing, the timing adjustment is performed for each main reception signal timing. Was However, by controlling the timing adjustment frequency not by the main reception signal timing but by an external control signal, a highly functional reference timing signal can be generated.
In order to realize the function of controlling the timing adjustment by the external control signal, for example, a timing control unit (not shown) having a timing control function built in the clock expansion / contraction unit 23 for the reference clock shown in FIG. This can be realized by making the clock expand and contract after the control signal is gated.
With the above control, it is possible to provide a feature that the reference timing signal can be changed more smoothly. The timing control unit that realizes the above-described timing control function can generate a stable reference signal by including an integration function using an up-down counter or the like.
[0052]
Further, the selection control unit 14 (FIG. 1) that selects the main reception signal timing 18 from the main reception timing signal selection unit 13 performs the correlation control that obtains the maximum reception power among the plurality of correlation devices 11-a to 11-c. Means such as selecting timing from the apparatus or selecting timing obtained from the earliest detected wave (shortest delay wave) with the shortest reception time can be used. As a result, path switching in a multipath environment can be performed appropriately.
[0053]
【The invention's effect】
As described above, according to the present invention, in a CDMA transmitting / receiving apparatus, a stable CDMA transmitting / receiving apparatus can be generated based on a received signal from a base station, without causing a large change in the reception reference timing and the transmission reference timing. realizable.
[Brief description of the drawings]
FIG. 1 is a block diagram of a baseband signal processing unit according to a first embodiment of the present invention.
FIG. 2 is a block diagram of a correlation device according to the first embodiment of the present invention.
FIG. 3 is a timing chart illustrating an operation of the synchronization tracking circuit according to the first embodiment of the present invention.
FIG. 4 is a block diagram of a loop filter according to the first embodiment of the present invention.
FIG. 5 is a block diagram of a reference clock generator according to the first embodiment of the present invention.
FIG. 6 is a timing chart illustrating an operation of a timing determination unit according to the first embodiment of the present invention.
FIG. 7 is a timing chart for explaining the operation of the clock expansion / contraction unit according to the first embodiment of the present invention.
FIG. 8 is a block diagram of a reference timing signal generator according to the first embodiment of the present invention.
FIG. 9 is a block diagram of a baseband signal processing unit according to a second embodiment of the present invention.
FIG. 10 is a block diagram of a receiving unit of a conventional CDMA system.
[Explanation of symbols]
11-a to 11-c correlation device
12-a to 12-c reception timing generator
13 Main reception timing signal selector
15 Reference clock generator
16 Reference timing generator
17 Reception timing signal
22 Timing judgment unit
23 Clock telescopic unit

Claims (7)

CDMA transmission / reception having a plurality of correlators prepared for receiving a signal having a periodicity spread by a pseudo-random code and combining and receiving a plurality of delayed waves, and a transmission unit for spreading and transmitting various data A device,
Each of the plurality of correlators has a function of synchronously following a corresponding delay wave included in the received signal,
A plurality of reception timing signal generators that output periodic reception timing signals synchronized with the tracking timing of each correlator,
A selection unit that selects one main reception timing signal from the plurality of reception timing signals according to a predetermined condition;
A first reference timing for generating one of a reference reception timing signal serving as a reference of the reception device and a reference transmission timing signal serving as a reference of the transmission device, which is a reference timing signal having periodicity, based on the supplied clock signal; A signal generation unit;
A timing determination unit that determines a phase difference between the reference timing signal generated by the first reference timing signal generation unit and the main reception timing signal;
A clock expansion / contraction unit that controls expansion / contraction of the cycle of the clock signal in accordance with the determination result of the phase difference in the timing determination unit, and supplies the expanded / contracted controlled clock signal to the first reference timing signal generation unit;
When the first reference timing signal generation section generates a reference reception timing signal, a reference transmission timing signal is generated. When the first reference timing signal generation section generates a reference transmission timing signal, a reference reception timing signal is generated. A second reference timing signal generation section that generates a timing signal by adding a time offset to the reference timing signal generated by the first reference timing signal generation section. The CDMA transceiver according to claim 1,
A CDMA receiving apparatus, wherein an arbitrary time offset is added to the main reception timing signal for use. The CDMA transceiver according to claim 1,
The CDMA transmission / reception device, wherein the clock expansion / contraction unit has a timing control unit that can arbitrarily control execution timing of expansion / contraction control of a clock signal cycle. The CDMA transceiver according to claim 3,
The CDMA transmission / reception apparatus, wherein the timing control unit manages the execution timing of expansion / contraction control of a clock signal cycle by providing an integration function. The CDMA transceiver according to claim 4,
A CDMA transmission / reception device, wherein the integration function is realized by an up / down counter. The CDMA transceiver according to claim 1,
The CDMA transmission / reception device, wherein the selection unit that selects the main reception timing signal selects a reception timing signal obtained from a correlation device that provides a maximum reception power among the plurality of correlation devices. The CDMA transceiver according to claim 1,
The selector for selecting the main reception timing signal selects a reception timing signal obtained from a correlation device that receives a delayed wave having the earliest radio wave arrival time among the plurality of correlation devices. apparatus.

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