JP2001281164A - Method and device for inspecting pattern - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a pattern defect inspecting technology capable of realizing both an enhancement of detection sensitivity and an enhancement of inspection speed. SOLUTION: A chip comparison inspection for comparing patterns of two adjoining chips on an inspected object and a repetitive pattern comparison inspection for comparing same patterns with each other in the same pattern repetition part in a chip are carried out in parallel.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

TECHNICAL FIELD The present invention relates to a pattern inspection technology,
That is, pattern defect inspection on semiconductor wafers, photomasks, magnetic disks, optical disks, etc.
The present invention relates to a technology effective when applied to a pattern or defect inspection of an integrated circuit device having a periodic pattern and a random pattern in one chip region, such as an LSI memory and a CCD (Charge Coupled Device).

[0002]

2. Description of the Related Art Conventionally, as a pattern inspection method, a method of comparing two adjacent chips has been widely used as a visual inspection apparatus for a photomask or a wafer. Further, as a method of detecting a defect on a wafer having a complicated multilayer pattern, a method of repeatedly performing pattern comparison has been proposed as described in Japanese Patent Application Laid-Open No. 59-192943.

In the two-chip comparison inspection, in order to compare patterns of two adjacent chips, in the case of a semiconductor wafer having a multi-layer pattern, fine defects are detected due to differences in chip dimensions, pattern overlay accuracy, and the like. Is difficult. On the other hand, the method of comparing repeated patterns is to compare patterns in the immediate vicinity,
The difference between the patterns to be compared is small, and even a fine defect can be detected, but there is a problem that only a repeated pattern portion can be inspected.

In the case of a wafer pattern to be inspected, the size of a defective defect differs between a fine pattern portion and a relatively thick pattern portion, and thus the required detection sensitivity also differs.

[0005] For this reason, the present inventors disclosed in Japanese Patent Application Laid-Open No. 63-5 / 1988.
As disclosed in Japanese Patent No. 2434, a method of switching detection sensitivity according to a pattern to be inspected has been proposed.

As an inspection apparatus for performing both two-chip comparison and repeated pattern comparison, a wafer appearance inspection apparatus KLA-20 series has been proposed by KLA Corporation in the United States.
According to this apparatus, a repetitive pattern and a random pattern can be inspected separately.

[0007]

However, the technique disclosed in Japanese Patent Application Laid-Open No. 63-52434 is based on the premise of a two-chip comparison inspection, and therefore has a problem of detection sensitivity on a wafer having a multilayer pattern.

[0008] On the other hand, the device of the US KLA is an iTV.
This is for comparing images captured by (industrial television), and has one problem that the inspection speed is slow because the movement of the stage is repeatedly stopped. In addition, since the repetitive pattern area and the random pattern area are separately inspected, if there is a non-repeated pattern in a very small area in the repetitive pattern area, even if the area is very small, only that part is separated by two chips. There is the problem of having to compare.

Therefore, in the prior art described above, no consideration has been given to simultaneously improving the detection sensitivity and the inspection speed.

An object of the present invention is to provide a pattern defect inspection technique capable of simultaneously improving the detection sensitivity and the inspection speed.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0012]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

In other words, the pattern defect inspection method and apparatus of the present invention generally use a memory cell region of a memory having a fine pattern, or a CCD, a MiD (Mos Image Device).
e) Inspection of the repetitive pattern section such as the light receiving area of the optical sensor element and the peripheral circuit section with separate circuits
The repetitive pattern section allows a repetitive pattern comparison inspection with relatively high detection sensitivity to be applied, and performs inspection while continuously scanning an effective stage for high-speed inspection. Based on each inspection area data created based on the above, the defect outputs of the chip comparison and the repetitive pattern comparison are prevented from overlapping, and high-speed inspection is also possible.

According to the above-mentioned means, a portion requiring a high-sensitivity inspection, such as a memory cell in a wafer, on which a fine pattern is formed can be inspected with high sensitivity, and a relatively large area such as the periphery of a chip can be inspected. The pattern portion can be inspected with relatively low sensitivity, the defect can be detected with a detection sensitivity corresponding to the fineness of the pattern in the chip, and the above object of providing a pattern defect inspection device capable of high-speed inspection can be achieved. Things.

[0015]

FIG. 1 is an explanatory view showing an example in which a pattern defect inspection apparatus according to the present invention is applied to a wafer appearance inspection.

In this pattern defect inspection apparatus, a semiconductor wafer 3 fixed on a wafer mounting table 2 on a stage 1 composed of an XY table is sequentially moved in the X and Y directions by the stage 1, Is configured to be inspected.

The wafer 3 is irradiated with light from an illumination light source 4 located above it through a half mirror 5 and an objective lens 6, and the reflected light from the wafer 3 is enlarged by the objective lens 6 to form a one-dimensional optical element. (For example, a line sensor such as a one-dimensional CCD) 7 is condensed. An electric output of the one-dimensional optical element 7 is passed through a signal processing circuit 8 for amplifying a signal or adjusting a signal level, and is then converted to an analog-digital (AD) signal.
The converter 9 converts the signal into a multi-tone signal.

The multi-tone signal is stored in a chip delay memory 10 for storing an image signal for one chip.
A signal output from the chip delay memory 10 with a delay of one chip is compared with a signal not delayed by the comparator 12, and a thresholding circuit 13 stores a threshold value of a threshold register 18 in which a predetermined density difference threshold is set. Compared with the set value, if there is a difference in shading equal to or greater than the threshold value, it is output from the thresholding circuit 13 as a defect candidate signal.

This signal is output to the chip comparison inspection output control circuit 1
4, an output is issued only when a defect output is possible, and a defect of a certain size or more is stored in the inspection result memory 16 by the defect size determination circuit 15. The computer 23 can read data of the defect information stored in the inspection result memory 16. The above is the flow up to the defect output of the chip comparison inspection.

Next, the flow up to the defect output of the repeated pattern comparison inspection will be described. The process up to the output of the AD converter 9 in FIG. One of the outputs of the AD converter 9 is stored in a repetitive pattern delay memory 11 (or unit cell delay memory) that stores image data corresponding to the repetition pitch of the pattern. The comparator 12 'takes a difference between a signal output with a delay of one repetition of the pattern by the repetition pattern delay memory and a signal which is not delayed, and a thresholding circuit 13' sets a predetermined shading difference threshold value to a threshold value. Compared with the set value of the circuit 13 ', if there is a difference in gray level equal to or larger than the threshold value, it is output from the thresholding circuit 13' as a defect candidate signal.

This signal is output only when a defect output is possible by the repetitive pattern comparison / inspection output control circuit 14 ', and a defect of a predetermined size or more is stored in the inspection result memory 16' by the defect size determination circuit 15 '. You. The data of the defect information stored in the inspection result memory 16 ′ can be read by the computer 23.

The gray level difference threshold registers 18 and 18 'for judging the defect detection can set data independently from the computer 23, so that the chip comparison and the repetition pattern comparison can be set to different thresholds. .

Since the defect size setting registers 17 and 17 'for setting the threshold value of the defect size can set data independently from the computer 23, the defect detection sizes for chip comparison and repetitive pattern comparison can be made different. It is possible.

Reference numeral 21 denotes a line sensor position counter for calculating the number of a bit in the scanning direction of the line sensor, which is the one-dimensional optical element 7. Reference numeral 19 denotes a line for storing whether each bit of the line sensor can be inspected in the chip comparison inspection. A sensor inspection enable / disable bit memory 19 'is a line sensor inspection enable / disable bit memory for storing whether each bit of the line sensor is inspectable or not in the repeated pattern comparison. These line sensor test enable / disable bit memories 19 and 19 ′ can write data from the computer 23.

Reference numeral 22 denotes a coordinate counter in the scanning direction of the stage. Reference numerals 20 and 20 'denote an in-chip inspection feasibility area data memory for storing an inspection feasibility area in the stage scanning direction for chip comparison and repeated pattern comparison, respectively. These intra-chip test availability area data memories 20 and 20 ′ can write data from the computer 23. The outputs of the data memories 19, 19 ', 20, and 20' are sent to the inspection output control circuits 14 and 14 ', where the output of the chip comparison and the output of the repeated pattern comparison are classified.

Next, the concept of the division between the chip comparison area and the repetition pattern comparison area will be described with reference to FIGS.

FIG. 2 shows an example of a semiconductor memory chip. The regions 1 to 4 in FIG. 2 are a repetitive pattern portion, that is, a memory cell portion, and the other regions are a random pattern portion, that is, a peripheral circuit portion.

When a chip as shown in FIG. 2 is inspected by a line sensor, as shown in FIG. 3, the effective inspection width of the line sensor (W in FIG. 2) and the inside of the chip as shown in regions 1 to 8 in FIG. Divided into That is, when performing the inspection, first, only the portion of the region 1 of each chip in the wafer is subjected to the comparison inspection, and after the comparison inspection of the region 1 is completed, the comparison inspection of the regions 2 to 8 is sequentially performed.

In this case, as an example, if an image is captured at 0.25 μm / bit using a 1024-bit one-dimensional line sensor, W is about 250 μm.

As an example, FIG. 4 shows an inspection availability area for chip comparison and repetitive pattern comparison when inspecting region 1 in FIG. In FIG. 4, a hatched portion is a repeated pattern portion. In FIG. 4, the area where the chip comparison inspection is performed is CPXS1 ≦ X ≦ CPXE1, and Y is C in FIG.
Area except for the shaded area. The area where the repeated pattern comparison is performed is CLXS1 ≦ X ≦ CLXE1 or CLXS1 ≦ X ≦ CLXE1.
S2 ≦ X ≦ CLXE2 and Y is the area B in the figure.

One embodiment for realizing this area control will be described with reference to FIGS.

FIG. 5 is a diagram showing a circuit configuration for controlling the inspection enable / disable bit in the scanning direction (Y) of the line sensor. A line sensor position counter 21 that indicates the bit number of the line sensor that performs continuous scanning is stored in an inspection enable / disable bit memory 19, 1 that stores whether each bit of the line sensor is inspectable.
The address of 9 '(19 is for the chip, 19' is for the repetitive pattern) is specified, and the output (signal A, signal B in FIG. 5) of each of the bit memories 19 and 19 'is 1 or 0. It is determined whether inspection is possible.

FIG. 6 is a diagram showing a part of the inspection area data control circuit in the scanning direction of the stage.

In FIG. 6, reference numerals 22 and 22 'denote coordinate counters in the scanning direction of the stage. Since the inspection area is in units of chips, the coordinates in the chip are counted. Reversible. The reference numerals 20-1 to 20-6 and 20'-1 to 20'-6 in FIG. 6 denote in-chip testability area data memories 20, 20 'in FIG.
Is shown in detail.

Reference numerals 20-1 and 20'-1 denote counters indicating the order of the inspection area. The counter is reversible according to the stage scanning direction, and an initial value can be written from the computer 23. 20-2 is the start coordinate of the X inspection area for chip comparison,
That is, in the example of FIG. 4, it is a memory that stores CPXS1. Reference numeral 20-3 denotes a memory that stores the end coordinates of the chip comparison X inspection area, that is, CPXE1 in the example of FIG. In this example, the X inspection area is only one area, but a plurality of areas can be set to increase versatility.

The memory addresses of 20-2 and 20-3 are
The read address is specified by the counter 20-1 indicating the number of the inspection area. Reference numerals 20-4 and 20-5 denote comparators, and the coordinate counter 22 and the inspection area start coordinates (20
-2) and the inspection area end coordinates (output of 20-3) are compared. 20-6 is a flip-flop,
For example, the output of the comparator 20-4, that is, the output of the comparator 20-5 is set depending on whether or not the inspection area has been entered.
That is, the output signal C is reset depending on whether the inspection area is completed, and the output signal C is a control signal.

In FIG. 6, elements 22 ', 20'-1 to 22'-1
The structure and function of 20′-6 are the same as those of the above elements 22, 20-1 to 2
Same as 0-6, for repeated pattern comparison. 2
In the example of FIG. 4, CLXS1 and CLXS2 are stored in 0'-2. In the example shown in FIG.
XE1 and CLXE2 are stored. Flip-flop 2
The output signal D of 0'-6 is a control signal in the stage scanning direction for repeating pattern comparison.

Next, what kind of logic is applied to the signals A, B, C, and D shown in FIGS.
Whether or not 4, 14 'is realized will be described.

[0039] Then, the repetitive pattern comparison inspection output control circuit 14 '
In the case of, What is necessary is just to make it.

In the case of the chip comparison inspection output control circuit 14,

[0041]

(Equation 1) What is necessary is just to make it.

FIG. 7 shows a comparator 12 of the chip comparison / inspection circuit.
FIG. 2 is a circuit block diagram showing details of internal processing of FIG. In the figure, reference numerals 24 and 25 denote differentiators for executing digital second-order differentiation to emphasize a step portion and the like.
Is a comparator that outputs only binary signals having a value equal to or greater than a certain threshold as “1” and other signals as “0”; 91 is a differential threshold setting circuit that sets thresholds for them;
Or 33 are 4-bit shift registers, 3
Numerals 4 to 37 denote an X-direction signal delay circuit for delaying one line of the line sensor 7, and 28 operates at the same timing as the two delay circuits 34 and 35 and the shift registers 30 and 31 for timing adjustment. A timing matching circuit in which bit shift registers are connected in series, a matching detection circuit 38 or 42 outputs "1" only when two input binary signals match, and a matching detection circuit 43 or 47 counts the number of matching and outputs the data. 48 is a positioning circuit (or a timing shift circuit) for shifting the currently detected image signal based on the coincidence data so that the coincidence rate is the highest, and 49 is a counter for the current detected image signal and the chip delayed image signal. Subtractors 92 and 93 for taking the difference hold the image data until the alignment is completed. A buffer memory.

FIG. 9 is a circuit block diagram showing details of the internal processing of the comparator 12 '(FIG. 1) of the repetitive pattern comparison / inspection circuit. In the figure, reference numerals 24 'and 25' denote differentiators for performing digital second-order differentiation to emphasize a step portion and the like.
6 ′ and 27 ′ are certain thresholds of the differential signal (threshold is 2
7) A comparator which outputs only the binary signal “1” and those other than that as “0”, 91 ′
Are differential threshold setting circuits for setting thresholds for them, 2
9 'to 33' are 4-bit shift registers, 34 'to 37' are X-direction signal delay circuits for delaying one line of the line sensor 7, and 28 'is one of the 34' and 35 'for adjusting timing. A timing matching circuit in which two delay circuits and a 2-bit shift register operating at the same timing as the shift registers 30 ', 31, etc. are connected in series. A timing matching circuit 38' or 42 'is used only when two input binary signals match. A coincidence detection circuit that outputs "1", a counter 43 'or 47' counts the number of coincidences, and a counter which outputs the data. A counter 48 'converts the currently detected image signal based on the coincidence data so that the coincidence rate becomes the highest. An alignment circuit for shifting, 49 'is a subtractor for calculating the difference between the current detected image signal and the cell delay image signal, and 92' and 93 'are for alignment. This is a buffer memory for holding image data until completion.

FIG. 8 is a top view of a wafer for explaining a defect inspection of a semiconductor memory wafer. In FIG.
2 is a scribe line, 71E is a previously scanned memory chip area, 71F is a currently scanned chip area, 71G is a next scanned chip area, and 51 is a next chip area.
And 52 are a memory cell mat region formed of a repetitive pattern, 55 and 56 are peripheral circuit portions formed of a random pattern, 57 is an Al power supply main wiring band having a width of about 50 μm to 100 μm, and 61, 63 and 68 are FIG. The same scanning zone as areas 1 to 8, 61Q, 63H to 6
3K and 68Q are alignment unit areas of the respective scanning bands. The size of the alignment unit area is about 0.25 μm in pixel size and 1024 bits in the line sensor, about 256 μm in length in the Y-axis direction (extending direction of the line sensor) and about 64 μm in length in the X direction.

Next, the positioning operation will be described with reference to FIGS. Here, an Al wiring pattern will be described as an example. For example, in the case of a 4-Mbit DRAM, for example, the critical defect size is generally different between the cell portion and the peripheral portion. Therefore, the minimum defect sizes in the defect size setting registers 17 and 17 'need to be different from each other.

In addition, the size of the hillock, which is a noise for defect detection, is generally different between an Al wiring having a small cell area and a wide wiring such as the Al trunk wiring 57 in the periphery. Therefore, the previous 4 Mbit DR
In the AM example, the minimum defect size for chip comparison is 0.75μ.
m, the minimum defect size for repeated pattern comparison is set to 0.5 μm.

As described above, this apparatus performs a defect judgment in real time while continuously reading an image so as to fill a wafer with a scanning band having a width of 256 μm. In the continuous image reading and the defect determination, it is necessary to execute positioning of the reference read image and the inspection read image in real time at many points on the scan path. Therefore, for example, taking the scanning band 63 as an example, the scanning band is subdivided into unit alignment regions 63H to K and the like, and the positioning is executed for each of the regions. On the other hand, in the cell comparison, the length of the alignment unit area in the X direction is the repeat unit length or an integral multiple thereof. Otherwise, the differential threshold, threshold circuit 13 ', defect size setting register 17'
Are exactly the same except that the parameters can be set independently of the chip comparison circuit. That is, in the image data of each alignment unit area, a pattern step is emphasized by a differential operation, and a similar step emphasis pattern serving as a reference is digitally compared with the reference step. Is shifted or aligned on the memory by the alignment circuits (or timing shift circuits) 48 and 48 'as described above, and in that state, the signals are output to the differentiators or subtracters 49 and 49' and then output as differential signals. You.

As described above, image reading, chip comparison, cell comparison, and their determination are always executed in parallel, and the comparison specification to be output is selected according to the inspection area. However, accurate positioning can be achieved.

Further, since various parameters in a plurality of inspection circuits can be set independently, a high-speed inspection of a complicated pattern such as a semiconductor memory having different defect parameters in each region can be performed.

Although the invention made by the present inventor has been described based on the embodiments, the present invention is not limited to the above-described embodiments, and may be variously modified without departing from the gist thereof. Needless to say.

For example, in the above embodiment, the output of each comparative inspection is controlled by hardware, but the detected defect is divided into a repetitive pattern section and a random pattern section based on the coordinates in the chip. The defect data is processed by software so as not to overlap. Alternatively, the threshold value of the defect size can be determined by software using the coordinates.

Further, when the inspection conditions for the two-chip comparison and the inspection conditions for the repeated pattern comparison are different, the computer 23
It is also possible to discriminate which of the comparison circuits is the output from the software processing in the above, and add this discrimination result data to the inspection result data. As a result, it is possible to determine that the inspection results are different from each other under inspection conditions. In the case where the processing is performed at the same time, the processing can be performed separately.

The above invention has been described with respect to the case where the invention made by the present inventor is applied to a wafer appearance inspection apparatus which is a field of application as a background, but the invention is not limited to this. For example, a photomask, The present invention can also be applied to a visual inspection device such as a liquid crystal and a disk. Further, the present invention can also be applied to a foreign substance inspection apparatus for performing a comparative inspection.

[0054]

Advantageous effects obtained by typical ones of the inventions disclosed in the present application will be briefly described.
It is as follows.

That is, in the appearance inspection of a wafer or the like, the detection sensitivity can be appropriately set according to the position in the chip.
In addition to optimizing the defect detection sensitivity, the chip comparison and the repetitive pattern comparison can be performed simultaneously, so that the speed of the test can be increased. In other words, according to the present invention, it is possible to improve the detection sensitivity and the inspection speed in the pattern defect inspection.

[Brief description of the drawings]

FIG. 1 is an explanatory diagram showing an embodiment in which the present invention is applied to a wafer appearance inspection.

FIG. 2 is a diagram illustrating an example of a chip.

FIG. 3 is an explanatory diagram for dividing a chip into scan width units of a line sensor.

FIG. 4 is an explanatory diagram showing one region of FIG. 3 and showing regions for each comparative inspection.

FIG. 5 is an example of a circuit configuration for controlling an inspection enable / disable bit in a scanning direction of a line sensor.

FIG. 6 is a circuit configuration diagram for controlling an inspection area in a stage scanning direction.

FIG. 7 is a circuit block diagram showing details of internal processing of a comparator (chip comparison side).

FIG. 8 is a top view of a wafer showing a layout of an upper main surface of a semiconductor memory device wafer to be inspected;

FIG. 9 is a circuit block diagram showing details of internal processing of a comparator (repeated pattern comparison or cell comparison side).

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Stage, 2 ... Wafer mounting table, 3 ... Wafer, 4 ... Illumination light source, 5 ... Half mirror, 6
..Objective lens, 7: one-dimensional optical element (line sensor), 8: signal processing circuit, 9: AD converter, 1
0: Chip delay memory, 11: Repetitive pattern delay memory, 12, 12 '... Comparator, 13, 13'
... Thresholding circuit, 14 ... Chip comparison inspection output control circuit, 14 '... Repeated pattern comparison inspection output control circuit, 15 ... Chip comparison defect size determination circuit, 15'
... Repeated pattern comparison defect size determination circuit
..Chip comparison inspection result memory, 16 ': repeated pattern comparison inspection result memory, 17: chip comparison defect size setting register, 17': repeated pattern comparison defect size setting register, 18: chip comparison Shading difference threshold register, 18 '... Repeated pattern comparison shading difference threshold register, 19 ... Chip comparison line sensor test enable / disable bit memory, 19' ... Repeat pattern compare line sensor test enable / disable bit memory, 20 ... In-chip test enable / disable area data memory for chip comparison, 20 '
• In-chip inspection availability area data memory for repeated pattern comparison, 20-1 ... Inspection area counter for chip comparison, 20'-1 ... Inspection area counter for repeated pattern comparison, 20-2 ... Chip comparison X inspection area start coordinates for use, 20'-2 ... X inspection area start coordinates for use in repeated pattern comparison, 20-3 ... X test area end coordinates for use in chip comparison, 20'-3 ... use for repeat pattern comparison X inspection area end coordinates, 20-4... Coordinate comparator, 20'-4.
..Coordinate comparison, 20-5 ... Coordinate comparator, 20'-5
... Coordinate comparator, 20-6 ... Flip-flop,
20'-6: flip-flop, 21: line sensor position counter, 22, 22 ': stage scanning direction coordinate counter, 23: computer, 24, 24',
25, 25 '... differentiator, 26, 26' 27, 27 '
... Comparator, 28, 28 '... Timing matching circuit,
29, 29 'to 33, 33': shift register, 3
4, 34 'to 37, 37' ... X-direction signal delay circuit,
38, 38 'to 42, 42' ... match detection circuit, 4
3, 43 'to 47, 47' ... counters, 48, 4
8 ': Positioning circuit (timing shift circuit),
49, 49 '... Subtracters (differentiators) 51, 52.
Memory cell mat area, 55, 56... Peripheral circuit section, 57... Al main wiring, 61, 63, 68... Scanning band, 61Q, 63H, 63I, 63J, 6
3K, 68Q: alignment unit area, 71E:
Memory chip area, 71F, 71G ... chip area,
72 scribe line, 91, 91 '... differential threshold value setting circuit, 92, 92', 93, 93 '... buffer memory.

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Mikito Saito 5-2-1, Josuihoncho, Kodaira-shi, Tokyo Inside the Musashi Plant of Hitachi, Ltd. (72) Inventor Yoshikazu Hori 3-chome Fujibashi, Ome-shi, Tokyo 3-2-2 Hitachi Tokyo Electronics Co., Ltd. (72) Inventor Takahiro Kamagata 3-3-1 Fujibashi, Ome-shi, Tokyo 3-2-2 Hitachi Hitachi Electronics Co., Ltd.

Claims (12)

[Claims] 1. A chip comparison test for comparing patterns of two adjacent chips on a device under test and a repetitive pattern comparison test for comparing the same patterns of the same repetitive pattern portion in a chip in parallel. A pattern inspection method characterized by the following. 2. The output of the chip comparison inspection and the repetition pattern comparison inspection are separately taken into a computer, and the computer compares the inspection result obtained by the two comparison inspections with a predetermined inspection condition; 2. The pattern inspection method according to claim 1, wherein only inspection results exceeding the preset inspection conditions are left as inspection results. 3. A semiconductor device comprising: a first comparison circuit for comparing patterns of two adjacent chips on a device under test; and a second comparison circuit for comparing the same patterns of the same repetitive pattern portion in the chip. A pattern inspection apparatus characterized in that both comparison circuits can operate in parallel. 4. The random pattern section in the chip is controlled to output a defect by the first comparison circuit, and the repetitive pattern section is controlled to output a defect of the second comparison circuit. The pattern inspection apparatus according to claim 1. 5. The pattern inspection apparatus according to claim 3, further comprising a one-dimensional optical line sensor, wherein a defect is detected while continuously scanning the stage. 6. Based on pattern arrangement information in a chip,
For each of the scanning direction of the one-dimensional sensor and the stage scanning direction from the starting point of the chip, it has a storage unit for storing data of the chip comparison inspection area and the repetitive pattern comparison inspection area, and is synchronized with the sensor scanning position and the stage scanning position. And 2
4. The pattern inspection apparatus according to claim 3, wherein whether or not a defect output of the chip comparison inspection or a defect output of the repeated pattern comparison inspection can be output is controlled. 7. Based on pattern arrangement information in a chip,
For each of the scanning direction of the one-dimensional sensor and the stage scanning direction from the starting point of the chip, it has a storage unit for storing data of the chip comparison inspection area and the repetitive pattern comparison inspection area, and is synchronized with the sensor scanning position and the stage scanning position. And 2
5. The pattern inspection apparatus according to claim 4, wherein whether or not a defect output in the chip comparison inspection or a defect output in the repeated pattern comparison inspection is output is controlled. 8. Based on pattern arrangement information in a chip,
For each of the scanning direction of the one-dimensional sensor and the stage scanning direction from the starting point of the chip, it has a storage unit for storing data of the chip comparison inspection area and the repetitive pattern comparison inspection area, and is synchronized with the sensor scanning position and the stage scanning position. And 2
6. The pattern inspection apparatus according to claim 5, wherein whether or not a defect output of the chip comparison inspection or a defect output of the repeated pattern comparison inspection can be output is controlled. 9. The pattern inspection apparatus according to claim 5, wherein a defect determination condition for two-chip comparison and a defect determination condition for repeated pattern comparison can be set independently. 10. The pattern inspection apparatus according to claim 3, wherein the detected defect is displayed or output by distinguishing between a defect in the two-chip comparison inspection and a defect in the repeated pattern comparison inspection. . 11. The pattern inspection apparatus according to claim 4, wherein the detected defect is displayed or output while distinguishing between a defect in the two-chip comparison inspection and a defect in the repeated pattern comparison inspection. . 12. The pattern inspection apparatus according to claim 5, wherein the detected defect is displayed or output by distinguishing between a defect in the two-chip comparison inspection and a defect in the repeated pattern comparison inspection. .