JP2001274367A - Non-volatile semiconductor memory device and producing method therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a highly reliable non-volatile semiconductor memory device capable of improving the inversion pressure resistance of a field transistor and the pressure resistance of an insulating film between a floating gate and a control gate, by protecting an element isolation region or producing method for non-volatile semiconductor memory device capable of improving throughput by protecting element isolation without using a lithography process. SOLUTION: After an element isolation region 21 is formed, an insulating film 28 such as silicon-nitride film and a silicon-oxide film 43 are formed all over the surface and the silicon-oxide film 43 is ground while using the insulating film 28 resistant to hydrofluoric acid as a stopper. Continuously, the insulating film 28 resistant to hydrofluoric acid on a polycrystal silicon film 30 is removed. Next, by removing the silicon-oxide film 43 on the insulating film 28 resistant to hydrofluoric acid by wet etching, the insulating film 28 is formed by self-aligning all over the upper surface of the element insulation region 21.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile semiconductor memory device and a method of manufacturing the same, and more particularly, to a method using a MOS transistor having a two-layer gate structure as a memory cell transistor.

[0002]

2. Description of the Related Art Due to recent improvements in semiconductor device manufacturing techniques, miniaturization of semiconductor memory devices in particular has been rapidly progressing. Accordingly, research on element isolation technology for electrically isolating individual elements has been actively pursued.

A conventional nonvolatile semiconductor memory device will be described with reference to FIG. FIG. 28 shows a NOR flash EEPROM (Electrically Erasable and Programmab).
FIG. 2 is a partial cross-sectional view along a word line direction in a memory cell array region of the “le Read Only Memory”.

As shown in the figure, an element isolation region 110 is formed on a silicon substrate 100, and a gate insulating film 13 is formed on an active region 120 between the adjacent element isolation regions 110.
0 is formed. Further, the floating gate 140 is formed on the gate insulating film 130. Further, a floating gate / control gate insulating film 150 is formed on the entire surface, and a control gate 160 is formed on the floating gate / control gate insulating film 150 so as to overlap with the floating gate 140. Although not shown, a memory cell transistor is formed by selectively forming an impurity diffusion layer in the silicon substrate 100 (not shown).

[0005] NOR type flash EEPROM having the above structure
In M, data is stored by injecting charges into the floating gate 160 of the memory cell transistor. This charge is injected by generating hot carriers in the channel region of the memory cell transistor and injecting them into the floating gate 160, or by applying a high electric field to the gate insulating film 130 between the floating gate 160 and the silicon substrate 100,
This is performed by a method of injecting charges by a tunnel effect.

In either method, the control gate 16
A high electric field must be applied to 0. In order to perform stable element isolation in this state, it is necessary to sufficiently secure the inversion withstand voltage of the field transistor formed by the MOS structure of the control gate 160, the floating gate / control gate insulating film 150, and the semiconductor substrate 100. In particular, with the progress of miniaturization of semiconductor devices in recent years, there has been a demand for making the depth of the element isolation region 110 shallower. Therefore, securing this inversion withstand voltage has become an increasingly important technique.

At the time of writing and erasing data,
In the insulating film 150 between the floating gate and the control gate, 5 MV /
A high electric field of about cm is applied. Therefore, it is also required to increase the breakdown voltage of the insulating film 150 between the floating gate and the control gate.

The floating gate 140 is generally formed of a polycrystalline silicon film. The withstand voltage of the insulating film 150 between the floating gate and the control gate is greatly affected by the cleanliness of the polycrystalline silicon film which is the underlying floating gate 140. Therefore, in the conventional method of manufacturing a NOR flash EEPROM, the insulating film 150 between the floating gate and the control gate is not used.
In order to improve the breakdown voltage of the polysilicon film, the polycrystalline silicon film is cleaned, and this cleaning treatment is a processing solution having an effect of removing a natural oxide film (for example, HF, diluted HF, NH ₄ F, or diluted NH ₄ F). This is performed using

However, when such a cleaning process is performed, there is a problem that the silicon oxide film forming the element isolation region 110 is etched. Figure 2 on this issue
9 will be described. FIG. 29 shows a NOR type flash EE
FIG. 3 is a cross-sectional view of the PROM along a word line direction. As shown in the figure, it can be seen that a part of the element isolation region 110 is eroded and thinned. As a result, the inversion withstand voltage of the field transistor decreases and the floating gate 140
In addition, in addition to the upper end 170 of the floating gate, the lower end 180
Since the corners are also formed, there is a problem that the concentration of the electric field is increased and the withstand voltage of the insulating film 150 between the floating gate and the control gate is also deteriorated.

To avoid the above problem, a structure shown in FIG. 30 has been proposed. FIG. 30 shows a NOR flash E
FIG. 3 is a cross-sectional view of the EPROM along a word line direction. As shown, a hydrofluoric acid-resistant insulating film (silicon nitride film or the like) 190 is provided on the element isolation region 110. for that reason,
In the cleaning process of the floating gate 140, the element isolation region 1
10 can be protected by the hydrofluoric acid resistant insulating film.

However, in order to form the above structure, a lithography step for leaving the hydrofluoric acid-resistant insulating film 190 only on the element isolation region 110 is required. Therefore, there is a problem that the throughput of the product is reduced. Furthermore,
As shown in FIG. 31, in the lithography step,
If the hydrofluoric acid-resistant insulating film 190 is displaced from the isolation region of the floating gate 140 due to misalignment of the hydrofluoric acid-resistant insulating film 190, the element isolation region 1 is also subjected to a subsequent cleaning process.
There was a problem that 10 was eroded. In particular, when the width of the element isolation region 110 becomes narrower as the miniaturization progresses, the amount of misalignment allowed in the lithography step becomes stricter, which is not practical in an actual semiconductor memory device manufacturing process.

[0012]

SUMMARY OF THE INVENTION The conventional semiconductor memory device and the method of manufacturing the same described above are intended to improve the breakdown voltage of the insulating film between the floating gate and the control gate. The floating gate was cleaned. However, since this cleaning step is performed with a hydrofluoric acid-based treatment liquid having an oxide film removing effect, the element isolation region below the isolation region of the floating gate may be eroded. Therefore, there is a problem that the inversion withstand voltage of the field transistor decreases, the electric field concentration portion increases in the floating gate, and the withstand voltage of the insulating film between the floating gate and the control gate also deteriorates.

Further, the method of providing a hydrofluoric acid-resistant insulating film on an element isolation region proposed to solve the above-mentioned problem requires a lithography step for processing the hydrofluoric acid-resistant insulating film. There is a problem that the throughput of the storage device is reduced. Furthermore, as the miniaturization progresses, the amount of misalignment allowed in the lithography process decreases,
If the hydrofluoric acid-resistant insulating film comes off the isolation region of the floating gate, there is also a problem that the element isolation region is eroded in the subsequent cleaning process.

The present invention has been made in view of the above circumstances, and a first object of the present invention is to protect the element isolation region to reduce the inversion breakdown voltage of a field transistor and the breakdown voltage of a floating gate-control gate insulating film. An object of the present invention is to provide a highly reliable nonvolatile semiconductor memory device which can be improved.

A second object of the present invention is to provide a method of manufacturing a nonvolatile semiconductor memory device which can improve throughput by protecting element isolation without using a lithography step.

[0016]

According to a first aspect of the present invention, there is provided a nonvolatile semiconductor memory device comprising: an element isolation region provided on a semiconductor substrate; and a fluorine-resistant device provided over the entire upper surface of the element isolation region. An acidic insulating film, a first gate insulating film provided on an active region between the adjacent element isolation regions,
A first gate electrode including a first conductive film provided on the first gate insulating film and a second conductive film provided on the first conductive film, and the first gate electrode A second gate insulating film provided on the second gate insulating film, a second gate electrode provided on the second gate insulating film and at least partially overlapping the first gate electrode, A gate insulating film, the first gate electrode, the second gate insulating film, and an interlayer insulating film covering a laminated gate structure formed by laminating the second gate electrode; The upper surface of the region is lower than the upper surface of the first conductive film.

According to a second aspect of the present invention, there is provided a method of manufacturing a nonvolatile semiconductor memory device, comprising: forming a first gate insulating film on a semiconductor substrate; and forming a first gate insulating film on the first gate insulating film. Forming a first conductive film constituting a part of a gate electrode; etching the first conductive film, the first gate insulating film and the semiconductor substrate to form a trench; Forming an element isolation region by embedding an insulating film, forming a hydrofluoric acid-resistant insulating film over the entire upper surface of the element isolation region in a self-aligned manner with respect to the element isolation region; Forming a second conductive film on the conductive film and the hydrofluoric acid-resistant insulating film;
Removing at least a portion of the second conductive film on the hydrofluoric acid-resistant insulating film until it reaches the hydrofluoric acid-resistant insulating film to form a first gate electrode; Forming a second gate insulating film on the second gate insulating film; forming a second gate electrode on the second gate insulating film at least partially overlapping the first gate electrode; Forming an interlayer insulating film so as to cover a stacked gate structure formed by stacking one gate insulating film, the first gate electrode, the second gate insulating film, and the second gate electrode; Are provided.

According to a third aspect of the present invention, in the method for manufacturing a nonvolatile semiconductor memory device according to the second aspect,
The step of forming a hydrofluoric acid-resistant insulating film on the entire upper surface of the element isolation region in a self-aligned manner with respect to the element isolation region includes lowering the surface of the element isolation region at least below the surface of the first conductive film. Etching, forming the hydrofluoric acid-resistant insulating film on the element isolation region and the first conductive film, and forming a first mask material on the hydrofluoric acid-resistant insulating film. Removing the first mask material using the hydrofluoric acid-resistant insulating film on the first conductive film as a stopper, and removing the hydrofluoric acid-resistant insulating film on the first conductive film And removing the first mask material on the hydrofluoric acid-resistant insulating film.

Further, as described in claim 4, in the method for manufacturing a nonvolatile semiconductor memory device according to claim 2,
The step of forming a hydrofluoric acid-resistant insulating film on the entire upper surface of the element isolation region in a self-aligned manner with respect to the element isolation region includes lowering the surface of the element isolation region at least below the surface of the first conductive film. Etching, forming the hydrofluoric acid-resistant insulating film on the element isolation region and the first conductive film, and forming a first mask material on the hydrofluoric acid-resistant insulating film. A step of removing the first mask material using the first conductive film as a stopper, and a step of removing the first mask material on the hydrofluoric acid-resistant insulating film. And

According to a fifth aspect of the present invention, in the method of manufacturing a nonvolatile semiconductor memory device according to any one of the second to fourth aspects, before the step of forming the second conductive film,
The method further comprises a step of cleaning the surface of the first conductive film with a treatment solution containing hydrofluoric acid.

According to a sixth aspect of the present invention, in the method for manufacturing a nonvolatile semiconductor memory device according to any one of the second to fifth aspects, the step of forming the second gate insulating film is performed before the step of forming the second gate insulating film. The method further comprises a step of cleaning the surface of the second conductive film with a treatment solution containing hydrofluoric acid.

According to a seventh aspect of the present invention, in the method of manufacturing a nonvolatile semiconductor memory device according to any one of the second to sixth aspects, at least a part of the second conductive film on the hydrofluoric acid-resistant insulating film. Forming a first gate electrode by removing the film until the film reaches over the hydrofluoric acid-resistant insulating film;
Forming a second mask material on the conductive film, forming the second mask material by lithography and etching, and forming a third mask material on the second mask material and the second conductive film. Forming the mask material, etching the third mask material and leaving it only on the side walls of the second mask material, and forming the second mask material using the second and third mask materials. Etching the conductive film to remove at least a part of the second conductive film on the hydrofluoric acid-resistant insulating film until reaching the hydrofluoric acid-resistant insulating film; and using a processing solution containing hydrofluoric acid. Removing the second and third mask materials and cleaning the surface of the second conductive film.

According to the first and second aspects of the present invention, the hydrofluoric acid-resistant insulating film is formed on the entire upper surface of the element isolation region. Since the hydrofluoric acid-resistant insulating film functions as a protective film for the element isolation region, it is possible to prevent the element isolation region from being etched in a subsequent cleaning step using a hydrofluoric acid-based treatment solution. Therefore, the element isolation region can maintain a high inversion breakdown voltage with respect to the field transistor. In addition, since the element isolation region is not etched, no extra corners are generated in the first gate electrode, it is possible to avoid an increase in the number of electric field concentration areas as in the related art, and maintain the breakdown voltage of the second gate insulating film. . Further, since the element isolation region is protected by the hydrofluoric acid-resistant insulating film, the surfaces of the first conductive film and the second conductive film can be sufficiently cleaned with a hydrofluoric acid-based treatment solution, so that the second gate The withstand voltage of the insulating film can be further improved. In addition, since the formation of the hydrofluoric acid-resistant insulating film can be performed by self-alignment, in the step of removing at least a part of the second conductive film on the hydrofluoric acid-resistant insulating film to form the first gate electrode, Can be increased, so that the throughput can be improved.

According to the method of the third or fourth aspect, the hydrofluoric acid-resistant insulating film can be formed in a self-aligned manner with respect to the element isolation region.

As described in claim 5 or 6, by cleaning the surfaces of the first conductive film and the second conductive film with a hydrofluoric acid-based treatment liquid, the withstand voltage of the second insulating film can be improved.

According to a seventh aspect of the present invention, a third mask material is formed on the second mask material patterned by lithography and etching, and the third mask material is formed by anisotropic etching.
By leaving the mask material only on the side wall of the second mask material, a mask pattern finer than the processing limit of the lithography technique can be formed. In addition, by using a hydrofluoric acid treatment solution for removing the mask material, the surface of the second conductive film can be washed at the same time.

[0027]

Embodiments of the present invention will be described below with reference to the drawings. For this explanation,
Common parts are denoted by common reference symbols.

A nonvolatile semiconductor memory device and a method of manufacturing the same according to the first embodiment of the present invention will be described by taking a NOR flash EEPROM as an example.

FIG. 1 is a circuit diagram of a NOR flash EEPROM. As shown, the memory cell array 10
Has multiple non-volatile memory cells (MC)
Are arranged in a matrix. Each nonvolatile memory cell MC has one bit line (BL: Bit Line) and one
Connected to two source lines (SL: Source Line). The gates of the plurality of nonvolatile memory cells MC are connected to different word lines (WL: Word Line) for each row, and the word lines WL1 to WL8 are connected to the row decoder 11, respectively. The row decoder 11 selectively drives any one of the plurality of word lines WL1 to WL8.

The bit lines BL1 to BL4 are connected to a column selector 12. The column selector 12 includes a plurality of transistors 13-1 to 13-4 having one ends of current paths connected to the bit lines BL1 to BL4, respectively. Have. The gates of the transistors 13-1 to 13-4 are respectively connected to different column selection lines (CSL: Column Sel).
ect Line) and this column selection line CSL
1 to CSL4 are connected to the column decoder 14, respectively. The column decoder 14 has a plurality of column selection lines CS
One of L1 to CSL4 is selectively driven. By selectively driving any one of the transistors 13-1 to 13-4, a plurality of bit lines BL1 to BL4
Is electrically connected to the read / write node 15. This read / write node 15
Are respectively connected to a read circuit and a write circuit (not shown). As a result, data reading / writing is performed on the nonvolatile memory cell MC selected by the column decoder 14 and the row decoder 11.

The nonvolatile memory cell MC is connected to a source line SL provided along the direction in which the word line WL extends. This source line SL is a global source line (G) provided along the direction in which the bit line BL extends.
SL: Global Source Line (SL), and the global source line GSL is connected to the source decoder 16.
The source decoder 16 supplies the source potential of the nonvolatile memory cell MC via the source line SL via the global source line GSL.

FIG. 2 is a plan view of a region 17 surrounded by a chain line in FIG. As shown in the figure, a silicon substrate 20 has an element isolation region (STI: Shallow Trench Isola).
An active area (AA) 22 for forming an element is formed between the element isolation regions 21.
It has become. The active region 22 has a floating gate (FG: Fl
An operating gate (CG) 24 is selectively provided, and a control gate (CG: Control Gate) 23 extends so as to cover the floating gate 24 and to be orthogonal to the active region 22.
In the silicon substrate 20 of each active region 22, the source and the source are sandwiched so as to sandwich the floating gate 24 and the control gate 23.
The memory cell transistor MC is formed by providing the impurity diffusion layers to be the drain regions S and D. Further, a contact hole 25 is provided in the drain D of the nonvolatile memory cell MC.
5 is connected to the bit line 26. The source S of the nonvolatile memory cell MC is different from the source S of the nonvolatile memory cell MC adjacent via the element isolation region 21.
For example, they are commonly connected by an impurity diffusion layer (source line SL) provided at the bottom of the element isolation region 21.

Next, FIGS. 3 (a) and 3 (b) show the AA 'line and BB' of the region 27 surrounded by the dashed line in FIG.
The cross-sectional views along the line direction are respectively shown. As shown, an element isolation region (STI) 21 is formed in a semiconductor substrate 20, and a hydrofluoric acid-resistant insulating film 28 is formed on the entire surface so as to cover the upper surface of the element isolation region 21. Then, a gate insulating film 29 (first gate insulating film) is formed on the active region 22 between the adjacent element isolation regions 21,
On this gate insulating film 29, a floating gate 24 (first gate electrode) composed of a polycrystalline silicon film 30 (first conductive film) and 31 (second conductive film), a floating gate-control gate insulating film 32 (second gate insulating film) and a control gate 23 (second gate electrode) are formed. Further, a memory cell transistor is formed by selectively forming an impurity diffusion layer 33 serving as a source or drain region in the semiconductor substrate 10. A silicon nitride film 34 is formed on the entire surface so as to cover the stacked gate structure including the gate insulating film 29, the floating gate 24, the floating gate / control gate insulating film 32, and the control gate 23. On the silicon nitride film 34, an interlayer insulating film 35 for protecting the memory cell transistor is formed, and on the interlayer insulating film 35, a silicon oxide film 36 is formed. In the silicon oxide film 36, a bit line 26 composed of a titanium film 37 and a tungsten film 38 is formed, and a contact plug 39 connected to the bit line 26 is formed so as to connect to the drain region of the memory cell transistor. Being done, NOR type flash E
An EPROM is formed.

The NOR flash EEPROM having the above configuration
FIGS. 4 (a), (b) to 19 show a method of manufacturing M.
This will be described with reference to (a) and (b). FIG. 4 (a), (b)
19 (a) and 19 (b) correspond to FIGS. 3 (a) and 3 (b). In FIG. 2, FIG.
(B) is a cross-sectional view of a manufacturing process of the NOR flash EEPROM along the line BB 'in order.

First, as shown in FIGS. 4A and 4B, a silicon oxide film serving as a gate insulating film 29 (first gate insulating film) is formed on a silicon substrate 20 by a thermal oxidation method or the like.
On the gate insulating film 29, a polycrystalline silicon film 30 (first conductive film) to which phosphorus is added as a lower layer electrode of the floating gate is formed on the gate insulating film 29 by low pressure CVD (Chemical Vapor Deposition).
Deposition) to form a film having a thickness of 800 °.
The gate insulating film 29 may be a silicon oxide film, or may be an oxynitride film by performing nitridation and oxidation using NH ₃ gas or the like. Subsequently, a silicon nitride film 40 is formed on the polycrystalline silicon film 30 by low pressure CVD.
It is formed to a thickness of 1500 ° by a method or the like.

Next, as shown in FIGS. 5A and 5B,
The silicon nitride film 40, the polycrystalline silicon film 30, and the gate insulating film 29 in the region where the element isolation region is to be formed are sequentially etched by lithography and anisotropic etching such as RIE (Reactive Ion Etching). 20 is etched to a depth of 4000 ° to form a trench 41 for forming an element isolation region.

Then, as shown in FIGS. 6A and 6B, a silicon oxide film 42 (insulating film) is
H using (tetraethylorthosilicate; Si (OC ₂ H ₅ ) ₄ )
The trench 41 is buried by forming it to a film thickness of 8000 ° by a DP (High Density Plasma) method or the like. Before the trench 41 is filled with the silicon oxide film 42, a heat treatment is performed in an oxidizing atmosphere, so that the surface of the silicon substrate 20 exposed on the surface of the trench 41 is
A silicon oxide film may be formed. This silicon oxide film is for preventing the concentration of stress and the like on the corner by making the shape of the corner between the side wall and the bottom of the trench 41 gentle.

Next, as shown in FIGS. 7A and 7B, the silicon oxide film 42 is polished and flattened by a CMP method using the silicon nitride film 40 as a stopper to complete the element isolation region 21. .

Then, as shown in FIGS. 8A and 8B, the silicon nitride film 40 is selectively removed by hot phosphoric acid treatment, and the silicon oxide film 42 is removed from the surface of the polycrystalline silicon film 30 by 200-200. HF until 400Å
Is performed by wet etching.

Thereafter, as shown in FIGS. 9A and 9B, a hydrofluoric acid-resistant insulating film 28 such as a silicon nitride film and a silicon oxide film 43 (first mask material) using TEOS are subjected to CVD.
It is formed to a thickness of 200 ° and 1000 °, respectively, by the method.

The silicon oxide film 43 is polished by a CMP method using the fluoric acid-resistant insulating film 28 as a stopper, and as shown in FIGS.
To expose.

Further, as shown in FIGS. 11A and 11B, the hydrofluoric acid-resistant insulating film 28 on the polycrystalline silicon film 30 is removed by performing hot phosphoric acid treatment. On this occasion,
The hydrofluoric acid-resistant insulating film 28 on the element isolation region 21 is not etched because it is protected by the silicon oxide film 43.

Next, by removing the silicon oxide film 43 on the hydrofluoric acid-resistant insulating film 28 by wet etching, as shown in FIGS. The acidic insulating film 28 can be formed by self-alignment. Thereafter, the polycrystalline silicon film 30 is subjected to a cleaning treatment with a hydrofluoric acid-based treatment liquid to remove the natural oxide film. At this time, the element isolation region 21 is protected by the hydrofluoric acid-resistant insulating film 28.

Thereafter, as shown in FIGS. 13A and 13B, a polycrystalline silicon film 31 (second conductive film) to which phosphorus is added as an upper layer electrode of the floating gate is entirely formed by a low pressure CVD method or the like. Form.

Then, the polycrystalline silicon film 31 is formed by lithography and anisotropic etching as shown in FIG.
As shown in (b), the floating gate 24 (first gate electrode) is formed by patterning in the extending direction of the bit line BL. Then, a hydrofluoric acid-based cleaning process is performed to remove the natural oxide film on the surface of the polycrystalline silicon film 31 in the upper layer portion of the floating gate 24. Also at this time, the element isolation region 21 can be protected by the hydrofluoric acid-resistant insulating film 28. Subsequently, a floating gate / control gate insulating film 32 (second gate insulating film) is formed on the entire surface. The insulating film 32 between the floating gate and the control gate is, for example, a silicon oxide film (SiO ₂ : 5 nm),
This is an ONO film having a three-layer structure of a silicon nitride film (SiN: 7 nm) and a silicon oxide film (SiO ₂ : 5 nm).
The insulating film 32 between the floating gate and the control gate may be simply a silicon oxide film, or may be an ON film or a NO film having a two-layer structure of a silicon oxide film and a silicon nitride film.

Subsequently, as shown in FIGS. 15A and 15B, a control gate 23 (second gate electrode) is formed on the insulating film 32 between the floating gate and the control gate. The control gate 23 has, for example, a polycrystalline silicon film to which an impurity is added, or a multilayer structure (polycide) of this polycrystalline silicon film and a silicide film.

Then, the control gate 23, the floating gate / control gate insulating film 32 and the floating gate 24 are again formed by lithography and anisotropic etching as shown in FIG.
Patterning is performed in the word line direction as shown in FIGS.

Next, impurities are introduced into the regions serving as the source and drain by ion implantation to selectively form the impurity diffusion layer 33, and a heat treatment is performed to activate the introduced impurities. Subsequently, the silicon nitride film 33 is depressurized C over the entire surface.
By forming the film to a thickness of 400 ° by the VD method, FIG.
The structure of (a) or (b) is formed.

By the above process, NOR flash EEP
The memory cell transistor of the ROM is completed.

Next, as shown in FIGS. 18A and 18B, a BPSG (Boron Phosphor) having high step coverage over the entire surface is provided.
ous Silicate Glass) film at normal pressure C
The interlayer insulating film 35 is formed by a VD method, and is flattened by reflow by a subsequent heat treatment. Subsequently, a silicon oxide film 36 is formed on the entire surface by a plasma CVD method or the like.

Then, a contact hole 25 as shown in FIGS. 19A and 19B is formed by lithography and anisotropic etching, and the surface of the silicon oxide film 36 in the region where the bit line BL is to be formed is etched. I do.

Thereafter, a contact plug 39 is formed by burying the contact hole 25 with a polycrystalline silicon film or the like, and a region where a bit line BL is to be formed is buried with a titanium film 37 and a tungsten film 38, as shown in FIGS. The structure shown in b) is completed.

According to the above-described nonvolatile semiconductor memory device and its manufacturing method, the hydrofluoric acid-resistant insulating film 28 such as a silicon nitride film is provided on the entire upper surface of the element isolation region 21. Therefore, the insulating film 32 between the floating gate and the control gate is used.
In the cleaning process of the polycrystalline silicon film 31 for the purpose of improving the breakdown voltage, the erosion of the element isolation region 21 can be prevented. Therefore, the element isolation region 21 can maintain a high inversion withstand voltage with respect to the field transistor. In addition, since the element isolation region 21 is not etched, no extra corners are generated in the floating gate 24, so that it is possible to avoid an increase in the number of electric field concentration places as in the prior art, and to reduce the withstand voltage of the floating gate / control gate insulating film 32. Can be maintained. Further, since the element isolation region 21 is protected by the hydrofluoric acid-resistant insulating film 28, the surfaces of the polycrystalline silicon films 30 and 31 can be sufficiently cleaned with a hydrofluoric acid-based processing solution. The withstand voltage of the insulating film 32 can be further improved. Therefore, the withstand voltage of the insulating film 32 between the floating gate and the control gate can be improved and the inversion withstand voltage of the field transistor can be improved, so that the reliability of the nonvolatile semiconductor memory device and the manufacturing method thereof can be improved. Further, since the hydrofluoric acid-resistant insulating film 28 can be formed by self-alignment, a margin when etching the polycrystalline silicon film 31 can be increased, so that the reliability of the manufacturing method can be improved.

The formation of the above-mentioned hydrofluoric acid-resistant insulating film 28 is performed as follows.
This can be performed in a self-aligned manner as shown in FIGS. Therefore, the present method can be applied to a non-volatile semiconductor memory device that has been further miniaturized beyond the processing limit by the lithography technique, and further, since no lithography step is required, the throughput of the non-volatile semiconductor memory device can be improved.

Next, the nonvolatile semiconductor memory device and the method of manufacturing the same according to the second embodiment of the present invention will be described.
An R-type flash EEPROM will be described as an example.

FIGS. 20 and 21 are cross-sectional views of a part of the manufacturing process of the NOR flash EEPROM along the word line direction.

First, a structure as shown in FIG. 9 is formed by the steps described in the first embodiment. In the first embodiment, the hydrofluoric acid-resistant insulating film 28 is exposed by CMP using the hydrofluoric acid-resistant insulating film 28 as a stopper, and the hydrofluoric acid-resistant insulating film 28 on the polycrystalline silicon film 30 is wet-etched.
And a silicon oxide film 43 on the hydrofluoric acid-resistant insulating film 28 (first
Is removed to obtain the structure of FIG.

On the other hand, in the present embodiment, after the structure of FIG. 9 is formed, polishing is performed using the polycrystalline silicon film 30 as a CMP stopper, and in this polishing step, as shown in FIG. The hydrofluoric acid-resistant insulating film on the film 30 is removed.

Thereafter, as shown in FIG. 21, by removing the silicon oxide film 43 by wet etching, the hydrofluoric acid resistant insulating film 28 can be formed in a self-aligned manner over the entire upper surface of the element isolation region 21.

Thereafter, as in the first embodiment, the NOR flash EEPROM shown in FIG. 3 is completed by the manufacturing steps shown in FIGS.

According to the above-described manufacturing method, the step of removing the hydrofluoric acid-resistant insulating film 28 on the polycrystalline silicon film 30 using hot phosphoric acid, which is performed in the first embodiment, can be omitted. It can be shortened and the manufacturing cost can be reduced.

Next, a nonvolatile semiconductor memory device and a method of manufacturing the same according to the third embodiment of the present invention will be described with reference to FIGS.
An R-type flash EEPROM will be described as an example.

FIGS. 22 to 27 are cross-sectional views of a part of the manufacturing process of the NOR flash EEPROM along the word line direction.

First, the structure shown in FIGS. 13A and 13B is formed by the manufacturing method described in the first or second embodiment.

In a subsequent step, the polycrystalline silicon film 31 is patterned by lithography and etching to form a floating gate.
There is a demand for reducing the width of the isolation region between adjacent floating gates.
The demand may exceed the resolution limit of the current lithography process.

In such a case, FIGS. 13 (a) and 13 (b)
In the structure of FIG. 22, a silicon oxide film 44 (second mask material) using, for example, TEOS is formed on the entire surface, and FIG.
The structure shown in FIG.

Next, a photoresist is applied to the entire surface, and is exposed to a size as large as possible by a lithography technique.
Using this photoresist as a mask, the silicon oxide film 44 is used.
Is etched to form the structure of FIG.

Next, as shown in FIG. 24, a silicon oxide film 45 (third mask material) using, for example, TEOS is formed on the entire surface.

Thereafter, the structure shown in FIG. 25 is obtained by performing anisotropic etching by the RIE method. That is, the silicon oxide film 45 can be left on the side wall of the silicon oxide film 44 as a sidewall.

Then, as shown in FIG. 26, etching is performed by the RIE method using the silicon oxide films 44 and 45 to form a floating gate isolation region finer than the resolution limit of the lithography process. it can.

Next, as shown in FIG. 27, the silicon oxide films 44 and 45 are removed by wet etching to complete the floating gate 24. In this wet etching,
Although a hydrofluoric acid-based processing solution is used as an etching solution, the fluoric acid-resistant insulating film 28 is formed on the element isolation region 21, so that the element isolation region 21 can be prevented from being eroded.
Further, simultaneously with the removal of the silicon oxide films 44 and 45, the cleaning of the polycrystalline silicon film 31 can be performed simultaneously.

Thereafter, as explained in the first embodiment, the NOR shown in FIG.
Type flash EEPROM is completed.

According to the above-described manufacturing method, when forming the isolation region of the floating gate, the mask material is first patterned as finely as possible by lithography, and the mask material is further applied to the side walls of the mask material. It is formed in a sidewall shape. The sidewalls can be controlled quite accurately by the film thickness, and by using these two mask materials, etching can be performed on a semiconductor device finer than the resolution limit of lithography technology. .

In the first to third embodiments, N
Although the description has been made by taking the OR type flash EEPROM as an example, it is needless to say that the present invention can be widely applied to a semiconductor memory device having a two-layered gate, such as a NAND type flash EEPROM. Can be implemented.

[0075]

As described above, according to the present invention, it is possible to improve the withstand voltage of the field transistor and the withstand voltage of the insulating film between the floating gate and the control gate by protecting the element isolation region. A nonvolatile semiconductor memory device can be provided.

Further, it is possible to provide a method of manufacturing a nonvolatile semiconductor memory device which can improve throughput by protecting element isolation without using a lithography step.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a NOR flash EEPROM according to a first embodiment of the present invention.

FIG. 2 is a partial plan view of the NOR flash EEPROM according to the first embodiment of the present invention;

FIGS. 3A and 3B are partial cross-sectional views of the NOR flash EEPROM according to the first embodiment of the present invention; FIG. 2A is a line AA ′, and FIG. 2B is a line BB ′; Sectional drawing along the line direction.

FIG. 4 is a sectional view of a first manufacturing step of the NOR flash EEPROM according to the first embodiment of the present invention;
In FIG. 2, (a) is a line AA ′, and (b) is a line B-
Sectional drawing along the B 'line direction.

FIG. 5 is a sectional view of a second manufacturing step of the NOR flash EEPROM according to the first embodiment of the present invention;
In FIG. 2, (a) is a line AA ′, and (b) is a line B-
Sectional drawing along the B 'line direction.

FIG. 6 is a sectional view of a third manufacturing step of the NOR flash EEPROM according to the first embodiment of the present invention;
In FIG. 2, (a) is a line AA ′, and (b) is a line B-
Sectional drawing along the B 'line direction.

FIG. 7 is a sectional view of a fourth manufacturing step of the NOR flash EEPROM according to the first embodiment of the present invention;
In FIG. 2, (a) is a line AA ′, and (b) is a line B-
Sectional drawing along the B 'line direction.

FIG. 8 is a sectional view of a fifth manufacturing step of the NOR flash EEPROM according to the first embodiment of the present invention;
In FIG. 2, (a) is a line AA ′, and (b) is a line B-
Sectional drawing along the B 'line direction.

FIG. 9 is a sectional view of a sixth manufacturing step of the NOR flash EEPROM according to the first embodiment of the present invention;
In FIG. 2, (a) is a line AA ′, and (b) is a line B-
Sectional drawing along the B 'line direction.

FIGS. 10A and 10B are cross-sectional views illustrating a seventh manufacturing process of the NOR flash EEPROM according to the first embodiment of the present invention; FIG. 2A is a sectional view taken along line AA ′, and FIG. Sectional drawing along the BB 'line direction.

11 is a sectional view of an eighth manufacturing process of the NOR flash EEPROM according to the first embodiment of the present invention; FIG. 2 (a) is an AA ′ line, and FIG. Sectional drawing along the BB 'line direction.

FIGS. 12A and 12B are cross-sectional views of a ninth manufacturing process of the NOR flash EEPROM according to the first embodiment of the present invention; FIG. 2A is a line AA ′, and FIG. Sectional drawing along the BB 'line direction.

13 is a sectional view of a tenth manufacturing process of the NOR flash EEPROM according to the first embodiment of the present invention. FIG. 2A is a sectional view taken along line AA ′, and FIG. Sectional drawing along the BB 'line direction.

FIGS. 14A and 14B are cross-sectional views showing an eleventh manufacturing process of the NOR flash EEPROM according to the first embodiment of the present invention; FIG. 2A is a sectional view taken along line AA ′, and FIG. Sectional drawing along the BB 'line direction.

FIG. 15 is a sectional view of a twelfth manufacturing step of the NOR flash EEPROM according to the first embodiment of the present invention; FIG. 2 (a) is a sectional view taken along line AA ′, and FIG. Sectional drawing along the BB 'line direction.

16 is a sectional view of a thirteenth manufacturing process of the NOR flash EEPROM according to the first embodiment of the present invention. FIG. 2A is a sectional view taken along line AA ′, and FIG. Sectional drawing along the BB 'line direction.

17 is a sectional view of a fourteenth manufacturing process of the NOR flash EEPROM according to the first embodiment of the present invention. FIG. 2A is a sectional view taken along line AA ′, and FIG. Sectional drawing along the BB 'line direction.

FIG. 18 is a cross-sectional view showing a fifteenth manufacturing step of the NOR flash EEPROM according to the first embodiment of the present invention; FIG. 2 (a) is an AA ′ line, and FIG. Sectional drawing along the BB 'line direction.

FIG. 19 is a cross-sectional view showing a sixteenth manufacturing process of the NOR flash EEPROM according to the first embodiment of the present invention; FIG. 2 (a) is an AA ′ line, and FIG. Sectional drawing along the BB 'line direction.

FIG. 20 is a sectional view of a first manufacturing step of the NOR flash EEPROM according to the second embodiment of the present invention;

FIG. 21 is a sectional view of a second manufacturing step of the NOR flash EEPROM according to the second embodiment of the present invention;

FIG. 22 is a sectional view of a first manufacturing step of the NOR flash EEPROM according to the third embodiment of the present invention;

FIG. 23 is a sectional view of a second manufacturing step of the NOR flash EEPROM according to the third embodiment of the present invention;

FIG. 24 is a sectional view showing a third manufacturing step of the NOR flash EEPROM according to the third embodiment of the present invention;

FIG. 25 is a sectional view showing a fourth manufacturing step of the NOR flash EEPROM according to the third embodiment of the present invention;

FIG. 26 is a sectional view showing a fifth manufacturing step of the NOR flash EEPROM according to the third embodiment of the present invention;

FIG. 27 is a sectional view of a sixth manufacturing step of the NOR flash EEPROM according to the third embodiment of the present invention;

FIG. 28 is a cross-sectional view of a conventional NOR flash EEPROM.

FIG. 29 is a cross-sectional view of a NOR flash EEPROM for explaining a conventional problem.

FIG. 30 is a cross-sectional view of a conventional NOR flash EEPROM in which a hydrofluoric acid resistant insulating film is provided on an element isolation region.

FIG. 31 is a cross-sectional view of a NOR flash EEPROM provided with a hydrofluoric acid-resistant insulating film on an element isolation region for describing a conventional problem.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 ... Memory cell array 11 ... Row decoder 12 ... Column selector 13 ... Transistor 14 ... Column decoder 15 ... Read / write node 16 ... Source decoder 17, 27 ... Region 20, 100 ... Silicon substrate 21, 110 ... Element isolation region 22, 120 ... Active regions 23, 160 ... Control gates 24, 140 ... Floating gates 25 ... Contact holes 26 ... Bit lines 28, 190 ... Hydrofluoric acid-resistant insulating films 29, 130 ... Gate insulating films 30, 31 ... Polycrystalline silicon films 32, 150 ... an insulating film between a floating gate and a control gate 33 ... an impurity diffusion layer 34, 40 ... a silicon nitride film 35 ... an interlayer insulating film 36, 42, 43, 44, 45 ... a silicon oxide film 37 ... a titanium film 38 ... a tungsten film 39 ... a contact Plug 41: trench 170, 180: floating gate Part

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5F001 AA30 AA43 AB08 AD53 AD60 AF25 AG03 AG07 AG28 AG29 5F083 EP05 EP23 EP54 EP55 EP56 EP76 EP77 ER22 GA24 GA28 JA04 JA39 JA56 MA06 MA20 NA01 PR05 PR29 PR40 5F101 BA12 BB05 BD34 BD35 BF09 B BH13 BH15 BH19

Claims (7)

[Claims] An element isolation region provided on a semiconductor substrate; a hydrofluoric acid-resistant insulating film provided on an entire upper surface of the element isolation region; and an active region provided between adjacent element isolation regions. A first gate electrode, comprising: a first gate insulating film; a first conductive film provided on the first gate insulating film; and a second conductive film provided on the first conductive film. A second gate insulating film provided on the first gate electrode; and a second gate insulating film provided on the second gate insulating film and at least partially overlapping the first gate electrode. A gate electrode; and an interlayer insulating film covering a stacked gate structure formed by stacking the first gate insulating film, the first gate electrode, the second gate insulating film, and the second gate electrode. Wherein the upper surface of the element isolation region is The nonvolatile semiconductor memory device, wherein the lower than the upper surface of the first conductive film. 2. A step of forming a first gate insulating film on a semiconductor substrate; and a step of forming a first conductive film forming a part of a first gate electrode on the first gate insulating film. Forming a trench by etching the first conductive film, the first gate insulating film, and the semiconductor substrate, and forming an element isolation region by embedding an insulating film in the trench; Forming a hydrofluoric acid-resistant insulating film on the entire upper surface of the isolation region in a self-aligned manner with respect to the element isolation region; and forming a second conductive film on the first conductive film and the hydrofluoric acid-resistant insulating film. Forming a first gate electrode by removing at least a portion of the second conductive film on the hydrofluoric acid-resistant insulating film until the second conductive film reaches the hydrofluoric acid-resistant insulating film; Forming a second gate insulating film on the first gate electrode Forming a second gate electrode at least partially overlapping the first gate electrode on the second gate insulating film; and forming the first gate insulating film and the first Forming an interlayer insulating film so as to cover the gate electrode, the second gate insulating film, and a stacked gate structure formed by stacking the second gate electrode. A method for manufacturing a nonvolatile semiconductor memory device. 3. The step of forming a hydrofluoric acid-resistant insulating film over the entire upper surface of the element isolation region in a self-aligned manner with respect to the element isolation region; A step of etching so as to be lower than a surface of the film; a step of forming the hydrofluoric acid-resistant insulating film on the element isolation region and the first conductive film; A step of forming a mask material; a step of removing the first mask material using the hydrofluoric acid-resistant insulating film on the first conductive film as a stopper; 3. The method for manufacturing a nonvolatile semiconductor memory device according to claim 2, further comprising: a step of removing an acid insulating film; and a step of removing the first mask material on the hydrofluoric acid-resistant insulating film. 4. The step of forming a hydrofluoric acid-resistant insulating film over the entire upper surface of the element isolation region in a self-aligned manner with respect to the element isolation region, comprising: A step of etching so as to be lower than a surface of the film; a step of forming the hydrofluoric acid-resistant insulating film on the element isolation region and the first conductive film; Forming a mask material; removing the first mask material using the first conductive film as a stopper; removing the first mask material on the hydrofluoric acid-resistant insulating film; 3. The method for manufacturing a nonvolatile semiconductor memory device according to claim 2, comprising: 5. The method according to claim 1, further comprising, before the step of forming the second conductive film, a step of cleaning the surface of the first conductive film with a treatment solution containing hydrofluoric acid. 5. The method for manufacturing a nonvolatile semiconductor memory device according to claim 2. 6. The method according to claim 1, further comprising, before the step of forming the second gate insulating film, a step of cleaning the surface of the second conductive film with a treatment solution containing hydrofluoric acid. Item 6. The method for manufacturing a nonvolatile semiconductor memory device according to any one of Items 2 to 5. 7. The step of forming a first gate electrode by removing at least a part of the second conductive film on the hydrofluoric acid-resistant insulating film until the second conductive film reaches the surface of the hydrofluoric acid-resistant insulating film, A step of forming a second mask material on the second conductive film; a step of patterning the second mask material by lithography and etching; and a step of forming a pattern on the second mask material and the second conductive film. A step of forming a third mask material; a step of etching the third mask material so as to remain only on a side wall of the second mask material; and a process of using the second and third mask materials. Etching the second conductive film to remove at least a portion of the second conductive film on the hydrofluoric acid-resistant insulating film until reaching the hydrofluoric acid-resistant insulating film; and a treatment solution containing hydrofluoric acid. Removing the second and third mask materials by using 7. The method for manufacturing a nonvolatile semiconductor memory device according to claim 2, further comprising a step of cleaning a surface of the second conductive film.