JP2001273715A - Device and method for detecting jitter of optical disk device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a jitter detector and a jitter detecting method of an optical disk device by which mechanical jitter especially caused by the structure of an optical disk device is detected and jitter generated in the read data from an optical disk is detected with a desired frequency. SOLUTION: A PLL circuit generates read clocks which are phase locked to be synchronized to changing edges of read data read from an optical disk. A lock point compensating circuit 30 and 40 compensate for the points of phase lock of the PLL circuit so that the edges of the read clocks and the changing edges of the read data are simultaneously generated. Having compensated for the points of phase lock by the circuits, jitter of the read data is detected by jitter detecting circuit 30 and 50.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an apparatus and a method for detecting a jitter in an optical disk apparatus.

[0002]

2. Description of the Related Art Conventionally, there has been known an optical disk apparatus capable of writing / reading information on / from an optical disk such as a CD, MD, and DVD. In this optical disk device, an optical pickup reads a signal from an optical disk and
Supply to amplifier. The RF amplifier amplifies and shapes the signal from the optical pickup, and supplies it to the PLL circuit as read data.

The PLL circuit performs frequency pull-in based on the read data from the RF amplifier, then locks the phase of the read clock so as to synchronize with the read data, and reads the read data using the phase-locked read clock. To detect. The detected read data is sent to the signal processing unit. Then, error detection and correction, EFM demodulation, and the like are performed in this signal processing unit, and final reproduction data is generated.

Incidentally, the read data from the PLL circuit includes jitter (fluctuation of the signal in the time axis direction). The jitter includes jitter caused by the optical disc itself, for example, a defect caused by a pit formed on the optical disc, a scratch formed on the optical disc, and a mechanical jitter caused by the structure of the optical pickup system. If errors caused by these jitters occur frequently, the error rate is deteriorated, and the optical disk device may become uncontrollable.

Therefore, conventionally, an error rate is calculated at a predetermined cycle in a signal processing unit, and an optical pickup or an RF amplifier is adjusted based on the error rate.

[0006]

However, since the error rate detected by the conventional optical disk device is based on read data, errors that are the basis for calculating the error rate include not only mechanical jitter but also jitter of the media itself. Errors caused by the as a result,
There is a problem that it is difficult to make adjustments targeting mechanical jitter. Also, in the conventional optical disk device,
Since the update cycle of the error rate is long, for example, several hundreds to several thousands of sync frames, there is a problem that the frequency of adjusting the optical pickup system is low.

As a related technique, Japanese Patent Application Laid-Open No.
Japanese Patent Laid-Open No. 191225 discloses an "optical disk device". In this optical disk device, an RF envelope signal is output from an RF signal reproduced from an optical pickup by an RF envelope detection unit and input to a jitter minimization algorithm unit. In addition, jitter is detected by a jitter amount detector from a phase error signal of a PLL (Phase Locked Loop) loop.
The lock determination signals are respectively detected by the PLL lock detection units, and are respectively input to the jitter minimization algorithm units. The jitter minimizing algorithm section first adjusts the focus offset so that the RF envelope is maximized, then confirms the range in which the PLL is locked, and finally adjusts the focus offset so that jitter is minimized. Thereby, the focus offset adjustment can be optimally performed.

However, Japanese Patent Application Laid-Open No. 11-1912
No. 25 discloses a configuration for minimizing the jitter amount using the detected jitter amount, but does not disclose a configuration and a method for detecting the jitter amount.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a jitter detecting device and a jitter detecting method for an optical disk device capable of detecting mechanical jitter caused by the structure of the optical disk device. It is another object of the present invention to provide a jitter detecting apparatus and a jitter detecting method for an optical disk apparatus capable of detecting jitter occurring in read data from an optical disk at a desired frequency.

[0010]

According to a first aspect of the present invention, there is provided an apparatus for detecting jitter in an optical disk, the phase lock of which is synchronized with a changing edge of read data read from the optical disk to achieve the above object. A PLL circuit for generating a read clock, a lock point correction circuit for correcting a phase lock point of the PLL circuit so that an edge of the read clock and a change edge of the read data occur simultaneously, and a lock point. A jitter detection circuit for detecting the jitter of the read data after the phase lock point is corrected by the correction circuit,
And

In a conventional PLL circuit, the lock point is not always at a desired position due to variations in the characteristics of the analog circuit, collapse of the read clock duty, and the like. Therefore, in the optical disk jitter detection apparatus according to the present invention, the lock point correction circuit
After locking the edge of the read data to the falling edge of the read clock, jitter detection is started. This eliminates an error caused by the jitter of the medium itself, so that the jitter can be detected by focusing on the mechanical jitter caused by the structure of the optical disk device.

In this jitter detecting apparatus, the PLL
The circuit comprises a PLL loop including a phase comparator that compares the phase of the read data and the read clock, and an oscillator that changes the frequency of the read clock in accordance with the comparison result of the phase comparator. The point correction circuit supplies oscillation control data for changing the oscillation frequency of the oscillator to the oscillator, thereby
It can be configured to correct the point of phase lock of the L circuit.

The lock point correction circuit may further include a phase delay period in which the phase of the read clock is delayed with respect to the read data, and a phase advance period in which the phase of the read clock is advanced with respect to the read data. A first counter for counting a change edge of the read data when the detection circuit detects the phase delay period, and the phase advance period for the detection circuit. A second counter that counts a change edge of the read data when is detected, if the difference between the value of the first counter and the value of the second counter is larger than a predetermined value, The point of the phase lock is corrected by supplying the corresponding oscillation control data to the oscillator, and the point of the phase lock is corrected if the point is within the predetermined value. It can be configured to determine that the.

Further, the jitter detection circuit counts a pulse generated when a change edge of the read data deviates from an edge of the read clock in a state where the phase lock point is corrected by the lock point correction circuit. And a clearing means for clearing the value of the counter at an arbitrary cycle, and the value of the counter immediately before being cleared by the clearing means can be detected as a jitter amount.

According to this configuration, the period for clearing the counter by the clearing unit can be set to a desired period, so that the frequency of adjusting the optical pickup system can be arbitrarily determined.

Further, in the jitter detecting method for an optical disk according to the second aspect of the present invention, a read clock phase-locked to be synchronized with a changing edge of read data read from the optical disk is generated, and the generated read clock is generated. The phase lock point is corrected so that the edge of the read clock and the change edge of the read data occur simultaneously, and the jitter of the read data is detected after the phase lock point is corrected. Have been.

In this jitter detection method, the step of generating the read clock includes comparing the phase of the read data with the phase of the read clock, and changing the frequency of the read clock according to the comparison result. Generating the read clock and correcting the phase lock point, wherein the phase lock point is corrected by further changing the frequency of the read clock based on oscillation control data for changing the oscillation frequency. Can be configured.

In the step of correcting the phase lock point, the phase of the read clock is delayed with respect to the read data, and the phase of the read clock is advanced with respect to the read data. A phase advance period is detected, and when it is detected that the phase is a phase delay period, a change value of the read data is counted to calculate a first value, and the phase advance period is detected. In this case, a change value of the read data is counted and a second value is calculated. If the difference between the first value and the second value is larger than a predetermined value, the oscillation control according to the difference is performed. The phase lock point may be further corrected based on the data, and if within the predetermined value, it may be determined that the phase lock point has been corrected.

Further, in the step of detecting the jitter of the read data, the pulse generated when the change edge of the read data deviates from the edge of the read clock in a state where the phase lock point has been corrected. It can be configured so that counting is performed for each cycle, and the counting result is detected as a jitter amount for each cycle.

[0020]

Embodiments of the present invention will be described below with reference to the drawings.

First, an outline of an optical disk device to which a jitter detection device according to an embodiment of the present invention is applied will be described.
FIG. 1 is a block diagram showing a schematic configuration of an optical disc device to which a jitter detection device according to an embodiment of the present invention is applied.

This optical disk device includes a spindle motor 10, an optical pickup 11, an actuator 12, an RF
Amplifier 13, EFM (Eight to Fourteen Modulation)
Comparator 14, PLL circuit 15, decoder 16, memory controller (HOSTI / F) 17, central processing unit (hereinafter referred to as "CPU") interface (CPU
(I / F) 18, a main controller 19, a digital servo processor 20, and a driver 21. Among them, the EFM comparator 14, the PLL circuit 1
5, the decoder 16, the memory controller 17, the CPU interface 18, the main controller 19, and the digital servo processor 20 are provided as a signal processing LSI.

A buffer RAM 22 and a personal computer 23 are connected to the memory controller 17 of the signal processing LSI. Also, the CPU interface 18
Is connected to a microcomputer 24.

The spindle motor 10 rotates the optical disc 1 fastened to its rotating shaft. The rotation speed of the spindle motor 10 is controlled according to a rotation servo signal from the driver 21.

The optical pickup 11 irradiates the signal surface of the optical disc 1 with a laser beam, detects the light beam reflected and returned from the signal surface, and outputs a signal modulated according to the presence or absence of a pit. I do. This optical pickup 11
Is supplied to the RF amplifier 13. The optical pickup 11 is configured to be moved by an actuator 12 in the radial direction of the optical disk 1 and in the direction perpendicular to the surface of the optical disk 1.

The actuator 12 moves the optical pickup 11 in the radial direction of the optical disk 1 according to a tracking servo signal supplied from the driver 21. Further, the actuator 12 moves the optical pickup 11 in a direction perpendicular to the surface of the optical disc 1 by a focus servo signal supplied from the driver 21.

The RF amplifier 13 amplifies the signal from the optical pickup 11 and shapes the waveform. This RF amplifier 1
3 includes an equalizer (not shown). This equalizer uses MTF (Modulation Transfer Functio
n) and the degradation of PTF (Phase Transfer Function) are corrected. The characteristics of the equalizer are controlled by a control signal from the CPU interface 18. The equalized RF signal from the RF amplifier 13 is supplied to the EFM comparator. In addition, this RF amplifier 13
Generates a servo error signal and supplies it to the digital servo processor 20. The servo error signal includes signals of a focus error, a tracking error, and a lens error.

The EFM comparator 14 is an RF amplifier 1
The RF signal from No. 3 is binarized by slicing it at a predetermined slice level. Thus, digital read data is obtained. The read data from the EFM comparator 14 is supplied to the PLL circuit 15. The slice level in the REF comparator 14 is C
It can be changed by a control signal from the PU interface 18.

The PLL circuit 15 includes the jitter detector of the present invention. The PLL circuit 15 generates a read clock synchronized with a clock component included in the read data from the EFM comparator 14, which will be described in detail later.
The read data is detected using the generated read clock and supplied to the decoder 16. PLL circuit 1
Reference numeral 5 corrects the lock point so that the changing edge of the read data and the falling edge of the read clock overlap, and then detects jitter. This detection result is CP
It is supplied to the U interface 18.

The decoder 16 decodes data from the PLL circuit 15. That is, data recorded on the optical disc 1 is EFM-modulated to prevent continuation of a state in which no pit exists on a track, and further, for example, CIRC (Cross
Interleave Read-Solomon Code). The decoder 16 decodes the read decoder encoded by the CIRC method, and further performs EFM demodulation. The data decoded by the decoder 16 is supplied to a memory controller 17 and a CPU interface 18.

The memory controller 17 stores data from the decoder 16 in the buffer RAM 22 under the control of the main controller 19, and stores the data in the buffer RA22.
Control is performed to read out the data stored in M22 and send it to the personal computer 23. If the optical disc is a writable medium, control is performed to read data from the personal computer 23 and store the data in the buffer RAM 22. In this case, the data stored in the buffer RAM 22 is written to the optical disc 1 via a path (not shown).

The CPU interface 18 has a signal processing L
EFM comparator 14 inside SI, PLL circuit 15,
It controls data transfer between the decoder 16, the main controller 19, the digital servo processor 20, and the microcomputer 24 connected to the outside of the signal processing LSI.

The main controller 19 includes the decoder 1
6. It controls the memory controller 17 and the CPU interface 18 to control the transfer of various data between them.

The digital servo processor 20 has a CPU
A rotation servo signal, a tracking servo signal, and a focus servo signal are generated based on an instruction from the interface 18 and a servo error signal from the RF amplifier 13,
It is supplied to the driver 21.

The driver 21 amplifies the rotation servo signal from the digital servo processor 20 and supplies it to the spindle motor 10. Thereby, the spindle motor 10
Is controlled. Further, the driver 21 amplifies the tracking servo signal and the focus servo signal from the digital servo processor 20 and supplies them to the actuator 12. Thereby, the optical pickup 11
Of the optical disc 1 in the radial direction and the movement of the optical pickup 11 in the direction perpendicular to the surface of the optical disc 1 are controlled.

(Embodiment 1) Next, details of a PLL circuit 15 including a jitter detector according to Embodiment 1 of the present invention will be described.

FIG. 2 is a block diagram showing a configuration of a portion for detecting jitter included in the PLL circuit 15. As shown in FIG. This P
The LL circuit 15 includes a common control unit 30, a lock point correction unit 40, and a jitter detection unit 50.

First, the common control unit 30 will be described.
The common control unit 30 includes a frequency comparator 31, a frequency comparator control register 31a, a phase comparator 32, a phase comparator control register 32a, an oscillator 33, an oscillator control register 33a, a frequency divider 34, a flip-flop 35 , 36
37, and an ENOR gate 38.

The frequency comparator 31 performs EF according to the frequency control data from the frequency comparator control register 31a.
An error between the frequency component included in the read data from the M comparator 14 and the frequency of the read clock output from the frequency divider 34 is detected. The detected error is generated by the oscillator 3
3 is supplied. Although not shown, the frequency control data for controlling the frequency comparator 31 from the microcomputer 24 via the CPU interface 18 is set in the frequency comparator control register 31a.

The phase comparator 32 changes the read data edge (rising edge and falling edge) in accordance with the phase control data from the phase comparator control register 32a.
And an error between the read clock and the falling edge of the read clock. This detection result is supplied to the oscillator 33 as a PCUP signal and a PCDN signal. Although not shown, the phase control data for controlling the phase comparator 32 from the microcomputer 24 via the CPU interface 18 is set in the phase comparator control register 32a.

As shown in FIG. 3C, the PCUP signal is a pulse having a width from the changing edge of the read data to the falling edge of the read clock pulse that first rises after the changing edge. . Also, P
The CDN signal is a pulse having a width from the first rising edge of the read clock to the next rising edge after the PCUP signal falls, as shown in FIG.

The oscillator 33 includes a charge pump and a voltage controlled oscillator (VCO), not shown. The charge pump generates a voltage corresponding to the difference between the pulse width of the PCUP signal and the pulse width of the PCDN signal. That is, PCU
If the pulse width of the P signal is longer than the pulse width of the PCDN signal, the current voltage is increased by the difference in pulse width, and if shorter, the current voltage is decreased by the difference in pulse width. The voltage from this charge pump is supplied to the VCO.

The VCO generates a signal that oscillates at a frequency corresponding to the voltage supplied from the charge pump and the signal supplied from the oscillator control register 33a. The signal generated by the VCO is supplied to a frequency divider 34. Although not shown, the oscillation control data for controlling the oscillator 33 from the microcomputer 24 via the CPU interface 18 is set in the oscillator control register 33a. This oscillator control register 3
3a is used to change the lock point under the control of the microcomputer 24.

The frequency divider 34 divides the frequency of the signal from the oscillator 33 and outputs it as a read clock. This divider 34
Is provided to reduce a frequency band that can be oscillated by the VCO to a frequency band suitable for a read clock. The read clock output from the frequency divider 34 is
In addition to the frequency comparator 31 and the phase comparator 32 described above,
It is supplied to flip-flops 35, 36 and 37.

Flip-flops 35 and 36 and EN
The OR gate 38 forms a digital differentiating circuit for detecting a change edge of the read data. The flip-flop 35 latches the read data input to the data input terminal D at the falling edge of the read clock input to the clock input terminal. The signal from the output terminal Q of the flip-flop 35 is supplied to the data input terminal of the flip-flop 36 and one input terminal of the ENOR gate 38.

The flip-flop 36 latches data from the output terminal Q of the flip-flop 35 input to the data input terminal D at the falling edge of the read clock input to the clock input terminal. This flip-flop 3
The signal from the output terminal Q of No. 6 is supplied to the other input terminal of the ENOR gate 38. The ENOR gate 38 takes the exclusive logic of the signal from the output terminal Q of the flip-flop 35 and the signal from the output terminal Q of the flip-flop 36, inverts the signal, and outputs the inverted signal as the SIG_A signal.

Therefore, as shown in FIG. 3E, the SIG_A signal output from the digital differentiating circuit is changed from the first falling edge of the read clock to the next falling edge after the change edge of the read data appears. The pulse becomes the L level during the period. The SIG_A signal is supplied to the lock point corrector 40 and the jitter detector 50.
Supplied to

The flip-flop 37 is connected to the phase comparator 32
, The read clock is latched in synchronization with the rising edge of the PCUP signal, and the latched read clock is output as the SIG_B signal. Therefore, this SIG_B signal is, as shown in FIG.
The section in which the read clock is delayed with respect to the read data is at the H level, and the section in which the read clock is advanced with respect to the read data is at the L level. When the falling edge of the read clock and the change edge of the read data overlap, the level becomes H level or L level with a probability of 50%.
This SIG_B signal is supplied to the lock point correction unit 40 and the jitter detection unit 50.

Next, the lock point correction section 40 will be described. The lock point correction unit 40 includes a gate circuit 41, a counter U42, a register 42A, a NOR gate 43, a counter D44, and a register 44A.

The gate circuit 41 is connected to the EN of the common control unit 30.
A signal obtained by inverting the SIG_A signal from the OR gate 38 and the SI from the flip-flop 37 of the common control unit 30
The logical AND with the G_B signal is taken and output as the SIG_D signal. Accordingly, in the SIG_D signal, as shown in FIG. 3 (G), in a section where the read clock is delayed with respect to the read data, a pulse appears every time a change edge of the read data appears, and the read clock is generated with respect to the read data. In the leading section, a signal in which no pulse appears even if a change edge of the read data appears. In a section where the falling edge of the read clock and the changing edge of the read data overlap, a signal in which a pulse appears with a probability of 50%. This SIG_D signal is supplied to the counter U42.

The counter U42 is cleared by a counter reset signal RST1 from the CPU interface 18. This counter reset RST1 signal is transmitted from the microcomputer 24 to the C
It is supplied via the PU interface 18. Note that the cycle of outputting the counter reset RST1 signal is not limited to the sync frame unit, but can be arbitrarily adjusted according to the rotation speed of the optical disc 1 and the type of the optical disc 1.

This counter U 42 counts the number of pulses of the SIG_D signal from the gate circuit 41. Therefore, the counter U42 counts up each time the read data changes in a section where the read clock is delayed with respect to the read data, and stops counting up in a section where the read clock advances with respect to the read data. In a section where the falling edge of the read clock and the change edge of the read data overlap, the count-up is performed with a probability of 50%. The output of this counter U42 is
2A. The register 42A stores the counter U42 in synchronization with the rising edge of the counter reset signal RST1.
Latch the value of. The value of this register 42A is
It is supplied to the interface 18.

The NOR gate 43 is connected to the E of the common control unit 30.
The logical sum of the SIG_A signal from the NOR gate 38 and the SUB_B signal from the flip-flop 37 is obtained, inverted, and output as a SIG_E signal. Therefore, SIG_
As shown in FIG. 3H, in the section where the read clock is delayed with respect to the read data, no pulse appears even if a change edge of the read data appears, and the read clock advances with respect to the read data. Is a signal in which a pulse appears each time the read data changes. In a section where the falling edge of the read clock and the changing edge of the read data overlap, a signal in which a pulse appears with a probability of 50%. This SIG_E signal is a counter D
44.

The counter D44 is cleared by the above-mentioned counter reset RST1 signal from the CPU interface 18. This counter D44 counts the number of pulses of the SIG_E signal from the NOR gate 43. Therefore, the counter D44 stops counting up in a section in which the read clock is delayed with respect to the read data, and counts up every time the read data changes in a section in which the read clock advances with respect to the read data. In a section where the falling edge of the read clock and the change edge of the read data overlap, the count-up is performed with a probability of 50%. The output of this counter D44 is
It is supplied to the register 44A. The register 44A latches the value of the counter D44 in synchronization with the rising of the counter reset RST1 signal. The value of the register 44A is supplied to the CPU interface 18.

Next, the jitter detector 50 will be described. This jitter detector 50 is a three-input AND gate 5
One- and two-input AND gate 52, low-pass filter (L
PF) 53, a Schmitt circuit 54, a counter 55, and a register 55A.

The AND gate 51 is connected to the E of the common control unit 30.
The logical product of the SIG_A signal from the NOR gate 38, the SIG_B signal from the flip-flop 37, and the PCUP signal from the phase comparator 32 is obtained and output as a SIG_C signal. This SIG_C signal is supplied to one input terminal of the AND gate 52. The other input terminal of the AND gate 52 receives the jitter detection EN signal. This jitter detection EN signal is a signal sent from the microcomputer 24 via the CPU interface 18. The output of the AND gate 52 is supplied to a low-pass filter 53.

The low-pass filter 53 removes a glitch from the SIG_C signal. The signal from the low-pass filter 53 is supplied to a Schmitt circuit 54. The Schmitt circuit 54 extends the pulse width of the signal from the low-pass filter 53. The signal from the Schmitt circuit 54 is supplied to a counter 55.

The counter 55 has the CPU interface 1
8 is cleared by the counter reset signal RST2. This counter reset RST2 signal is transmitted from the microcomputer 24 to the CP in units of sync frames, for example.
It is supplied via the U interface 18. Note that the cycle of outputting the counter reset RST2 signal is not limited to the sync frame unit, but can be arbitrarily adjusted according to the rotation speed of the optical disc 1 and the type of the optical disc 1.
Thereby, the update cycle of the error rate can be set arbitrarily, so that the problem that the frequency of adjusting the optical pickup system is low because the update cycle of the error rate is long as in the related art can be solved.

The counter 55 includes a Schmitt circuit 54
The number of pulses from is counted. The value of this counter 55 is
This is a value representing the amount of jitter. The output of this counter 55 is
It is supplied to the register 55A. The register 55A latches the value of the counter 55 in synchronization with the rising of the counter reset RST2 signal. The value of the register 55A is supplied to the CPU interface 18.

Next, the operation of the PLL circuit 15 configured as described above will be described with reference to the timing charts shown in FIGS.

First, the operation of the lock point correction will be described. Lock point correction is performed by the common control unit 3 shown in FIG.
This is performed by a lock point correction circuit composed of 0 and a lock point correction unit 40. FIG. 3 and FIG.
6 is a timing chart showing the operation of the lock point correction.

FIG. 3A shows the waveform of the read clock output from the frequency divider 34, and FIG. 3B shows the waveform of the read data supplied from the EFM comparator 14 (see FIG. 1). 3A and 3B show the state where the read clock is delayed with respect to the read data, and the broken lines T3 and T4 show the state where the read clock is delayed with respect to the read data. The dashed lines T5 and T6 indicate a state where there is no delay or advance of the read clock for the read data.

First, the operation when the read clock is behind the read data will be described.

In this case, the microcomputer 24
The frequency control data is set in the frequency comparator control register 31a via the CPU interface 18, and the oscillation control data is set in the oscillator control register 33a. As a result, the oscillator 33 starts oscillating at a predetermined frequency, and a frequency loop is formed by the frequency comparator 31, the oscillator 33, and the frequency divider 34. When the frequency controlled by the loop becomes a predetermined frequency, the phase comparator 32 and the oscillator 33
And a phase loop constituted by the frequency divider 34.

When performing the jitter detection, the microcomputer 24 activates the counter reset RST1 signal to clear the counters U42 and D44. At this time, the values of the counter U42 and the counter D44 are latched by the registers 42A and 44A, respectively. Further, the counter reset RST2 signal is activated to clear the counter 55. At this time, the value of the counter 55 is latched in the register 55A. After the lock point correction operation is started in this way, as shown by broken lines T1 and T2 in FIGS. 3A and 3B, if the read clock is delayed with respect to the read data, as shown in FIG. 3
As shown in (C), a PCUP signal having a pulse longer than one read clock period is generated in response to the rise or fall of the read data.

Further, as shown in FIG. 3D, the PCDN signal is set to the H level only for one read clock period from the first rising edge of the read clock to the next rising edge after the PCUP signal falls. Become. These PCUP and PCDN signals are output from the oscillator 3
3, the phase loop performs a normal PLL operation for advancing the phase of the read clock by the difference between the pulse width of the PCUP signal and the pulse width of the PCDN signal.

On the other hand, since the phase of the read clock lags behind the read data,
The SIG_B signal from the flip-flop 37, which is latched at the rising edge of the CUP signal, is set to the H level in both the broken line portions T1 and T2, as shown in FIG. Also, SI from ENOR gate 38
The G_A signal is 1 after the appearance of the change edge of the read data.
It becomes L level only during the read clock period.

As a result, the gate circuit 41 is switched to the state shown in FIG.
As shown in FIG. 5, the SIG_A signal having the same phase as the SIG_A signal is output. The counter U42 is counted up by the SIG_D signal. NO
Since the SIG_B signal is at the H level, the R gate 43 maintains the SIG_E signal at the L level as shown in FIG. Therefore, the value of the counter D44 does not change.

The above operation is repeated while the read clock is behind the read data (while the SIG_B signal is at the H level). That is, while the read clock is behind the read data, a pulse appears in the SIG_D signal as shown in FIG. 6A, and the SIG_E signal is at the L level as shown in FIG. 6B. To maintain. As a result, as shown in FIG. 6 (D), the value of the counter U42 sequentially increases as “a → a + 1 → a + 2 → a + 3 →...”, But the value of the counter D44 becomes as shown in FIG. 6 (F). As shown, "b" is maintained.

In the above state, when a counter reset signal RST1 is supplied from the microcomputer 24 via the CPU interface 18 as shown in FIG. 6C, the counter reset signal RST1 is synchronized with the rising edge of the counter reset signal RST1. The value "a + 3" of the counter U42 is latched in the register 42A as shown in FIG. 6 (E), and the value "b" of the counter D44 is latched in the register 44A as shown in FIG. 6 (G). Is done. Thereafter, the counter U42 sets the SIG_D as shown in FIG.
After being cleared by the first pulse of the signal, counting up is restarted in response to the pulse of the SIG_D signal. Similarly, the counter D44, as shown in FIG.
After being cleared by the first pulse of the signal, counting up is restarted according to the pulse of the SIG_B signal. The microcomputer 24 sends the values latched in these registers 42A and 44A to the CPU interface 18
Ingest through.

The microcomputer 24 has a counter U
Since the value of 42 is larger than the value of the counter D44, oscillation control data for increasing the oscillation frequency of the oscillator 33 is generated and set in the oscillator control register 33a via the CPU interface 18. Accordingly, the phase loop is controlled so that the change edge of the read data approaches (overlaps) the falling edge of the read clock.

Next, the operation when the read clock is advanced with respect to the read data will be described.

In the case of performing jitter detection, as shown by broken lines T3 and T4 in FIGS. 3A and 3B, if the read clock is advanced with respect to the read data, FIG.
As shown in (C), a PCUP signal having a pulse shorter than one read clock period is generated in response to the rise or fall of the read data. The PCDN signal is the same as the case where the read clock is behind the read data described above. When the PCUP signal and the PCDN signal are supplied to the oscillator 33, the phase loop performs a normal PLL operation for delaying the phase of the read clock by the difference between the pulse width of the PCUP signal and the pulse width of the PCDN signal.

On the other hand, since the phase of the read clock is advanced with respect to the read data,
The SIG_B signal from the flip-flop 37, which is latched at the rising edge of the CUP signal, is set to the L level in both of the broken lines T3 and T4, as shown in FIG. Also, SI from ENOR gate 38
The G_A signal is 1 after the appearance of the change edge of the read data.
It becomes L level only during the read clock period.

As a result, the gate circuit 41 outputs SIG_B
Since the signal is at the L level, as shown in FIG.
The SIG_D signal is maintained at the L level. Therefore, the value of the counter U42 does not change. Also, the NOR gate 43
FIG. 3H shows that the SIG_B signal is at the L level.
As shown in (1), the SIG_A signal having the same phase as the SIG_A signal is output. The value of the counter D44 is counted up by the SIG_E signal.

The above operation is repeated while the read clock advances for the read data (while the SIG_B signal is at the L level). That is, while the read clock is behind the read data, the SIG_D signal maintains the L level as shown in FIG. 6A, and the SIG_E signal has a pulse as shown in FIG. Appears. As a result, the value of the counter U42 maintains “3” as shown in FIG. 6D, but the value of the counter D44 becomes
As shown in (F), the number sequentially increases from “0 → 1 → 2 → 3 →...”.

In the above state, although not shown in FIG. 6, when a counter reset signal RST1 is supplied from the microcomputer 24 via the CPU interface 18, the counter reset signal RST1 is synchronized with the rising of the counter reset signal RST1. , The value of the counter U42 is latched in the register 42A, and the value of the counter D44 is latched in the register 44A. Thereafter, the counter U42
Is S after being cleared by the first pulse of the SIG_D signal.
The counting up is restarted in response to the pulse of the IG_D signal. Similarly, after being cleared by the first pulse of the SIG_B signal, the counter D44 restarts counting up according to the pulse of the SIG_B signal. The microcomputer 24 takes in the values latched in the registers 42A and 44A via the CPU interface 18.

The microcomputer 24 has a counter U
Since the value of 42 is smaller than the value of the counter D44, oscillation control data for lowering the oscillation frequency in the oscillator 33 is generated and set in the oscillator control register 33a via the CPU interface 18. Accordingly, the phase loop is controlled so that the change edge of the read data approaches (overlaps) the falling edge of the read clock.

Next, the operation in the case where there is no delay or advance of the read clock with respect to the read data will be described.

In the case of performing the jitter detection, as shown in broken lines T5 and T6 in FIGS. 3A and 3B, if there is no delay or advance of the read clock with respect to the read data, FIG. As shown in C), a PCUP signal having a pulse substantially equal to one read clock period is generated in response to the rise or fall of the read data.
The PCDN signal is the same as the case where the read clock is behind the read data described above. These PCs
When the UP signal and the PCDN signal are supplied to the oscillator 33, the phase loop performs a normal PLL operation of entering a lock state.

On the other hand, since there is no delay or advance of the phase of the read clock with respect to the read data, the SIG_B signal from the flip-flop 37 that latches the read clock at the rising edge of the PCUP signal is shown in FIG. As shown, in each of the broken line portions T3 and T4, the L level is set at a probability of approximately 50%. Further, the SIG_A signal from the ENOR gate 38 becomes L level only for one read clock period after the appearance of the change edge of the read data.

As a result, the gate circuit 41 outputs SIG_B
Since the signal goes to the L level with a probability of 50%, FIG.
As shown in the figure, a pulse appears in the SIG_D signal with a probability of 50%. Therefore, the value of the counter U42 changes with a probability of 50%. Further, the NOR gate 43 is connected to the SIG_
Since the B signal goes to the L level with a probability of 50%, FIG.
As shown in (H), a SIG_E signal in which a pulse having the same phase as the SIG_A signal appears with a probability of 50% is output.
The value of the counter D44 is counted up by the SIG_E signal.

The above operation is performed while there is no delay and advance of the read clock with respect to the read data, that is, while the probability that the delay of the read clock and the probability of the advance with respect to the read data are 50%. Is repeated. Accordingly, the value of the counter U42 and the value of the counter D44 sequentially increase while maintaining substantially equal values.

In the above state, although not shown in FIG. 6, when the counter reset signal RST1 is supplied from the microcomputer 24 via the CPU interface 18, the counter U42 is operated in the same manner as described above. The value is latched in the register 42A and the value of the counter D44 is latched in the register 44A. Thereafter, the counter U42 and the counter D44 each restart counting up. The microcomputer 24 stores the values latched in these registers 42A and 44A,
The data is fetched via the CPU interface 18.

The microcomputer 24 has a counter U
It is recognized that the lock point correction is completed when the value of the counter 42 is substantially equal to the value of the counter D44 (within a predetermined difference range), that is, when the changing edge of the read data overlaps the falling edge of the read clock. Then, start jitter detection. In this state, the error caused by the jitter of the medium itself is corrected by the decoder 16. Therefore, after the completion of the lock point correction, mechanical jitter due to the structure of the optical disk device is generated with a probability of about 50% before and after the falling edge of the read clock. Specialized jitter detection can be performed.

Next, the operation of jitter detection will be described. First, jitter appears in a range as shown in FIG. That is, when the read clock lags behind the read data, jitter appears in the range indicated by A1 and A2 in FIG. In this case, when the jitter is detected by the jitter detecting device, a larger amount of jitter is detected than is actually the case. On the other hand, when the read clock is advanced with respect to the read data, jitter appears in the range indicated by B1 and B2 in FIG. In this case, when the jitter is detected by the jitter detection device, a smaller amount of jitter than the actual amount is detected.

On the other hand, if there is no delay or advance of the read clock with respect to the read data,
Jitter appears in the ranges indicated by 1 and C2. That is, when the lock point is corrected by the lock point correction circuit, the jitter generated in the read data exists symmetrically with respect to the time axis with respect to the falling edge of the read clock. In this case, when jitter is detected by the jitter detection device, the actual amount of jitter is detected. Therefore, when jitter is detected after the lock point is corrected by the lock point correction circuit, it can be seen that the actual amount of jitter is detected. Also, by detecting the jitter amount on one side with respect to the falling edge of the read clock,
It is possible to know the total amount of jitter.

The jitter is detected by the common control unit 3 shown in FIG.
This is performed by a jitter detection circuit composed of 0 and a jitter detection unit 50. FIG. 5 is a timing chart showing the operation of the jitter detection. This jitter detection operation
The microcomputer 24 is the CPU interface 18
Through the Jitter detection EN signal of the jitter detection unit 50
Start by sending to ND gate 52.

When the lock point correction is completed by the above-described operation and jitter occurs in a state where the change edge of the read data overlaps the falling edge of the read clock, the change of the read data with respect to the falling edge of the read clock. A phenomenon occurs in which the edge shifts in the time axis direction. That is, the jitter occurs symmetrically before and after the positions indicated by P1 and P4 in FIG.

Now, as shown by P2 in FIG. 5, it is assumed that a jitter occurs such that the falling edge of the read data is temporally shifted (leftward in the figure) from the falling edge of the read clock. . In this case, the common control unit 30
Since all of the PCUP signal, SIG_A signal, and SIG_B signal from the controller are at the H level only during the above-mentioned deviation,
As shown in FIG. 5C, the AND gate 51 generates a SIG_C signal having a pulse width corresponding to the shift time,
Supply to AND gate 52. At this time, the jitter detection EN
Since the signal is at the H level, the pulse of the SIG_C signal passes through the AND gate 52 and is supplied to the low-pass filter 53. The high-frequency component is removed by the low-pass filter 53, and the pulse width is further reduced by the Schmitt circuit 54. It is spread and supplied to the counter 55. This allows
The counter 55 counts up.

As shown by P5 in FIG. 5, when the rising edge of the read data is temporally shifted forward (left side in the figure), jitter occurs in the same manner as described above.
A pulse is generated in the signal, and the counter 55 counts up. It should be noted that when a jitter occurs such that the rising edge of the read data is shifted backward (right side in the figure) as shown by P3 in FIG. 5, and when the falling edge of the read data is shifted as shown by P6. If jitter occurs that shifts backward in time (right side in the figure), S
Although no pulse is generated in the IG_C signal, the jitter occurs with a probability of about 50% before and after the falling edge of the read clock. it can.

In the above state, when the counter reset RST2 signal is supplied from the microcomputer 24 via the CPU interface 18, the value of the counter 55 is latched in the register 55A in synchronization with the rising of the counter reset RST2 signal. You. Thereafter, the counter 55 is cleared by the first pulse of the signal output from the Schmitt circuit 54, and then restarts counting up according to the pulse of the signal. The microcomputer 24 can take in the value latched in the register 55A via the CPU interface 18 by outputting a counter reset RST2 signal at an arbitrary cycle.

Then, the microcomputer 24 uses the value of the counter 55 taken in by the RF amplifier 13
Correction of the equalizing characteristic of the optical pickup 11 and the focus balance and tilt correction of the optical pickup 11 are performed. By performing these corrections, the state of reading data from the optical disk 1 can be optimized, and the error rate can be reduced.

(Embodiment 2) Next, a PLL circuit 15 including a jitter detector according to Embodiment 2 of the present invention will be described.

FIG. 7 is a block diagram showing a configuration of the jitter detector according to the second embodiment. In this jitter detection device, the lock point correction unit 40 'has the same structure as that of the jitter detection device according to the first embodiment.
And different. That is, in the lock point correction unit 40 'of the second embodiment, an up / down counter 45 is provided instead of the counter U42 and the counter D44, and a register 46 is provided instead of the registers 42A and 44A.

The up / down counter 45 is cleared by a counter reset signal RST1 from the CPU interface 18. This up-down counter 45
Counts up in response to the SIG_D signal from the gate circuit 41,
Count down in response to the _E signal. Therefore, the up / down counter 45 counts up every time the read data changes in a section where the read clock is delayed with respect to the read data, and every time the read data changes in a section where the read clock advances with respect to the read data. Count down to In a section where the falling edge of the read clock and the changing edge of the read data overlap, one of the count-up and the count-down is performed with a probability of 50%.

The up / down counter 45 outputs the count value as a SIG_H signal. The up / down counter 45 outputs the SIG_F signal and the SIG_F signal.
A circuit for generating a G signal is included. The SIG_F signal becomes H level when the count value of the up / down counter 45 exceeds the lock determination range specified by the CNT signal from the register 46 in the positive direction. In other words, when the delay of the read clock with respect to the read data becomes larger than the predetermined frequency, the level becomes H level.

The SIG_G signal goes high when the count value of the up / down counter 45 exceeds the lock determination range in the negative direction. In other words, when the read clock for the read data advances more than the predetermined frequency, it goes to the H level. Therefore, SIG_
When both the F signal and the SIG_G signal are at the L level, it is determined that the lock point is within the lock determination range and has converged to a desired range. The SIG_F signal, SIG_G signal and SIG_H signal generated by the up / down counter 45 are sent to the register 46.

The register 46 has a counter reset RST
Up / down counter 4 in synchronization with the rise of one signal
5, SIG_F signal, SIG_G signal and SIG_
Latch the H signal. The register 46 latches a control signal sent from the microcomputer 24 via the CPU interface 18 and sends it to the up / down counter 45 as a CNT signal. This CNT signal
As described above, it is used to specify the lock determination range.

Next, the operation of the jitter detector according to the second embodiment will be described. The microcomputer 24
Prior to operating this jitter detection device, a control signal is sent to the register 46 via the CPU interface 18 to set a lock determination range in the up / down counter 45. In the lock point corrector 40 'of the jitter detector according to the second embodiment, the SIG_D signal and the SI
The operation until the G_E signal is generated is the same as the operation of the first embodiment.

The up / down counter 45 is provided by
As shown in (H), count-up and count-down are repeated in response to the SIG_D signal and the SIG_E signal. In this state, as shown in FIG.
When the counter reset RST1 signal is supplied via the counter, the value “c + 3” of the up / down counter 45 is synchronized with the rising of the counter reset RST1 signal.
Is latched in the register 46 as shown in FIG. After that, the up / down counter 45 changes to the state shown in FIG.
As shown in (H), after being cleared by the first pulse of the SIG_D signal, counting up is restarted in response to the pulse of the SIG_D signal.

Although not shown, when the pulse of the SIG_E signal is inputted after the rise of the counter reset signal RST1, this counter reset signal R
In synchronization with the rise of the ST1 signal, the up / down counter 45 counts down in response to the pulse of the SIG_E signal after being cleared by the first pulse of the SIG_E signal. The microcomputer 24 outputs the SIG_F signal, the SIG_G signal, and the SIG_H signal latched in the register 46 to the CPU interface 18 at a timing immediately before outputting the counter reset RST1 signal.
Ingest through.

Then, the microcomputer 24 calculates S
If the IG_F signal is at the H level, it recognizes that the read clock is behind the read data, generates oscillation control data for increasing the oscillation frequency in the oscillator 33, and generates an oscillator control register via the CPU interface 18. Set to 33a. Accordingly, the phase loop is controlled so that the change edge of the read data approaches (overlaps) the falling edge of the read clock.

If the SIG_G signal is at the H level, it recognizes that the read clock is advanced with respect to the read data, and generates oscillation control data for lowering the oscillation frequency of the oscillator 33.
Is set in the oscillator control register 33a via Accordingly, the phase loop is controlled so that the change edge of the read data approaches (overlaps) the falling edge of the read clock.

Further, if both the SIG_F signal and the SIG_G signal are at the L level, it is recognized that the change edge of the read data and the falling edge of the read clock are within a predetermined range and the lock point correction is completed, and the edge is recognized. Start detection.

[0106]

As described in detail above, according to the present invention,
It is possible to provide a jitter detection device and a jitter detection method for an optical disk device that can specifically detect mechanical jitter caused by the structure of the optical disk device. Further, it is possible to provide a jitter detection device and a jitter detection method of an optical disk device that can detect jitter generated in read data from an optical disk at a desired frequency.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of an optical disc device to which a jitter detection device according to a first embodiment of the present invention is applied.

FIG. 2 is a block diagram showing a configuration of an optical disc jitter detecting apparatus according to Embodiment 1 of the present invention.

FIG. 3 is a timing chart for explaining an operation of lock point correction of the optical disc jitter detection device according to the first embodiment of the present invention.

FIG. 4 is a diagram for explaining a range in which jitter appears in the optical disc jitter detection device according to the first embodiment of the present invention.

FIG. 5 is a timing chart for explaining an operation of jitter detection of the optical disk jitter detection device according to the first embodiment of the present invention.

FIG. 6 is a timing chart for explaining an operation of the lock point correction of the jitter detector according to the first and second embodiments of the present invention.

FIG. 7 is a block diagram illustrating a configuration of an optical disc device to which a jitter detection device according to a second embodiment of the present invention is applied.

[Explanation of symbols]

 Reference Signs List 1 optical disk 10 spindle motor 11 optical pickup 12 actuator 13 RF amplifier 14 EFM comparator 15 PLL circuit 16 decoder 17 memory controller 18 CPU interface 19 main controller 20 digital servo processor 21 driver 22 buffer RAM 23 personal computer 24 microcomputer 30 common control unit 31 Frequency comparator 31a Frequency comparator control register 32 Phase comparator 32a Phase comparator control register 33 Oscillator 33a Oscillator control register 34 Divider 35-37 Flip-flop 38 ENOR gate 40 Lock point corrector 41 Gate circuit 42 Counter U 42A, 44A, 46, 55A Register 43 NOR gate 44 Counter D 45 Up / down counter 50 Jitter detector 51 3-input AND gate 52 2-input AND gate 53 Low-pass filter 54 Schmitt circuit 55 Counter

Claims (8)

[Claims] 1. A PLL circuit for generating a read clock phase-locked so as to synchronize with a change edge of read data read from an optical disk, wherein an edge of the read clock and a change edge of the read data occur simultaneously. A lock point correction circuit that corrects a phase lock point of the PLL circuit, and a jitter detection circuit that detects jitter of the read data after the phase lock point is corrected by the lock point correction circuit. Jitter detection device for optical disk devices. 2. The PLL circuit includes: a phase comparator that compares a phase of the read data with a phase of the read clock; and an oscillator that changes a frequency of the read clock according to a comparison result of the phase comparator.
The optical disk according to claim 1, comprising an LL loop, wherein the lock point correction circuit corrects a phase lock point of the PLL circuit by supplying oscillation control data for changing an oscillation frequency of the oscillator to the oscillator. Jitter detection device. 3. The lock point correction circuit includes: a phase delay period in which the phase of the read clock is delayed with respect to the read data; and a phase advance period in which the phase of the read clock is advanced with respect to the read data. A first counter that counts a change edge of the read data when the detection circuit detects that the phase delay period has occurred, and that the detection circuit has the phase advance period. And a second counter that counts a change edge of the read data when is detected. If a difference between the value of the first counter and the value of the second counter is larger than a predetermined value, By supplying the corresponding oscillation control data to the oscillator, the point of the phase lock is corrected, and if within the predetermined value, the point of the phase lock is corrected. Jitter detection device of an optical disk according to claim 2 for determining that the. 4. The jitter detection circuit counts a pulse generated when a change edge of the read data deviates from an edge of the read clock in a state where the phase lock point is corrected by the lock point correction circuit. And a clearing means for clearing the value of the counter at an arbitrary cycle, wherein the value of the counter immediately before being cleared by the clearing means is detected as a jitter amount. Item 2. The optical disc jitter detecting device according to item 1. 5. A read clock phase-locked to be synchronized with a changing edge of read data read from an optical disk, wherein the generated edge of the read clock and the changing edge of the read data occur simultaneously. A jitter detection method for an optical disk device, wherein the jitter of the read data is detected after the phase lock point is corrected. 6. The step of generating the read clock, comprising: comparing a phase of the read data with a phase of the read clock; and changing a frequency of the read clock in accordance with a result of the comparison. The method according to claim 5, wherein the step of correcting the phase lock point further comprises: changing the frequency of the read clock based on oscillation control data for changing an oscillation frequency. An optical disk jitter detection method. 7. The step of correcting the phase lock point includes: a phase delay period in which the phase of the read clock is delayed with respect to the read data; and a phase of the read clock that is advanced with respect to the read data. A phase advance period is detected, and when it is detected that the phase is a phase delay period, a change value of the read data is counted to calculate a first value, and the phase advance period is detected. In this case, a change value of the read data is counted to calculate a second value. If a difference between the first value and the second value is larger than a predetermined value, the oscillation control according to the difference is performed. 7. The optical disc jitter detecting method according to claim 6, wherein the phase lock point is further corrected based on the data, and if the phase lock point is within the predetermined value, it is determined that the phase lock point has been corrected. 8. The step of detecting the jitter of the read data includes the steps of: generating a pulse generated by shifting a change edge of the read data from an edge of the read clock in a state where the phase lock point is corrected; 8. The optical disc jitter detecting method according to claim 5, wherein counting is performed for each cycle, and the count result is detected as a jitter amount for each cycle.