JP2001273351A - Device and method for verifying multi-cycle path and computer readable storage medium with verification program stored therein - Google Patents

Abstract

PROBLEM TO BE SOLVED: To easily and quickly verify whether a multi-cycle path is correctly designated by a designer. SOLUTION: This device includes an RTL(register transfer level) timing analysis part 102 which analyzes the circuit description of RTL and detects a multi-cycle path candidate whose delay covering its start point through end point exceeds a clock cycle or not and a check part 103 which collates the multi-cycle path candidate with the multi-cycle path/false path that is designated for analyzing the gate level timing.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital circuit design, and more particularly, to a circuit including a multi-cycle path in RTL.
(Register transfer level), and then to a technique of converting to a gate level circuit.

[0002]

2. Description of the Related Art Conventionally, when a circuit is designed by RTL and then converted to a gate-level circuit, timing analysis is not performed in RTL, and timing analysis is performed after conversion to a gate-level circuit.

FIG. 23 is a flowchart showing the flow of processing in the conventional design method, and FIG. 24 is a flowchart showing the flow of data in the conventional design method.

As shown in FIGS. 23 and 24, the conventional gate-level timing analysis alone cannot check whether the multi-cycle path specified by the designer is correct. Was doing.

FIG. 23 is described in detail below.

In the case where a multi-cycle path exists in the circuit, in order to correctly obtain the simulation result at the cycle boundary, in the RTL design process of S2301,
It is necessary to specify a delay time that exceeds the clock cycle as a total in a multi-cycle path. Typically, set the delay time required for the assignment statement. RTL design process (S23
01), whether the delay time for the multi-cycle path is set correctly or not is determined in the test design process (S230).
In 2), it is determined whether or not the test pattern is correctly designed by performing a simulation (S2303), and checking whether or not the simulation result matches the operation expected by the designer (S2304).

If the operation does not match the expected operation, RT
Correct L, test pattern, delay time (S230
5).

If the operation matches the expected operation, S2306
Specify the timing to create with, specify the multi-cycle path,
The RTL circuit is converted into a gate-level circuit by logic synthesis or manual conversion while following the false path specification (S2307). Hereinafter, the step of S2307 may be referred to as logic synthesis.

The timing designation means designation of an arrival time of an input signal, an expected value of a time delay of an output signal, and a rise / fall and a cycle of a clock signal. It is necessary to create a gate circuit from RTL with a logic synthesis tool. It is also needed for gate-level timing analysis tools.

In S2308, a detailed timing analysis is performed on the gate-level circuit created in S2307 with reference to the timing designation, multi-cycle path designation, and false path designation created in S2306.
At this time, the path specified as the multi-cycle path is
Even if the path delay exceeds the clock cycle, it does not cause a timing violation unless the path delay exceeds the specified clock number times the cycle cycle. A path specified as a false path is not subject to timing analysis for path delay. S23
At 09, it is checked whether there is a timing violation.
If there is a timing violation, the RTL, timing specification, multi-cycle path specification, and false path specification are corrected (S2310). If there is no timing violation, it leads to a post-process such as a layout operation.

Next, FIG. 24 will be described.

A simulation is performed using the test pattern D2402 for the RTL design data D2401 (S2303), and a simulation result D2404 is obtained. After confirming that the simulation result D2404 matches the expected value, using the constraint file D2405 relating to the timing specification, false path specification, and multi-cycle path specification, the RTL circuit is converted to the gate level by logic synthesis or manual conversion. Convert to circuit (S
2307), gate level design data D2407 is obtained. A gate level timing analysis is performed using the gate level design data D2407 and the constraint file D2405 (S2308), and a timing analysis result report D
2409 is obtained.

R specified by RTL design data D2401
Delay time for multi-cycle path included in TL circuit and designation of multi-cycle path and false path D24
05 has a relationship but has not been verified by inter-comparison. Therefore, if the designer mistakenly specifies a multi-cycle path, an incorrect inspection is performed in the gate level timing analysis (S2308). In some cases, a product is manufactured and the product does not operate at the expected frequency.

[0014]

A description will be given of the designation of the delay time in the RTL. In the gate-level circuit, the physical structure of each cell for realizing functions such as flip-flops and ANDs is determined, and the delay time unique to the cell is determined. On the other hand, in the RTL, since the degree of abstraction is high, the physical structure for realizing the function is not determined, so the delay time is not determined. Therefore, the delay time used by the designer in RTL is not considered to be the actual signal delay, but rather a delay time for making it easy to understand the order in which signals are calculated or an estimated signal delay for roughly estimating the result of logic synthesis. Can be

FIG. 25 shows a delay assignment table for the RTL circuit. As shown in FIG. 25, when performing a simulation with RTL, there are various combinations of how to give a delay time. When the parts other than the multi-cycle path are combined into a gate, the delay times of the parts estimated to be combined with the flip-flop, the latch, and the combinational circuit are all set to 0 delay (first column from the top). In the case where the portion that is estimated to be combined with the flip-flop and the latch has a unit delay and the portion that is estimated to be combined with the combinational circuit has a zero delay (the second column from the top), In the case where all the portions estimated to be combined with the loop, the latch, and the combinational circuit are set to the unit delay (third column from the top), three types are usually used.

All the parts estimated to be combined with the flip-flop, the latch, and the combinational circuit are 0.
In the case of a delay (first column from the top), since the delay time from the flip-flop or latch to the next-stage flip-flop or latch is 0, whether the total delay time exceeds the clock cycle specified in the simulation. There is an advantage that there is no need to check, but there are drawbacks that the number of logical stages cannot be estimated due to the delay time, and that racing tends to occur.

In the case where the portion estimated to be combined with the flip-flop and the latch is a unit delay, and the portion estimated to be combined with the combinational circuit is 0 delay (the second column from the top), Since the delay time from the first stage to the next flip-flop or latch is a unit delay,
Although there is an advantage that it is not necessary to check whether the total of the delay times exceeds the clock cycle and that racing is unlikely to occur, there is a disadvantage that the number of logic stages cannot be estimated from the delay time.

In the case where all the parts estimated to be combined with the flip-flop, the latch, and the combinational circuit are unit delays (third column from the top), it is possible to estimate the number of logic stages only by looking at the delay time. However, there is a disadvantage that it is necessary to check whether the total delay time exceeds the clock cycle.

R including an n-cycle multi-cycle path
There are two methods for ensuring that the signal change at the cycle boundary of the TL circuit is the same as that of the gate-level circuit after synthesis. The first method (fourth column from the top) is that the delay time of a part that is estimated to be combined into a combinational circuit and that corresponds to a multi-cycle path is (n−1) as a total.
This is a method of expressing a multi-cycle path by designating a delay time that is greater than x clock cycle and smaller than nx clock cycle. The second method (fifth column from the top) is a method of inserting n-1 virtual flip-flops or latches in a portion that is estimated to be combined into a combinational circuit and that corresponds to a multi-cycle path. Here, n is an integer of 2 or more.

The first method of expressing the multi-cycle path by designating the sum of the delay times to be larger than (n-1) × clock period and smaller than n × clock period requires that the circuit need not be changed. There are advantages.

The second method of inserting n-1 virtual flip-flops or latches has the advantage that there is no need to specify a delay time, but a virtual flip-flop different from the actual RTL circuit is used. Or RTL with inserted latch
It has the disadvantage of having to create and maintain circuits.

An RTL circuit is usually created with a delay time of 0 delay or a fixed unit delay except for a multi-cycle path. When a delay other than 0 is added to the combinational gate, when the combinational gate is combined with the flip-flop or the latch through the part estimated to be combined with the combinational circuit, In the path up to the estimated portion and other than the multi-cycle path, the sum of all delays must be smaller than the clock period.

However, conventionally, the designer has not checked the above-mentioned restrictions on the RTL circuit. If the test pattern does not happen to activate a path having a delay time larger than the clock cycle, the above problem cannot be found by RTL simulation, and the logic pattern is converted to a gate-level circuit after logic synthesis. There was a problem of being discovered.

[0024]

Means for Solving the Problems The first invention is (1) R
An RTL timing analysis unit that analyzes a circuit description of the TL and detects a multi-cycle path candidate in which a delay from a start point to an end point exceeds a clock cycle; (2) the multi-cycle path candidate; And a check unit for comparing the multi-cycle path designation and the false path designation designated for the timing analysis with each other.

A multi-cycle path candidate is a path that is known to take more than one cycle to transmit a signal, and includes a false path, and thus may include more paths than an actual multi-cycle path. . For this reason, the multi-cycle path is referred to as a “candidate”.

The multi-cycle path designation means a path designated as a path having a signal transmission time longer than one cycle for a logic synthesis tool or a gate level timing analysis tool. Each tool does not signal an error if the transmission time of a signal greater than one cycle is calculated for a multi-cycle path designation.

The false path designation means a path designated as a path which does not need to transmit a signal in a practical use state to a logic synthesis tool or a gate level timing analysis tool. Each tool does not perform a timing check on false path designation.

According to a second aspect of the present invention, (1) an RTL for analyzing a circuit description of an RTL and detecting a multi-cycle path candidate in which a delay from a start point to an end point exceeds a clock cycle.
A timing analyzer, (2) a gate-level timing analyzer that analyzes a gate-level circuit description to detect a timing violation path at the gate level, and (3) the multi-cycle path candidate and the gate-level timing violation. And a check unit for comparing the path with the path.

According to a third aspect of the present invention, (1) an RTL for analyzing a circuit description of an RTL and detecting a multi-cycle path candidate in which a delay from a start point to an end point exceeds a clock cycle.
A timing analyzer, (2) a gate-level timing analyzer that analyzes a gate-level circuit description to detect a timing violation path at the gate level, and (3) the multi-cycle path candidate and a gate-level timing analysis. And a check unit for comparing the multi-cycle path designation / false path designation designated for this purpose with the gate level timing violation path.

The check unit of the first invention compares (a) a multi-cycle path candidate with (b) a multi-cycle path specification / false path specification specified for gate-level timing analysis.

The check unit of the second invention compares (a) a multi-cycle path candidate with (c) a gate level timing violation path.

The check unit according to the third aspect of the present invention includes (a) a multi-cycle path candidate, (b) a multi-cycle path designation / false path designation designated for gate level timing analysis, and (c) a gate level designation. Compare and compare timing violation paths.

According to a fourth aspect of the present invention, (1) an RTL for analyzing a circuit description of an RTL and detecting a multi-cycle path candidate in which a delay from a start point to an end point exceeds a clock cycle.
A timing analysis step; and (2) a check step of comparing and comparing the multi-cycle path candidate with a multi-cycle path designation / false path designation designated for gate-level timing analysis. .

According to a fifth aspect of the present invention, (1) an RTL for analyzing a circuit description of an RTL and detecting a multi-cycle path candidate in which a delay from a start point to an end point exceeds a clock cycle.
A timing analysis step, and (2) a gate level timing analysis step of analyzing a gate level circuit description to detect a timing violation path at the gate level.
(3) A check step of comparing the multi-cycle path candidate with the gate-level timing violation path for comparison.

According to a sixth aspect of the present invention, (1) an RTL for analyzing a circuit description of an RTL and detecting a multi-cycle path candidate whose delay from a start point to an end point exceeds a clock cycle.
A timing analysis step, and (2) a gate level timing analysis step of analyzing a gate level circuit description to detect a timing violation path at the gate level.
(3) a check step of comparing the multi-cycle path candidate with a multi-cycle path designation / false path designation designated for gate-level timing analysis and the gate-level timing violation path. Features.

According to a seventh aspect of the present invention, (1) an RTL for analyzing a RTL circuit description and detecting a multi-cycle path candidate in which a delay from a start point to an end point exceeds a clock cycle.
Causing the computer to execute a timing analysis step, and (2) a check step of comparing the multi-cycle path candidate with a multi-cycle path specification / false path specification specified for gate-level timing analysis. Features.

According to an eighth aspect of the present invention, (1) an RTL for analyzing a circuit description of an RTL and detecting a multi-cycle path candidate in which a delay from a start point to an end point exceeds a clock cycle.
A timing analysis step, and (2) a gate level timing analysis step of analyzing a gate level circuit description to detect a timing violation path at the gate level.
And (3) causing a computer to execute a check step of comparing the multi-cycle path candidate with the gate level timing violation path.

According to a ninth aspect of the present invention, (1) an RTL for analyzing a circuit description of an RTL and detecting a multi-cycle path candidate in which a delay from a start point to an end point exceeds a clock cycle.
A timing analysis step, and (2) a gate level timing analysis step of analyzing a gate level circuit description to detect a timing violation path at the gate level.
(3) The computer executes a check step of comparing the multi-cycle path candidate with a multi-cycle path designation / false path designation designated for gate-level timing analysis and the gate-level timing violation path. It is characterized by making it.

[0039]

Embodiments of the present invention will be described below with reference to the drawings.

(1) First Embodiment FIG. 1 is a functional block diagram showing a hardware configuration of a first embodiment of the present invention, and FIG. 2 exemplifies peripheral devices connected to the RTL timing analysis unit 102 in FIG. FIG. 3 and FIG.
FIG. 4 is a diagram showing an example of peripheral devices connected to a gate level timing designation and RTL timing analysis result matching check unit 103. FIG. 4 is a flowchart showing a processing flow in the multi-cycle path verification method according to the first embodiment. FIG. 5 is a flowchart showing a data flow in the verification method.

As shown in FIG. 1, the multi-cycle path verification apparatus according to the first embodiment includes an RTL simulation unit 101, an RTL timing analysis unit 102, a gate level timing designation and a RTL timing analysis result matching check unit 103. , A logic synthesis unit 104, and a gate level timing analysis unit 105.

The RTL simulation unit 101 performs the
The configuration and operation of the functional block created by the L design are verified using a test pattern.

The RTL timing analysis unit 102 and the matching check unit 103 for specifying the gate level timing and the RTL timing analysis result will be described later.

The logic synthesis unit 104 converts the given RTL description into a gate level description.

The gate level timing analyzer 105
Analyze the gate level description and detect timing violation paths.

As shown in FIG. 2, another system 201 such as an RTL simulator and a monitor 2 for displaying an RTL timing analysis result
04, printer 205 for printing out RTL timing analysis results, RTL necessary for RTL timing analysis
A tape 206 and a disk 207 for storing descriptions are connected. The RTL timing analysis unit 102 outputs a C
It is composed of PU, ROM, RAM, cache memory, bus and the like.

As shown in FIG. 3, the matching check unit 103 includes another system 3 such as an RTL simulator.
01, monitor 30 for displaying the result of the matching check
4. A printer 305, a tape 306, and a disk 307 for printing out the results of the matching check are connected. The tape 306 and the disk 307 store multi-cycle path candidates obtained as a result of RTL timing analysis, gate-level timing specification, multi-cycle path specification, and false path specification. The matching check unit 103 also includes a CPU, a ROM, a RAM (not shown),
It is composed of a cache memory, a bus and the like.

The RTL timing analysis unit 102 and the matching check unit 103 may be separate hardware or may be the same hardware.

The design flow will be described with reference to FIG.

An RTL circuit is designed (S401), and a test pattern is designed (S402). The RTL circuit created in S401 and the test pattern created in S402 are input to the RTL simulation unit 101,
An RTL simulation is performed (S403). It is checked whether the simulation result matches the expected operation (S404). If the result does not match, the RTL or test pattern is corrected (S405).
The L timing analysis is performed (S406).

Using the RTL timing analysis unit 102,
A TL timing analysis is performed (S406), and a path in which the total delay time along the path exceeds the clock cycle is output as a multi-cycle path candidate D407.

Further, a timing specification, a multi-cycle path specification, and a false path specification are created (S408), and the multi-cycle path candidate D407 is matched with the multi-cycle path specification and the false path specification to determine whether the specification in S408 is correct. It is checked whether it is (S413).

The specific contents of the check are (1) D407
Is included in the multi-cycle path designation or false path designation in S408, and (2) the multi-cycle path designation in S408 is D4
07 is included in the multi-cycle path candidate of 07,
(3) The number of those multicycles. If a problem is found in S413, the RTL design in S401 or
Correct the multi-cycle path and false path designation in S408. If no problem is found in S413, S
According to the timing specification, multi-cycle path specification, and false path specification created in step S408, the RTL is set in step S409.
Is converted into a gate-level circuit by logic synthesis or manually. For the gate-level circuit, detailed gate-level timing analysis is performed in S410 based on the timing in S408, multi-cycle path designation, and false path designation. In S411, the result of the gate-level timing analysis is checked. If there is a timing violation in S411, the RTL, test pattern, timing specification, multi-cycle specification, and false path specification are corrected in S412. If there is no timing violation in S411, the process proceeds to a post-process such as layout.

The data-centric flow will be described with reference to FIG.

A simulation is performed using the RTL design data D501 and the test pattern D502 (S40).
3) Obtain a simulation result D504. After the simulation result D504 matches the expected result, R
The RTL timing analysis is performed based on the TL timing designation D505 (S406), and the multi-cycle path candidate D
407 are obtained. The false path specification and the multi-cycle path specification of the constraint file D507 are matched with the multi-cycle path candidate D407 to check whether there is any problem (S413). Using the constraint file D507 for specifying timing, false path, and multi-cycle path,
Perform logic synthesis or manual conversion to gate level (S40)
9) Obtain gate level design data D509. Timing analysis is performed using the constraint file D507 and the gate level design data D509 (S410), and a timing analysis result report D511 is obtained.

FIG. 6 shows a flow of the RTL timing analysis, FIG. 8 shows an example of a circuit for performing the RTL timing analysis, and FIG. 9 shows Ve estimated to be synthesized into a flip-flop.
An example of a rilog description is shown.

In step S601, a set of starting points for RTL timing analysis is found. A variable on the left side of an external input or an assignment statement in a portion where a flip-flop or a latch is estimated to be synthesized is a start point of the timing analysis. FIG. 9 as an example
Is the start point of the timing analysis. That RT
Assuming that there are a plurality of starting points of the L timing analysis in the circuit,
The set is called a set of starting points of the RTL timing analysis. In FIG. 8, {Clk, In1, In2, A, Out2,} is a set of the start points of the RTL timing analysis.

In step S602, an unanalyzed point is arbitrarily selected from the set of signals at the start point of the RTL timing analysis in step S601, and is set as the current search start point. As an example, in FIG. 8, A is selected and is set as the starting point of the current search.
At this time, A already has a delay of 1 from Clk.

At S603, the starting point selected at S602 is set as a set of search signals. In the previous example, it would be {A}.

In step S604, a search is made for a signal in the set of the current search signal that appears on the right side of the assignment statement or the condition signal of the conditional statement. For example, in FIG. 8, an assignment statement 805 is found for the search signal A.

In S605, the delay time of the assignment statement is added to the delay time of the path. That is, the delay time of the assignment statement is added to the total delay time of the path from the start point specified in S602 to the assignment statement found in S604, and the signal from the start point specified in S602 to the signal appearing on the left side of the assignment statement is added. Path delay time. For example, in 805 of FIG. 8, the delay from A to A2 is 2, and the delay from Clk is 3. Thereafter, execution proceeds, and the search signal of A2 is applied to S604.
The conditional statement 8031 in the block of the assignment statements 8021 and 803 in 802 is found. A2 → B from the assignment statement of 8021
Is 15, the total delay of A → A2 → B is 2 + 15 = 17, and the delay from Clk is 18.

In S605, if the condition of the conditional statement found in S604 is satisfied or not, the delay time of each assignment statement included in each block is calculated from the start point specified in S602 to the conditional statement. In addition to the total path delay time, the path delay time up to the signal appearing on the left side of the assignment statement is set. For example, in FIG.
Since the delay of A2 → Out1 is 1, A → A2 → Out1 is 2 + 1
And the delay from Clk is 4. In 8033, since the delay of A2 → Out1 is 2, A → A2 → Out1 is 2+
2 and 4 and 5 with the delay from Clk.

In S612, the current search signal is removed from the set of search signals. In the example of FIG. 8, when the search for the set of search signals is completed in the set {A} in S604, the set of search sets becomes the empty set ｛｝.

In step S606, the signal appearing on the left side of the assignment statement in step S605, or the signal appearing on the left side of the assignment statement included in each block when the condition of the conditional statement is satisfied or not satisfied, is the starting point of the RTL timing analysis. Check whether it is or external output. For example, the signal B on the left side of 8021 in FIG. 8 is neither a start point of the RTL timing analysis nor an external output. On the other hand, Ou on the left side of 8032 and 8033
t1 is an external output.

If it is found in S606 that neither the start point of the RTL timing analysis nor the external output is present, in S607,
If the signal appearing on the left side of the assignment statement in S605 or the condition of the conditional statement is satisfied or not satisfied, the signal appearing on the left side of the assignment statement included in each block is added to the set of search signals, and the process returns to S604. For example, in FIG.
After searching for A, add A2 to the set.

If it is determined in step S606 that the output is the start point of the RTL timing analysis or an external output, the process proceeds to step S608.
It is checked whether the delay from the start point to the end point or the external output exceeds the clock cycle, and if so, along with information on the number of multi-cycle paths, S6
Report at 09. For example, in FIG. 8, for the search signal of B, Out2 is the start point of the RTL timing analysis in 8041, so the process proceeds to S608. At this time, the path is A → A
2 → B and the delay is 17 and the delay from Clk is 18
Becomes If the clock cycle is 10, this path is a two-cycle multi-cycle path. At S610,
Check if there is a signal to search in the set of search signals.

If it is determined in S610 that there is still a signal to be searched, the process returns to S604. If it is determined in S610 that there is no more signal to be searched, then S611 is further performed.
If it is determined that there is no more start point of the RTL timing analysis that has not been searched yet, the RTL timing analysis ends.

Next, the matching check (S413) in FIGS. 4 and 5 will be described with reference to FIG.

First, the multi-cycle path candidate D407, which is the result of the RTL timing analysis, is stored (S70).
1).

Next, the timing specification, false path specification, and multi-cycle path specification in the constraint file D507 are stored (S702).

Next, the gate-level multi-cycle path designation is developed so as to include all intermediate nodes that pass through. For example, when inA → outA is specified as a multi-cycle path, the data is expanded to include all intermediate nodes na1, na2, and na3 that pass from inA to outA. Then, the developed multi-cycle path is stored.
For example, it is stored in the form of inA → na1 → na2 → na3 → outA (S703).

Next, a gate-level false path specification is developed to include all intermediate nodes that pass through.
For example, if inB → outB is specified as a false path, the path is expanded to include all intermediate nodes nb1, nb2, and nb3 that pass from inB to outB. Then, the false path after expansion is stored. For example, inB
→ na1 → na2 → na3 → outB (S70
4).

Next, it is checked whether the gate-level multi-cycle path in the constraint file D507 is included in the multi-cycle path candidate D407 for the RTL timing analysis (S705).

The gate-level multi-cycle path in the constraint file D507 is a multi-cycle path candidate D40.
If the RTL is not included, it reports that the designation of the gate-level multi-cycle path is wrong or that the RTL is wrong (S707).

The gate-level multi-cycle path in the constraint file D507 is a multi-cycle path candidate D40.
7, the multi-path path candidate D407 of the RTL timing analysis is checked whether it is included in the expanded multi-cycle path and the false path at the gate level (S708).

The gate-level multi-cycle path in the constraint file D507 is a multi-cycle path candidate D40.
Also, if it is not included, the multi-path path candidate D407 of the RTL timing analysis is checked whether it is included in the expanded multi-cycle path and the false path at the gate level (S708).

If the multi-cycle path candidate D407 is not included in the gate-level expanded multi-cycle path and the false path, it reports that the multi-cycle path and false path designation are insufficient (S710).

If the multi-cycle path candidate D407 is included in the multi-level path and the false path where the gate level has been developed, the matching check is terminated.

If the multi-cycle path candidate D407 is not included in the gate-level expanded multi-cycle path and the false path, the matching check is terminated.

FIG. 9 shows an example of a Verilog description in which a flip-flop is estimated as a result of logic synthesis. In the example of FIG. 9, the assignment to out1 is performed at the rising edge of the clk signal.
It can be estimated that this is combined with a flip-flop that stores data at the rising edge of the clk signal. FIG. 10 shows an example of an equivalent VHDL.

FIG. 11 shows an example of a Verilog description in which a latch is estimated as a result of logic synthesis. When the clk symbol is high, in
The change of 1 is transmitted to out1, but when the clk signal is low, the output of out1 is held. This is consistent with the operation of the latch. V
FIG. 12 shows an example of the HDL.

FIG. 13 shows a Verilog description example in which synthesis into a combinational circuit is estimated. In the always sentence B1301,
When the signal of a or b changes, the and of a and b are evaluated and substituted into the signal c. This is consistent with the operation of the and gate. In the assign statement A1302, when the signal of d or e changes, the or of d and e is evaluated and assigned to the signal f. FIG. 14 shows an example of an equivalent VHDL.

FIG. 15 shows Verilog of RTL timing analysis.
Here is an example. The synthesis of the always sentence B1501 to the flip-flop is estimated, and out1 is the start point of the RTL timing analysis. Considering the path from the clock, Clk → out1
Becomes The assignment statement A1502 is estimated to be synthesized into a combination gate. In A1502, the delay time 15 is specified. It is estimated that the always statement B1503 is synthesized into a flip-flop. Therefore, this pass is completed by substituting the signal In2 for the signal Out2. The delay of Clk → Out1 → In2 is 15. In T1304, since the clock cycle is 10, this path is a two-cycle multi-cycle path. FIG. 16 shows a description obtained by rewriting the Verilog description of FIG. 15 in VHDL.

As shown in the delay table 1504 in FIG. 15, if the cycle time of the clock in the RTL is 10, the number of paths from Clk to Out1 to In2 is 15, so that it is a two-cycle multicycle path.

By applying the present invention, if a delay other than 0 is added to the combinational circuit, it is early checked whether the sum along a path other than the multi-cycle path accidentally exceeds the clock period. be able to.

FIG. 17 does not show a multi-cycle path.
An example of an RTL exceeding a clock cycle due to a delay in a combinational circuit is shown. The always statement B1701 is estimated to be synthesized into a flip-flop. The path from clk to Sig1 is set as delay 1 and becomes the starting point of path analysis. assign
Statements A1702, A1703, A1704, A1705
In A1706, synthesis to the combination gate is estimated.
Therefore, the path delay of clk → Sig1 → Sig2 → Sig3 → Sig4 → Sig5 → Sig6 is 6. In the always statement B1707, the synthesis into the flip-flop is estimated, and this pass ends. Since the clock cycle is 5, clk → Sig1 → Sig2 → Sig3 → Sig
It can be seen that the path from 4 → Sig5 → Sig6 is a multi-cycle path or has a problem with the delay time. In this case, since it is not a multi-cycle path, there is a problem in the delay time, and it is understood that it is necessary to make the clock cycle longer than 6 or to modify the delay time so as to be shorter.

(2) Second Embodiment FIG. 18 is a functional block diagram showing a second embodiment of the hardware configuration of the entire system using the multi-cycle path verification device of the present invention. FIG. 19 is a diagram showing the gate level timing designation in FIG. And FIG. 20 is a diagram illustrating peripheral devices connected to a matching check unit 1803 for comparing the RTL timing analysis result and the gate level timing analysis result. FIG. FIG. 21 is a flowchart showing a data flow in the verification method.

As shown in FIG. 18, the multi-cycle path verification device according to the second embodiment includes an RTL simulation section 1801, an RTL timing analysis section 1802,
It comprises a matching check unit 1803 for specifying the gate level timing, the RTL timing analysis result, and the gate level timing analysis result, a logic synthesis unit 1804, and a gate level timing analysis unit 1805.

RTL simulation section 1801, RT
The L timing analysis unit 1802, the logic synthesis unit 1804, and the gate level timing analysis unit 1805
Since they are the same as the TL simulation unit 101, the RTL timing analysis unit 102, the logic synthesis unit 104, and the gate level timing analysis unit 105, the description is omitted.

The matching check unit 1803 for specifying the gate level timing, the RTL timing analysis result, and the gate level timing analysis result will be described later.

As shown in FIG. 19, the matching check unit 1803 includes another system 1901 such as an RTL simulator, a monitor 1904 for displaying the matching check result, a printer 1905 for printing out the matching checking result, a tape 1906 and a disk 190.
7 is connected. The tape 1906 and the disk 1907 include a multi-cycle path candidate obtained as a result of the RTL timing analysis, a gate-level timing specification, a multi-cycle path specification, a false path specification, and a timing violation path obtained as a result of the gate-level timing analysis. Is stored. The matching check unit 1803 also includes a CPU, ROM, RAM, cache memory, bus, and the like (not shown).

A design flow will be described with reference to FIG.

S2001 to S2006 and D2007
Are the same as S401 to S406 and D407 in FIG. 4, and a description thereof will be omitted.

A timing specification, a multi-cycle path specification, and a false path specification are created (S2008), converted into gate-level design data by logic synthesis or manually (S2009), and the timing specification, the multi-cycle path specification, the false path specification, and the like are performed. A gate-level timing analysis is performed using the gate-level design data (S2010). If an error exists, a timing analysis result report D2014 is created.

A multi-cycle path candidate D2007, a timing designation, a multi-cycle path designation, a false path designation, and a timing analysis result report D201
Then, it is checked whether or not the designation in S2008 is correct by matching 4 (S2013). Specific check contents will be described later.

In step S2011, the result of the gate-level timing analysis is checked. If there is a timing violation in S2011, the RTL, timing designation, multi-cycle designation, and false path designation are corrected in S2012. S
If there is no timing violation in 2011, the process proceeds to a post-process such as layout.

A data-centric flow will be described with reference to FIG.

A simulation is performed using the RTL design data D2101 and the test pattern D2102 (S2
003), and obtain a simulation result D2104. After the simulation result D2104 matches the expected result, RTL timing analysis is performed (S2006), and a multi-cycle path candidate D2007 is obtained. Using the timing specification, false path specification, and multi-cycle path specification of the constraint file D2107, logic synthesis or manual conversion to the gate level is performed (S2009), and the gate level design data D2109 is obtained. Constraint file D210
7 and the gate level design data D2109 to perform timing analysis (S2010), and obtain a timing analysis result report D2014. The false path specification and the multi-cycle path specification in the constraint file D2107 are compared with the multi-cycle path candidate D2007 and the timing analysis result report D2014 to check whether there is any problem (S2013).

Next, the matching check (S2013) in FIGS. 20 and 21 will be described with reference to FIG.

First, the multi-cycle path candidate D2007, which is the result of the RTL timing analysis, is stored (S220).
1).

Next, the timing specification, false path specification, and multi-cycle path specification in the constraint file D2107 are stored (S2202).

Next, the gate-level multi-cycle path designation is developed to include all the intermediate nodes that pass through. For example, when inA → outA is specified as a multi-cycle path, the data is expanded to include all intermediate nodes na1, na2, and na3 that pass from inA to outA. Then, the developed multi-cycle path is stored.
For example, it is stored in the form of inA → na1 → na2 → na3 → outA (S2203).

Next, the gate-level false path specification is developed to include all the passing intermediate nodes.
For example, if inB → outB is specified as a false path, the path is expanded to include all intermediate nodes nb1, nb2, and nb3 that pass from inB to outB. Then, the false path after expansion is stored. For example, inB
→ na1 → na2 → na3 → outB (S220)
4).

Next, it is checked whether or not the multi-cycle path in which the gate level has been expanded is included in the multi-cycle path candidate D2007 obtained as a result of the RTL timing analysis (S2205).

If the expanded multi-cycle path at the gate level is not included in the multi-cycle path candidate D2007, it is determined that the multi-cycle path specification or the false path specification at the gate level is wrong or the RTL is wrong. A report is made (S2207).

When the expanded multi-cycle path at the gate level is included in the multi-cycle path candidate D2007, the multi-cycle path candidate D2007 is included in the expanded multi-cycle path and the false path at the gate level. It is checked whether it is (S2208).

When the gate-level expanded multi-cycle path is not included in the multi-cycle path candidate D2007, the multi-cycle path candidate D2007 is
It is checked whether it is included in the expanded multi-cycle path and the false path at the gate level (S220)
8).

When the multi-cycle path candidate D2007 is not included in the gate-level expanded multi-cycle path and the false path, the path not included is included in the gate-level timing analysis result report D201.
It is checked whether an error is reported in No. 4 (S2210).

The path not included in S2209 is
If an error is reported in the gate-level timing analysis result, it reports that the multi-cycle path specification and the false path specification in the gate-level timing analysis are incorrect. Otherwise, it reports that the delays of the RTL and the gate are different (S2211), and ends.

Also, a multi-cycle path candidate D2007
Is included in the expanded multi-cycle path and the false path at the gate level, the matching check is terminated.

Further, a program for causing a computer to execute each step required in each of the above-described multi-cycle verification methods is recorded on a recording medium, and is read and executed by a computer. Can be realized. Here, examples of the recording medium include devices capable of recording a program, such as a memory device, a magnetic disk device, an optical disk device, and a magnetic tape device.

FIG. 26 is a schematic diagram showing an example of a computer system that reads a program stored in these recording media and implements a multi-cycle verification method according to the steps described therein. A floppy (registered trademark) disk drive 81 and a CD-ROM drive 82 are provided on the front of the main body of the computer system 80. A floppy disk 83 as a magnetic disk device or a CD-ROM 84 as an optical disk device is provided.
Is inserted from each drive entrance and a predetermined read operation is performed, whereby the programs stored in these recording media can be installed in the system. Also, by connecting a predetermined drive device, for example, a ROM 85 as a memory device used for a game pack or the like and a cassette tape 8 as a magnetic tape device are connected.
6 can also be used.

[0113]

According to the present invention, the following effects can be obtained.

In the design flow of designing a circuit by RTL and then converting it to a gate level circuit, (1) RTL
Verify whether the designer's designation of the multi-cycle path is correct by comparing the multi-cycle path candidate found by the timing analysis with (2) the set of the multi-cycle path and the false path specified for the gate-level timing analysis. can do.

That is, (condition 1) a path found as a multi-cycle path candidate by RTL timing analysis is included in a set of paths designated as a multi-cycle path or a false path for gate-level timing analysis. (Condition 2) that a path specified as a multi-cycle path for gate-level timing analysis is included in a set of paths discovered as a multi-cycle path candidate by RTL timing analysis. By verifying whether or not the condition is satisfied, it is possible to verify whether or not the multi-cycle path designation performed by the designer for the gate-level timing analysis is correct.

If the multi-cycle path is not specified correctly (if a path for which the multi-cycle path is not specified has a delay equal to or longer than the clock cycle), the simulation result of the gate-level circuit obtained by logically synthesizing the RTL is not correct. It may not be done. That is, the occurrence of a problem in the gate-level simulation after the logic synthesis can be predicted by the RTL timing analysis before the logic synthesis.

Also, by comparing (1) a multi-cycle path candidate found by RTL timing analysis with (2) a timing violation path found by gate-level timing analysis, the timing found by gate-level timing analysis is compared. It can be determined whether the offending path is a multi-cycle path.

More specifically, a true timing violation path is found by removing a multi-cycle path candidate found by RTL timing analysis from a set of paths found as timing violation in gate level timing analysis. Can be.

Further, by confirming that the number of cycles of the timing violation path discovered by the gate-level timing analysis matches the number of cycles of the multi-cycle path candidate discovered by the RTL timing analysis, it is possible to correctly determine the gate-level path. It can verify that the timing analysis has been performed.

[Brief description of the drawings]

FIG. 1 is a functional block diagram illustrating a hardware configuration according to a first embodiment of the present invention.

FIG. 2 is a diagram illustrating peripheral devices connected to an RTL timing analysis unit 102 in FIG. 1;

FIG. 3 is a diagram exemplifying peripheral devices connected to a matching check unit 103 for specifying a gate level timing and an RTL timing analysis in FIG. 1;

FIG. 4 is a flowchart showing a flow of processing according to the first embodiment of the present invention.

FIG. 5 is a flowchart showing a data flow in the first embodiment of the present invention.

FIG. 6 is a flowchart showing a flow of processing of RTL timing analysis of FIGS. 4 and 5;

FIG. 7 is a flowchart showing a flow of a matching check process in FIGS. 4 and 5;

FIG. 8 is a diagram illustrating an example of a circuit that performs the RTL timing analysis of FIG. 4;

FIG. 9: Verilo estimated to be synthesized into flip-flops
It is a figure showing the example of g description.

FIG. 10 is a diagram illustrating an example of a VHDL description corresponding to FIG. 9;

FIG. 11 is a diagram illustrating an example of a Verilog description in which synthesis into a latch is estimated.

FIG. 12 is a diagram illustrating an example of a VHDL description corresponding to FIG. 11;

FIG. 13: Verilo estimated to be synthesized into a combinational circuit
It is a figure showing the example of g description.

FIG. 14 is a diagram illustrating an example of a VHDL description corresponding to FIG. 13;

FIG. 15 is a diagram illustrating another example of a circuit that performs RTL timing analysis.

FIG. 16 is a diagram showing an example of a VHDL description corresponding to FIG.

FIG. 17 is a diagram illustrating an example of a circuit in which a path delay exceeds a clock cycle.

FIG. 18 is a functional block diagram illustrating a hardware configuration according to a second embodiment of the present invention.

19 is a diagram showing gate level timing designation and RT shown in FIG. 18;
It is a figure which illustrates the peripheral device connected to the matching check part 1803 of L timing analysis result and gate level timing analysis result.

FIG. 20 is a flowchart showing a flow of processing according to the second embodiment of the present invention.

FIG. 21 is a flowchart showing a data flow in the second embodiment of the present invention.

FIG. 22 is a flowchart showing a flow of a matching check process in FIGS. 20 and 21;

FIG. 23 is a flowchart showing the flow of a conventional process.

FIG. 24 is a flowchart showing a conventional data flow.

FIG. 25 is a delay assignment table for an RTL circuit.

FIG. 26 is a schematic diagram illustrating an example of a computer system that implements the multi-cycle verification method of the present invention.

[Explanation of symbols]

Reference Signs List 101 RTL simulation unit 102 RTL timing analysis unit 103 Matching check unit for specifying gate level timing and RTL timing analysis result 104 Logic synthesis unit 105 Gate level timing analysis unit

Claims (9)

[Claims] An RTL timing analysis unit for analyzing a circuit description of an RTL to detect a multi-cycle path candidate whose delay from a start point to an end point exceeds a clock cycle; Multi-cycle path specified for level timing analysis
A multi-cycle path verification device, comprising: a check unit that compares a false path specification with a false path specification. 2. An RTL timing analysis unit for analyzing a circuit description of an RTL to detect a multi-cycle path candidate in which a delay from a start point to an end point exceeds a clock cycle, and analyzes a gate-level circuit description. A multi-cycle path, comprising: a gate level timing analysis unit that detects a timing violation path at a gate level; and a check unit that compares the multi-cycle path candidate with the timing violation path for comparison. Verification device. 3. An RTL timing analysis unit for analyzing a RTL circuit description to detect a multi-cycle path candidate in which a delay from a start point to an end point exceeds a clock cycle, and analyzes a gate-level circuit description. A gate-level timing analysis unit that detects a timing violation path at a gate level; a multi-cycle path candidate; and a multi-cycle path designation / designation designated for gate-level timing analysis.
A multi-cycle path verification device, comprising: a check unit for comparing a false path specification with the timing violation path for comparison. 4. An RTL timing analysis step of analyzing a circuit description of an RTL to detect a multi-cycle path candidate in which a delay from a start point to an end point exceeds a clock cycle; Multi-cycle path specified for level timing analysis
A checking step of comparing against a false path specification. 5. An RTL timing analysis step for analyzing an RTL circuit description to detect a multi-cycle path candidate in which a delay from a start point to an end point exceeds a clock cycle, and analyzing a gate-level circuit description. A gate-level timing analysis step of detecting a timing violation path at a gate level; and a check step of comparing and comparing the multi-cycle path candidate with the gate-level timing violation path. Path validation method. 6. An RTL timing analysis step for analyzing a RTL circuit description to detect a multi-cycle path candidate in which a delay from a start point to an end point exceeds a clock cycle; and analyzing a gate-level circuit description. A gate-level timing analysis step of detecting a timing violation path at the gate level; and a multi-cycle path designation and multi-cycle path designation / designation specified for gate-level timing analysis.
A multi-cycle path verification method, comprising: checking a false path and comparing the path with the gate level timing violation path. 7. An RTL timing analysis step of analyzing a circuit description of an RTL to detect a multi-cycle path candidate in which a delay from a start point to an end point exceeds a clock cycle; Multi-cycle path specified for level timing analysis
A computer-readable recording medium having recorded thereon a multi-cycle path verification program, wherein the computer executes a check step of comparing against a false path specification. 8. An RTL timing analysis step of analyzing a circuit description of an RTL to detect a multi-cycle path candidate in which a delay from a start point to an end point exceeds a clock cycle; and analyzing a gate-level circuit description. Causing a computer to execute a gate level timing analysis step of detecting a timing violation path at a gate level, and a check step of comparing the multi-cycle path candidate with the gate level timing violation path for comparison. A computer-readable recording medium on which a multi-cycle path verification program is recorded. 9. An RTL timing analysis step for analyzing a circuit description of an RTL to detect a multi-cycle path candidate in which a delay from a start point to an end point exceeds a clock cycle; and analyzing a gate-level circuit description. A gate-level timing analysis step of detecting a timing violation path at the gate level; and a multi-cycle path designation and multi-cycle path designation / designation specified for gate-level timing analysis.
A computer-readable recording medium on which a multi-cycle path verification program is recorded, the program causing a computer to execute a false path designation and a check step of comparing the path with the gate level timing violation path.